JP2009159114A - Bit synchronization circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bit synchronization circuit for reproducing reception data by judging a synchronized state of the reception data without relying on a pattern of the reception data based on a burst signal. <P>SOLUTION: A continuous clock generating circuit generates an intra-device reference clock CLK to be used within the circuit, a Gate signal generating section 141 extracts a Gate signal synchronized with reception data based on a burst signal, and a phase oscillator 142 with Gate generates frequency-divided clocks G-VCOCK1 to G-VCOCKn obtained by frequency-dividing a clock of N phases obtained by dividing a bitwidth of the reception data into N (1<N, N is a natural number) while being phase-locked to the Gate signal. A synchronized state determining section 146 then determines a synchronized state of the reception data based on a result of latching the frequency-divided clocks G-VCOCK1 to G-VCOCKn with a frequency-divided clock CK1 obtained by frequency-dividing the intra-device reference clock CLK. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a bit synchronization circuit that samples and reproduces received data by a burst signal.

  In a point-to-multipoint communication system such as a PON (Passive Optical Networks) system in which a master station device (OLT: Optical Line Terminal) and a plurality of subscriber devices (ONU: Optical Network Unit) are connected by optical fibers, The distance and transmission path conditions differ between the station apparatus and the plurality of subscriber apparatuses. Therefore, burst signals, which are intermittent signals, are used at least for communication from the subscriber unit to the master station device so that signals received on the master station device side do not overlap.

  When transmitting data in the uplink transmission direction to the master station device, each subscriber device ensures that the data in the uplink transmission direction from other subscriber devices does not collide with the data in the uplink transmission direction transmitted by its own device. The data in the upstream transmission direction is transmitted in bursts by adjusting the timing.

  In the case of a continuous signal, a master station device that receives data can perform retiming of received data using a PLL (Phase Locked Loop) circuit or the like. However, in the PON system, as described above, the data in the upstream transmission direction is not a continuous signal but a burst signal, and the length of the optical fiber connecting each subscriber unit and the master station unit is as follows. Therefore, the phase of the bit position of the signal reaching the master station apparatus and the optical signal level are different for each subscriber apparatus.

  Therefore, each time the master station device receives data that is a burst signal, it establishes bit synchronization of the data within the preamble period added to the head of the received data and identifies the payload area by the subsequent delimiter pattern, Received data is processed based on the data signal after delimiter synchronization.

  As a representative technique of the above-described bit synchronization circuit, for example, a timing clock extraction system that extracts a timing clock from received data by a PLL (Phase Locked Loop), and latches the received data based on the extracted timing clock. An optimal phase data selection method that generates multiple data sequences with different phases and selects the data sequence with the most phase margin with respect to the reference clock in the device and performs data processing. There is known an optimum phase clock selection method that generates a clock, selects an internal clock having the most phase margin with respect to the phase of received data, and performs data processing.

  In the bit synchronization circuit using the optimum phase data selection method, the received data is sampled into an n-phase data string whose phase is shifted by 1 / n (n is a natural number) period of the in-device reference clock. Of the sampled n-phase sampled data strings, the optimum phase data string having the most phase margin with respect to the received data is selected, and the selected optimum phase data string is latched in synchronization with the reference clock in the apparatus and retimed. It outputs as a data string (for example, refer patent document 1 and patent document 2).

  The bit synchronization circuit using the optimum phase clock selection method generates an n-phase clock having a phase different by 1 / n cycle from an in-device reference clock having the same frequency as the received data, and the received n-phase clock generates the received data. Is sampled, the optimum phase clock having the most phase margin with respect to the received data is selected from the sampled n-phase sampling data string, and the received data is reproduced according to this optimum phase clock (for example, Patent Document 3-6).

  Since the bit synchronization circuit based on the timing clock extraction method requires a long preamble section for each burst data, a substantial decrease in transmission speed is caused in a PON system that performs high-speed transmission at gigabits per second or more. Therefore, in order to realize high-speed bit synchronization, a bit synchronization circuit using the optimum phase data selection method described in Patent Documents 1 and 2, or a bit synchronization circuit using the optimum phase clock selection method described in Patent Documents 3 to 6 Is promising.

  For example, ITU-T Recommendation G. In the PON system standardized by 984 and IEEE Recommendation 802.3ah, the data in the uplink transmission direction transmitted from the subscriber unit to the master station unit is variable length burst data, and the maximum burst length is several μs up to that time. It has been extended to a much longer time of about 1 ms. In consideration of effective transmission efficiency, when a higher speed system is introduced in the future (for example, 10G-PON system standardized by IEEE), the possibility that the burst length is shortened is very low.

  In the bit synchronization circuit based on the optimum phase data selection method described in Patent Documents 1 and 2, or the bit synchronization circuit based on the optimum phase clock selection method described in Patent Documents 3 to 6, the bit synchronization circuit is optimized once during the preamble reception period. When the phase is determined, bit synchronization of the received data is performed without changing the optimum phase data or the optimum phase clock during the burst data reception period. However, in systems with an extended burst data length, when the optimum phase data selection method or optimum phase clock selection method is applied as it is to the bit synchronization circuit, the optimum phase data or optimum phase clock determined in the preamble area is generated in the payload area. There is a possibility of deviating from the optimum phase due to phase fluctuation or frequency asynchronization. In this case, there is a problem that the retiming data based on the optimum phase data or the optimum phase clock determined in the preamble area becomes indefinite and a bit error occurs in the output data.

  In order to improve such a problem, a technique relating to a bit synchronization circuit having a phase tracking function over the entire region of the received burst signal has been considered (for example, see Patent Document 7).

  According to the bit synchronization circuit described in Patent Document 7, the received burst data is sampled and converted into a multiphase data sequence having different phases, and the phase margin having the most phase margin with respect to the reference clock is obtained from the sampled multiphase sampling data sequence. A certain optimum phase data string is detected, a control signal indicating the detected optimum phase data string is generated, and an optimum phase data string indicated by the generated control signal is selectively output. The control signal indicating the optimum phase data string is output in accordance with the repetition of the detection operation of the optimum phase data string during the reception period of the same burst signal, and the optimum phase data string to be selectively output is dynamically switched.

Japanese Patent Laid-Open No. 9-162853 JP-A-9-36849 Japanese Patent Laid-Open No. 7-193562 Japanese Patent Laid-Open No. 9-181713 JP-A-10-247903 Japanese Patent Laid-Open No. 11-308204 JP 2005-12305 A

  By the way, in order to realize a high transmission rate, it is indispensable to increase the bit synchronization, and it is desired to increase the speed and reliability of the generation of the control signal indicating the optimum phase data string. Since the optical signal received by the master station device in the PON system differs in the reception level of the optical signal depending on the transmission source, it is identified and reproduced for each received burst data by the ATC (Automatic Threshold Control) function of the photoelectric conversion unit. However, in order to set an optimal ATC threshold for burst data with a low light reception level, it is necessary to make the offset threshold value set in the guard time period as small as possible. However, the smaller the offset threshold, Since the photoelectric conversion unit is sensitive to noise, an erroneous signal may be input to the bit synchronization circuit, causing the bit synchronization circuit to malfunction.

  The conventional bit synchronization circuit using the optimum phase data selection method described in Patent Documents 1, 2, and 7 and the conventional bit synchronization circuit using the optimum phase clock selection method described in Patent Documents 3 to 6 are as follows. The rising or falling change point of the multiphase received data is detected, and the one closest to the phase of the input signal is selected. However, the conventional bit synchronization circuit using the optimum phase data selection method described in Patent Documents 1, 2, and 7 and the conventional bit synchronization circuit using the optimum phase clock selection method described in Patent Documents 3 to 6 above. However, when an incorrect clock is selected at the end of the preamble due to noise or the like, there is a problem that an identification error occurs in the data portion of the received burst signal. In addition, when the optimum phase selection is performed only by the preamble, there is a problem that an identification error may occur in the entire target burst.

  In order to solve such a problem, a protection circuit that repeats the coincidence between the burst signal and the fixed pattern and the change point detection of the rising edge or falling edge of the clock multiple times is used. A method of selecting the optimum phase by means of average value processing is also considered. However, if the number of stages of the protection circuit is increased in order to improve the stability, a long preamble is required, resulting in a new problem that high-speed synchronization cannot be performed.

  The present invention has been made in view of the above, and an object of the present invention is to obtain a bit synchronization circuit that determines the synchronization state of received data and reproduces the received data without depending on the pattern of the received data by the burst signal. And

  In order to solve the above-described problems and achieve the object, the present invention provides a continuous clock generation circuit that generates a reference clock used in a circuit in a bit synchronization circuit that samples and reproduces reception data by a burst signal, A Gate signal generator for extracting a Gate signal synchronized with received data, and a bit width of the received data divided into N (1 <N, N is a natural number) in phase with the Gate signal extracted by the Gate signal generator A phase oscillator with a gate that generates an N-phase clock, and synchronization of the received data based on a result of latching an N-phase clock generated by the phase oscillator with a gate with a reference clock generated by the continuous clock generation circuit. A synchronization state determination unit for determining a state, and based on a determination result of the synchronization state determination unit Reproducing the serial reception data, characterized by.

  According to the present invention, the continuous clock generation circuit generates a reference clock used in the circuit, the Gate signal generation unit extracts the Gate signal synchronized with the received data by the burst signal, and the phase oscillator with Gate is phase-synchronized with the Gate signal. Then, an N-phase clock is generated by dividing the bit width of the received data by N (1 <N, N is a natural number), and the synchronization state determination unit latches the N-phase clock with the reference clock to determine the received data Since the sync status is determined and the received data is reproduced based on the determination result of the sync status determination unit, the sync status of the received data is determined and received without depending on the pattern of the received data by the burst signal. There is an effect that a bit synchronization circuit for reproducing data can be obtained.

  Embodiments of a bit synchronization circuit according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a diagram showing a configuration of a PON (Passive Optical Networks) system which is one of point-to-multipoint communication systems to which a bit synchronization circuit according to the present invention is applied. In FIG. 1, a PON system includes a master station device (OLT: Optical Line Terminal) 1 and one to a plurality of (in this case, three) subscriber devices (ONU: Optical Network Unit) 2-1 to 2-3. And an optical fiber 3 and an optical coupler 4 as an optical transmission medium for connecting the master station device 1 and the subscriber devices 2-1 to 2-3.

  When the subscriber apparatuses 2-1 to 2-3 transmit data to the master station apparatus 1 (uplink transmission direction), the subscriber apparatuses 2-1 to 2-3 transmit data in the uplink transmission direction. The data is transmitted in bursts with the timing adjusted so that it does not collide with data in the uplink transmission direction transmitted by the own device. The data frame in which the subscriber units 2-1 to 2-3 transmit data includes a preamble for the master station device 1 to establish synchronization with the data signal, a delimiter pattern for identifying the payload area, and data It consists of a payload area to be set.

  The master station device 1 includes a bit synchronization circuit, receives data frames in the uplink transmission direction transmitted from the subscriber devices 2-1 to 2-3, and the leading preamble of the received data frame (hereinafter referred to as received data). Thus, bit synchronization of the received data is established, the payload area is identified by the delimiter pattern following the preamble, and the received data processing is performed on the data in the payload area.

  FIG. 2 is a block diagram showing a configuration of the first embodiment of the bit synchronization circuit according to the present invention. In FIG. 2, the bit synchronization circuit includes a continuous clock generation circuit 10, a PLL (Phase Locked Loop) 11, a multiphase clock generation unit 12, a 1 / N frequency divider 13, a reset signal generation unit 14, and a multiphase data sampling unit 15. , A continuous clock synchronization circuit 16 and an optimum phase selection unit 17.

  The continuous clock generation circuit 10 generates an in-device reference clock CLK that is a continuous clock used in the master station device 1. The PLL 11 generates a multiplier internal reference clock obtained by multiplying the internal reference clock CLK generated by the continuous clock generation circuit 10 by a predetermined value. The multiphase clock generation unit 12 generates n multiphase clocks in which the phase of the reference clock in the multiplier generated by the PLL 11 is different by 1 / N (1 <N, N is a natural number). The 1 / N frequency divider 13 generates a divided clock obtained by dividing the n number of multiphase clocks generated by the multiphase clock generator 12 by 1 / N.

  The reset signal generation unit 14 includes a preamble of received data received from the subscriber devices 2-1 to 2-3, an in-device reference clock CLK generated by the continuous clock generation circuit 10, and an in-multiplier device generated by the PLL 11. Based on the reference clock, the synchronization state of the received data is determined. The reset signal generation unit 14 asserts the reset signal RES when it is determined that the received data is in a synchronized state, and when it is determined that the received data is not in a synchronized state or when a synchronization release signal is received from the outside. The reset signal RES is negated. Here, the received data is in a synchronized state is a state in which the fluctuation of the received data is stable.

  FIG. 3 is a block diagram showing a configuration of the reset signal generation unit 14 shown in FIG. In FIG. 3, the reset signal generation unit 14 includes a 1 / N2 frequency divider 144, a Gate signal generation unit 141, a phase oscillator 142 with Gate, a 1 / N1 frequency divider 145, and a synchronization state determination unit 146.

  The 1 / N2 divider 144 divides the in-device reference clock CLK generated by the continuous clock generation circuit 10 into 1 / N1 (N1 is a natural number) to generate a divided clock CK1. The Gate signal generation unit 141 extracts a signal synchronized with the received data as a Gate signal. The phase oscillator 142 with Gate is configured to divide the bit width of the received data into N in synchronization with the Gate signal based on the Gate signal generated by the Gate signal generator 141 and the reference clock in the multiplier generated by the PLL 11. The N-phase clock is generated.

  The 1 / N1 frequency divider 145 divides the N-phase clock generated by the gated phase oscillator 142 into 1 / N1 to generate frequency-divided clocks G-VCOCK1 to G-VCOCKn.

  The synchronization state determination unit 146 latches and synchronizes the divided clocks G-VCOCK1 to G-VCOCKn generated by the 1 / N1 divider 145 with the divided clock CK1 generated by the 1 / N2 divider 144. It is determined whether or not it is in a state. The synchronization state determination unit 146 asserts the reset signal RES when it is determined that it is in a synchronization state, and negates the reset signal RES when it is determined that it is not in a synchronization state or when a synchronization release signal is received from the outside. To do.

  Returning to FIG. 2, the multiphase data sampling unit 15 samples the received data using the n N phase clocks generated by the multiphase clock generation unit 12. The continuous clock synchronization circuit 16 outputs the sampling data sampled by the multiphase data sampling unit 15 as phase synchronization data synchronized with the in-device reference clock CLK.

  Based on the reset signal RES generated by the reset signal generation unit 14, the optimum phase selection unit 17 has phase synchronization having the most phase margin with respect to received data among the phase synchronization data input from the continuous clock synchronization circuit 16. Data is selected as the optimum phase synchronization data string, and the selected optimum phase synchronization data string is output as output data.

  Next, the operation of the bit synchronization circuit of the first embodiment will be described. The continuous clock generation circuit 10 generates the in-device reference clock CLK, and outputs the generated in-device reference clock CLK to the PLL 11, the continuous clock synchronization circuit 16, and the optimum phase selection unit 17.

  The PLL 11 generates a multiplier internal reference clock obtained by multiplying the internal reference clock CLK by a predetermined value. The PLL 11 outputs the generated multiplier internal reference clock to the reset signal generation unit 14 and the multiphase clock generation unit 12.

  The gate signal generation unit 141 of the reset signal generation unit 14 extracts a signal synchronized with the received data as a gate signal. Specifically, the preamble is a signal having a predetermined “L” or “H” pattern, and the reset signal generation unit 14 detects a change point (edge) of the preamble. The gate signal generation unit 141 inverts the polarity of the gate signal for each edge detection and outputs the inverted signal to the gated phase oscillator 142.

  The phase oscillator 142 with Gate generates n N-phase clocks obtained by dividing the bit width of the received data into N in synchronization with the Gate signal based on the Gate signal and the reference clock in the multiplier. The phase oscillator 142 with Gate outputs the generated N-phase clock to the 1 / N1 frequency divider 145.

  The 1 / N1 frequency divider 145 divides the N-phase clock into 1 / N1 to generate frequency-divided clocks G-VCOCK1 to G-VCOCKn. The 1 / N1 divider 145 outputs the generated divided clocks G-VCOCK1 to G-VCOCKn to the synchronization state determination unit 146. On the other hand, the 1 / N2 divider 144 divides the in-device reference clock CLK by 1 / N2 to generate a divided clock CK1. The 1 / N2 frequency divider 144 outputs the generated frequency-divided clock CK1 to the synchronization state determination unit 146.

  The synchronization state determination unit 146 latches and synchronizes the divided clocks G-VCOCK1 to G-VCOCKn generated by the 1 / N1 divider 145 with the divided clock CK1 generated by the 1 / N2 divider 144. It is determined whether or not it is in a state. The synchronization state determination unit 146 asserts the reset signal RES when it is determined that it is in a synchronization state, and negates the reset signal RES when it is determined that it is not in a synchronization state or when a synchronization release signal is received from the outside. To do.

  With reference to the timing chart of FIG. 4, the detailed operation of the synchronization state determination of the synchronization state determination unit 146 will be described. FIG. 4 is a timing chart for explaining the operation of determining the synchronization state when the phase-added phase oscillator 142 generates two (n = 2) clocks whose phases are shifted by π. The synchronization state determination unit 146 generates two clocks whose phases are shifted by π by the gated phase oscillator 142 at the rising edge of the divided clock CK1 obtained by dividing the in-device reference clock CLK by 1 / N2 by the 1 / N2 divider 144. The frequency-divided clocks G-VCOCK1 and G-VCOCK2 divided by the 1 / N1 frequency divider 145 are latched.

  At time t0, the result of latching the divided clock G-VCOCK1 with the divided clock CK1 is “L”, and the result of latching the divided clock G-VCOCK2 with the divided clock CK1 is “H”.

  At the time t1, the rising edge of the divided clock CK1 and the edge of the divided clock G-VCOCK1 (in this case, the change point from “H” to “L”) overlap, so that the divided clock G-VCOCK1 is The result of latching with the divided clock CK1 is “?” (Undefined). On the other hand, since the divided clock G-VCOCK2 is stable at "H", the result of latching the divided clock G-VCOCK2 at the rising edge of the divided clock CK1 is "H".

  From time t2 to time t9, the result of latching the divided clock G-VCOCK1 at the rising edge of the divided clock CK1 is "L", and the result of latching the divided clock G-VCOCK2 at the rising edge of the divided clock CK1 is “H”.

  As described above, the divided clock G-VCOCK1 and the divided clock G-BCOCK2 are out of phase with each other by π. Therefore, in the synchronized state, if one of the latch results is “H”, the other is “L”. It becomes the opposite value. Therefore, the synchronization state determination unit 146 is in a stable state (synchronization state) in which the fluctuation of the received data is stable when it is detected that a combination in which the result of latching is contradictory continues for a predetermined period. And the reset signal RES is asserted. In FIG. 4, the synchronization state determination unit 146 latches the divided clock G-VCOCK1 with the divided clock CK1 during the period from the time t2 to the time t5, and becomes “L”, and the divided clock G-VCOCK2 is divided. It is detected that the result latched by the clock CK1 is “H”, and the reset signal is asserted (“H” in this case) at time t5.

  Note that the synchronization state determination unit 146 detects that the combination of the latched results that are in conflict with each other for a certain period of time is continuously counted by counting the number of times that the latch results have opposite values. Is detected when it exceeds a predetermined criterion value.

  By the way, when two (n = 2) clocks whose phases are shifted by π are generated, the changing points of the divided clocks G-VCOCK1 and G-VCOCK2 obtained by frequency-dividing the clock generated by the phase oscillator 142 with gate are in the apparatus. It may coincide with the rising or falling edge of the divided clock CK1 obtained by dividing the reference clock CLK. In this case, the frequency-divided clocks G-VCOCK1 and G-VCOCK2 cannot be correctly latched by the frequency-divided clock CK1, which causes a problem that the synchronization state cannot be correctly determined. Also, when flip-flops are used to correctly latch the divided clocks G-VCOCK1 and G-VCOCK2, the divided clocks G-VCOCK1 and G-VCOCK2 are correctly latched depending on the setup time and hold time of the flip-flops. There are things you can't do.

  Specifically, for example, as shown in FIG. 5, when the divided clocks G-VCOCK1 and G-VCOCK2 are latched at the rising edge of the divided clock CK1, the divided clock G-VCOCK1 is obtained at times t1 and t2. Therefore, “H” and “L” can be latched while satisfying the setup time and hold time of the flip-flop. However, at times t0, t3 to t10, the rising edge of the divided clock CK1 and the changing point of the divided clock G-VCOCK1 are not coincident, and the setup time or hold time of the flip-flop cannot be satisfied. The latch result of the peripheral clock G-VCOCK1 is indefinite (“?”). For the divided clock G-VCOCK2, the rising edge of the divided clock CK1 coincides with the changing point of the divided clock G-VCOCK2 at time t0 to time t10, and the setup time or hold time of the flip-flop is satisfied. It cannot be done and becomes indefinite (“?”). With such a latch result, it cannot be correctly determined that the fluctuation is stable.

  In order to improve such a problem, the number of clocks generated by the phase-added phase oscillator 142 may be increased. For example, it is assumed that the gated phase oscillator 142 generates four (n = 4) clocks whose phases are shifted by π / 2. In this case, as illustrated in FIG. 6, the synchronization state determination unit 146 includes the divided clocks G-VCOCK1 to G-VCOCK4 obtained by dividing the clocks generated by the phase-added phase oscillator 142 by π / 2. And the divided clocks G-VCOCK1 to G-VCOCK4 are latched by the divided clock CK1.

  In FIG. 6, the divided clocks G-VCOCK1 to G-VCOCK4 are latched at the rising edge of the divided clock CK1, and at the time t0, the rising edge of the divided clock CK1 and the divided clocks G-VCOCK2 and G- Since the edge of −VCOCK4 overlaps, the result of latching the divided clocks G-VCOCK2 and G-VCOCK4 with the divided clock CK1 is “?” (Undefined). On the other hand, since the divided clock G-VCOCK1 is stable at “L” and the divided clock G-VCOCK3 is stable at “H”, the divided clock G-VCOCK1 is latched at the rising edge of the divided clock CK1. The result is “L”, and the result of latching the divided clock G-VCOCK3 at the rising edge of the divided clock CK1 is “H”.

  At time t1, since the rising edge of the divided clock CK1 and the edges of the divided clocks G-VCOCK1 and G-VCOCK4 overlap, the divided clocks G-VCOCK1 and G-VCOCK4 are latched at the rising edge of the divided clock CK1. The result is “?” (Undefined). On the other hand, since the divided clocks G-VCOCK2 and G-VCOCK3 are both stable at "H", the results of latching the divided clocks G-VCOCK2 and G-VCOCK3 at the rising edge of the divided clock CK1 are both "H". It becomes.

  At time t2, since the rising edge of the divided clock CK1 and the edges of the divided clocks G-VCOCK3 and G-VCOCK4 overlap, the divided clocks G-VCOCK3 and G-VCOCK4 are latched at the rising edge of the divided clock CK1. The result is “?” (Undefined). On the other hand, since the divided clocks G-VCOCK1 and G-VCOCK2 are both stable at "L", the results of latching the divided clocks G-VCOCK1 and G-VCOCK2 at the rising edge of the divided clock CK1 are both "L". It becomes.

  From time t3 to time t10, the rising edge of the divided clock CK1 and the edge of the divided clocks G-VCOCK2 and G-VCOCK4 overlap, so that the divided clocks G-VCOCK2 and G-VCOCK4 rise. The result of latching at is “?” (Undefined). On the other hand, since the divided clock G-VCOCK1 is stable at “L” and the divided clock G-VCOCK3 is stable at “H”, the divided clock G-VCOCK1 is latched at the rising edge of the divided clock CK1. The result is “L”, and the result of latching the divided clock G-VCOCK3 at the rising edge of the divided clock CK1 is “H”.

  As described above, the divided clocks G-VCOCK1 to G-VCOCK4 are shifted in phase by π / 2. Therefore, in a stable state, the divided clocks G-VCOCK1 to G-VCOCK4 are shifted from the rising edge of the divided clock CK1. Among the latched results, at least one combination (in this case, a combination of the divided clock G-VCOCKC1 and the divided clock G-VCOCK3) among two conflicting combinations of the divided clocks G-VCOCK1 to G-VCOCK4. When the latch result of (1) is “H”, the other is an opposite value such as “L”. Therefore, when the synchronization state determination unit 146 detects that the conflicting combinations continue in any of the combinations obtained as a result of latching for a predetermined period, the synchronization state determination unit 146 is in a stable state in which the fluctuation of the received data is stable. It is determined that there is a reset signal RES and asserted. In FIG. 6, the synchronization state determination unit 146 latches the divided clock G-VCOCK1 with the divided clock CK1 during the period from time t3 to time t7 to “L”, and divides the divided clock G-VCOCK3. It is detected that the result latched by the clock CK1 is “H”, and the reset signal is asserted (“H” in this case) at time t7.

  In this way, by increasing the number of the divided clock G-VCOCKn latched at the rising edge of the divided clock CK1, even when the change point of the divided clock G-VCOCKn and the rising edge of the divided clock CK1 overlap, The state can be reliably determined.

  On the other hand, the multiphase data sampling unit 15 samples received data using the n N phase clocks generated by the multiphase clock generation unit 12. The polyphase data sampling unit 15 outputs the sampled received data to the continuous clock synchronization circuit 16 as sampling data.

  The continuous clock synchronization circuit 16 outputs the sampling data as phase synchronization data synchronized with the in-device reference clock CLK. Specifically, the continuous clock synchronization circuit 16 holds sampling data in a buffer (not shown) by the frequency-divided clock generated by the 1 / N frequency divider 13, and the device generated by the continuous clock generation circuit 10 The sampling data held in the buffer is output by the internal reference clock CLK.

  Based on the reset signal RES generated by the reset signal generation unit 14, the optimum phase selection unit 17 has sampling data having the most phase margin with respect to the reception data among the phase synchronization data input from the continuous clock synchronization circuit 16. Is selected as the optimum phase synchronization data string, and the selected optimum phase synchronization data string is output as output data.

  Specifically, the optimum phase selection unit 17 detects that the reset signal RES generated by the reset signal generation unit 14 is asserted and recognizes that the fluctuation of the received data is stable. When the optimum phase selection unit 17 recognizes that the fluctuation of the received data is stable, the sampling data having the phase margin with respect to the received data among the phase synchronized data input from the continuous clock synchronization circuit 16 is optimum phase synchronized. Select as data column.

  As described above, in the first embodiment, the continuous clock generation circuit 10 generates the in-device reference clock CLK used in the circuit, and the Gate signal generation unit 141 generates the Gate signal synchronized with the received data by the burst signal. A phase-divided clock G-VCOCK1-G is obtained by dividing the N-phase clock obtained by extracting and dividing the bit width of the received data by N (1 <N, N is a natural number) in phase with the Gate signal. -VCOCKn is generated, and the synchronization state determination unit 146 determines the synchronization state of the received data based on the result of latching the divided clocks G-VCOCK1 to G-VCOCKn with the divided clock CK1 obtained by dividing the in-device reference clock CLK. Therefore, the synchronization status of the received data without depending on the pattern of the received data by the burst signal The determination results can be stably obtained. That is, the determination result of the synchronization state of the received data can be stably obtained without providing a protection circuit as in the prior art.

  In the first embodiment, the multiphase clock generation unit 12 generates multiphase clocks in which the phase of the in-device reference clock CLK is different by 1 / N, and the multiphase data sampling unit 15 uses the multiphase clock. The received data is sampled, and the continuous clock synchronization circuit 16 uses the sampling data sampled by the multiphase data sampling unit 15 as phase synchronization data synchronized with the in-device reference clock CLK, and the optimum phase selection unit 17 determines the synchronization state determination unit 146. After indicating that the result is in a synchronized state, the phase synchronization data having the most phase margin with respect to the received data is selected from the phase synchronization data and output as reproduction data. Regardless of the data pattern, the optimum phase data string is dynamically increased from the multiphase sampled received data. And stably can be selected, faster bit synchronization circuit, it is possible to reliability.

  Furthermore, in the first embodiment, the synchronization state determination unit 146 generates two or more phase clocks generated by the phase oscillator 142 with Gate at the rising or falling edge of the divided clock CK1 obtained by dividing the in-device reference clock CLK. When frequency-divided clocks G-VCOCK1 to G-VCOCKn are latched, the number of consecutive times in which the results of the latch results in opposite values are counted, and the count value exceeds a predetermined criterion value Therefore, the determination result of the synchronization state of the reception data can be obtained stably without depending on the pattern of the reception data by the burst signal.

  In the first embodiment, the case where the divided clock G-VCOCKn is latched at the rising edge of the divided clock CK1 has been described as an example. However, the divided clock G-VCOCKn at the falling edge of the divided clock CK1. May be latched.

Embodiment 2. FIG.
A second embodiment of the present invention will be described with reference to FIGS. The bit synchronization circuit of the second embodiment is the same as the bit synchronization circuit of the first embodiment shown in FIG. 2, but the synchronization state determination operation of the synchronization state determination unit 146 of the reset signal generation unit 14 is the same. Different. Since the operations other than the synchronization state determination operation of the synchronization state determination unit 146 are the same as those of the bit synchronization circuit of the first embodiment, description thereof is omitted here, and the synchronization state of the synchronization state determination unit 146 is omitted. Only the determination operation will be described.

  The synchronization state determination unit 146 of the reset signal generation unit 14 according to the first embodiment described above has an edge (rising or rising) on one side of the divided clock CK1 obtained by dividing the in-device reference clock CLK by the 1 / N2 divider 144. The n-phase clocks G-VCOCK1 to G-VCOCKn obtained by dividing the n clocks generated by the phase oscillator 142 with the gate by the 1 / N1 frequency divider 145 are latched. The synchronization state determination unit 146 of the reset signal generation unit 14 according to the second embodiment uses the divided clocks G-VCOCK1 to G-VCOCKn obtained by frequency division using the edges (rising and falling) on both sides of the divided clock CK1. It is to latch.

  Regarding the operation of determining the synchronization state of the synchronization state determination unit 146 of the reset signal generation unit 14 of the bit synchronization circuit of the second embodiment, the phase oscillator 142 with Gate has four (n = 4) phases shifted by π / 2. A case where a clock is generated will be described as an example.

  With reference to FIG. 7, the operation for determining the synchronization state when the divided clocks G-VCOCK1 to G-VCOCK4 are latched at the rise and fall of the divided clock CK1 will be described. At time t0, the rising edge of the divided clock CK1 and the edge of the divided clocks G-VCOCK2 and G-VCOCK4 overlap, so the divided clocks G-VCOCK2 and G-VCOCK4 are latched at the rising edge of the divided clock CK1. The result is “?” (Undefined). On the other hand, since the divided clocks G-VCOCK1 and G-VCOCK3 are stable at “L” and “H”, the result of latching the divided clocks G-VCOCK1 and G-VCOCK3 at the rising edge of the divided clock CK1 is “ L ”and“ H ”.

  At time t1, the divided clocks G-VCOCK1 and G-VCOCK4 are stable at “H” and the divided clocks G-VCOCK2 and G-VCOCK3 are stable at “L” at the fall of the divided clock CK1. Therefore, the result of latching the divided clocks G-VCOCK1 and G-VCOCK4 at the falling edge of the divided clock CK1 is “H”, and the divided clocks G-VCOCK2 and G-VCOCK3 are raised. The result of latching downstream is “L”.

  At time t2, since the rising edge of the divided clock CK1 and the edges of the divided clocks G-VCOCK1 and G-VCOCK4 overlap, the divided clocks G-VCOCK1 and G-VCOCK4 are latched at the rising edge of the divided clock CK1. The result is “?” (Undefined). On the other hand, since the divided clocks G-VCOCK2 and G-VCOCK3 are both stable at “H”, the result of latching the divided clocks G-VCOCK2 and G-VCOCK3 at the rising edge of the divided clock CK1 is “H”. It becomes.

  At time t3, the falling edge of the divided clock CK1 and the edges of the divided clocks G-VCOCK1 to G-VCOCK3 overlap, so that the divided clocks G-VCOCK1 to G-VCOCK3 fall at the falling edge of the divided clock CK1. All latched results are “?” (Undefined). On the other hand, since the divided clock G-VCOCK4 is stable at "H", the result of latching the divided clock G-VCOCK4 at the falling edge of the divided clock CK1 is "H".

  At time t4, the rising edge of the divided clock CK1 and the edges of the divided clocks G-VCOCK3 and G-VCOCK4 overlap, so the divided clocks G-VCOCK3 and G-VCOCK4 are latched at the rising edge of the divided clock CK1. The result is “?” (Undefined). On the other hand, since the divided clocks G-VCOCK1 and G-VCOCK2 are both stable at "L", the results of latching the divided clocks G-VCOCK1 and G-VCOCK2 at the rising edge of the divided clock CK1 are both "L". It becomes.

  At time t5, since the falling edge of the divided clock CK1 and the edge of the divided clock G-VCOCK2 overlap, the result of latching the divided clock G-VCOCK2 at the falling edge of the divided clock CK1 is "?" Indefinite). On the other hand, the divided clock G-VCOCK1 is stable at "H", and the divided clocks G-VCOCK3 and G-VCOCK4 are stable at "L". Therefore, the result of latching the divided clock G-VCOCK1 at the falling edge of the divided clock CK1 is "H", and the results of latching the divided clocks G-VCOCK3 and G-VCOCK4 at the falling edge of the divided clock Ck1 are both “L”.

  At times t6, t8, t10, t12, t14, t16, t18, and t20, the rising edge of the divided clock CK1 and the edges of the divided clocks G-VCOCK2 and G-VCOCK4 overlap, so that the divided clock G-VCOCK2, The result of latching G-VCOCK4 at the rising edge of the divided clock CK1 is “?” (Undefined). On the other hand, the divided clock G-VCOCK1 is stable at “L”, and the divided clock G-VCOCK3 is stable at “H”. Therefore, the result of latching the divided clock G-VCOCK1 at the rising edge of the divided clock CK1 is “L”, and the result of latching the divided clock G-VCOCK3 at the rising edge of the divided clock CK1 is “H”.

  At times t7, t9, t11, t13, t15, t17, t18, and t19, the falling edge of the divided clock CK1 overlaps with the edges of the divided clocks G-VCOCK2 and G-VCOCK4. The results of latching G-VCOCK2 and G-VCOCK4 at the falling edge of the divided clock CK1 are both “?” (Undefined). On the other hand, the divided clock G-VCOCK1 is stable at “H”, and the divided clock G-VCOCK3 is stable at “L”. Therefore, the result of latching the divided clock G-VCOCK1 at the falling edge of the divided clock CK1 is "H", and the result of latching the divided clock G-VCOCK3 at the falling edge of the divided clock CK1 is "L". .

  As described above, when the divided clocks G-VCOCK1 to G-VCOCKn are latched at the rising and falling edges of the divided clock CK1, in a stable state, the divided clocks G-VCOCK1 to G-VCOCK4 are raised. Among the results obtained by latching in step (1), at least one combination of the divided clocks G-VCOCK1 to G-VCOCK4 (in this case, out of the two combinations of the divided clocks G-VCOCK1 to G-VCOCK4) whose phase is shifted by π. If one of the latch results of the divided clock G-VCOCKC1 and the divided clock G-VCOCK3) is "H", the other has an opposite value such as "L", and the divided clock G- As a result of latching VCOKC1 and G-VCOCK3 at the falling edge of the divided clock CK1, one of them is “ "If, on the other hand becomes" conflicting values and so H ". The synchronization state determination unit 146 indicates that the latch result at the rising edge of the divided clock CK1 is an opposite value between “H” and “L” and the latch result at the falling edge of the divided clock CK1 for a certain period. When a set of latch results having opposite values of “L” and “H” is detected, it is determined that the fluctuation of the received data is in a stable synchronization state, and the reset signal RES is asserted. Specifically, the synchronization state determination unit 146 counts the number of consecutive times in which the polarities of the latch results of the divided clocks G-VCOCK1 to G-VCOCK4 whose phases are shifted by π are opposite to each other. When the value exceeds a predetermined criterion value, it is determined to be in a synchronized state.

  In FIG. 7, the synchronization state determination unit 146 latches the divided clock G-VCOCK3 when the divided clock G-VCOCK1 is latched at the rising edge of the divided clock CK1 during the period from the time t5 to the time t9. It is detected that the result is “H” and the latch result of the divided clock G-VCOCK1 at the falling edge of the divided clock CK1 is “H” and the latch result of the divided clock G-VCOCK3 is “L”. At time t9, the reset signal RES is asserted (in this case, “H”).

  Here, if the setting for a certain period is the number of latches, the divided clocks G-VCOCK1 to G-G at one edge (rising or falling) of the divided clock CK1 as in the synchronization state determination unit 146 of the first embodiment. Compared with the case where −VCOCK4 is latched, the divided clocks G-VCOCK1 to G-VCOCK4 are used at both edges (falling and rising) of the divided clock CK1 as in the synchronization state determination unit 146 in the second embodiment. When latched, it can be detected that the fluctuation of the received data is stable at double speed.

  As described above, in the second embodiment, the synchronization state determination unit 146 has the phase oscillator 142 with Gate at the both side edges (rising and falling) of the divided clock CK1 obtained by dividing the in-device reference clock CLK. The divided clocks G-VCOCK1 to G-VCOCKn obtained by dividing the generated clocks of two or more phases are latched, and the latch results of the divided clocks G-VCOCK1 to G-VCOCKn whose phases are shifted by π out of the latch results Since the number of consecutive times in which the polarities are opposite to each other is counted, and the count value exceeds a predetermined criterion value, it is determined that the synchronization state is established. Without depending on the pattern, it is received at a higher speed than when latching at one edge (rising or falling) of the divided clock CK1. The synchronization state determination result of the data can be stably obtained.

  In the second embodiment, it is detected that the fluctuation of the received data is stabilized at high speed by latching the divided clocks G-VCOCK1 to G-VCOCKn at both edges of the divided clock CK1. Instead of using both edges of the divided clock CK1, the frequency of the divided clock CK1 may be set to twice the frequency of the divided clocks G-VCOCK1 to G-VCOCKn. In this case, the in-device reference clock CLK may be set so as to be twice the frequency of the n clocks generated by the phase oscillator 142 with Gate.

  FIG. 8 shows that the phase oscillator 142 with Gate generates four (n = 4) clocks whose phases are shifted by π / 2, and the number of n clocks generated by the phase oscillator 142 with Gate generates the frequency of the in-device reference clock CLK. FIG. 10 is a timing chart showing a divided clock CK1, divided clocks G-VCOCK1 to G-VCOCK4, and a latch result that are input to the synchronization state determination unit 146 when set to be twice the frequency of the clock.

  The frequency-divided clock CK1 in FIG. 8 has a frequency twice that of the frequency-divided clock CK1 shown in FIG. Therefore, the result of latching the divided clocks G-VCOCK1 to G-VCOCK4 at the rising edge of the divided clock CK1 in FIG. 8 and the divided clocks G-VCOCK1 to G-- at the rising and falling edges of the divided clock CK1 in FIG. The result of latching VCOCK4 is the same. Therefore, even when the latch result by the frequency-divided clock CK1 having the double frequency shown in FIG. 8 is used, the synchronization state determination unit 146 has the determination condition described with reference to the timing chart shown in FIG. It can be determined that the fluctuation of the received data is stable under the same determination condition.

Embodiment 3 FIG.
A third embodiment of the present invention will be described with reference to FIGS. The bit synchronization circuit of the third embodiment includes a reset signal generation unit 14a instead of the reset signal generation unit 14 of the bit synchronization circuit of the first embodiment shown in FIG. Components having the same functions as those of the bit synchronization circuit of the first embodiment shown in FIG. 2 are given the same reference numerals, and redundant descriptions are omitted.

  FIG. 9 is a block diagram showing a configuration of the reset signal generation unit 14a of the bit synchronization circuit according to the third embodiment. The reset signal generation unit 14a illustrated in FIG. 9 is 1 / N2 minutes instead of the 1 / N2 frequency divider 144 and the synchronization state determination unit 146 of the reset signal generation unit 14 of the first embodiment illustrated in FIG. A peripheral 144a and a synchronization state determination unit 146a are provided. Components having the same functions as those of the reset signal generation unit 14 of the first embodiment shown in FIG. 3 are given the same reference numerals, and redundant descriptions are omitted.

  The 1 / N2 frequency divider 144a divides the in-device reference clock CLK generated by the continuous clock generation circuit 10 into 1 / N1 (N1 is a natural number) to generate a divided clock CK1. In addition, a divided clock CK2 having a phase shifted from the divided clock CK1 by a predetermined phase is generated. The 1 / N2 divider 144a inputs the generated divided clocks CK1 and CK2 to the synchronization state determination unit 146a.

  The synchronization state determination unit 146a latches the divided clocks G-VCOCK1 to G-VCOCKn generated by the 1 / N1 divider 145 with the divided clocks CK1 and CK2 generated by the 1 / N2 divider 144a. To determine the synchronization status. The synchronization state determination unit 146a asserts the reset signal RES when it is determined to be stable, and negates the reset signal RES when it is determined that the state is not stable (unstable state).

  Next, the operation of the bit synchronization circuit of the third embodiment will be described. The bit synchronization circuit of the third embodiment is substantially the same as the bit synchronization circuit of the first embodiment, and the difference is the operation of determining the synchronization state of the synchronization state determination unit 146a of the reset signal generation unit 14a. It is. Therefore, here, only the operation of the synchronization state determination unit 146a will be described with reference to the timing chart of FIG.

  In FIG. 10, the divided clock CK1 and the divided clock CK2 are out of phase by π / 2, and the divided clocks G-VCOCK1 to G-VCOCK4 are latched at the rising edge of the divided clocks CK1 and CK2. Yes. Since the rising edge of the divided clock CK1 and the edge of the divided clocks G-VCOCK2 and G-VCOCK4 overlap at time t0, the result of latching the divided clocks G-VCOCK2 and G-VCOCK4 with the divided clock CK1 is “ ? ”(Indefinite). On the other hand, since the divided clock G-VCOCK1 is stable at “L” and the divided clock G-VCOCK3 is stable at “H”, the divided clock G-VCOCK1 is latched at the rising edge of the divided clock CK1. The result is “L”, and the result of latching the divided clock G-VCOCK3 at the rising edge of the divided clock CK1 is “H”.

  At time t1, since the rising edge of the divided clock CK2 and the edge of the divided clock G-VCOCK3 overlap, the result of latching the divided clock G-VCOCK3 at the rising edge of the divided clock CK2 is “?” (Undefined). Become. On the other hand, the divided clocks G-VCOCK1 and G-VCOCK2 are both stable at "L" and the divided clock G-VCOCK4 is stable at "H". Both latched at the rising edge of the divided clock CK2 are "L", and the result of latching the divided clock G-VCOCK4 at the rising edge of the divided clock CK2 is "H".

  At time t2, since the rising edge of the divided clock CK1 and the edges of the divided clocks G-VCOCK1 and G-VCOCK4 overlap, the result of latching the divided clocks G-VCOCK1 and G-VCOCK4 at the rising edge of the divided clock CK1 Are both “?” (Undefined). On the other hand, since the divided clocks G-VCOCK2 and G-VCOCK3 are both stable at "H", the result of latching the divided clocks G-VCOCK2 and G-VCOCK3 at the rising edge of the divided clock CK1 is "H". It becomes.

  At the time t3, the rising edge of the divided clock CK2 and the edges of the divided clocks G-VCOCK1 and G-VCOCK2 overlap, so that the divided clocks G-VCOCK1 and G-VCOCK2 are latched at the rising edge of the divided clock CK2. Are both “?” (Undefined). On the other hand, since the divided clocks G-VCOCK3 and G-VCOCK4 are both stable at "H", the results of latching the divided clocks G-VCOCK3 and G-VCOCK4 at the rising edge of the divided clock CK2 are both "H". It becomes.

  At time t4, since the rising edge of the divided clock CK1 and the edge of the divided clock G-VCOCK4 overlap, the result of latching the divided clock G-VCOCK4 at the rising edge of the divided clock CK1 is “?” (Undefined). Become. On the other hand, the divided clocks G-VCOCK1 and G-VCOCK2 are stable at “L” and the divided clock G-VCOCK3 is stable at “H”. The results of latching at the rising edge of the divided clock CK1 are both “L”, and the result of latching the divided clock G-VCOCK3 at the rising edge of the divided clock CK1 is “H”.

  At time t5, the rising edge of the divided clock CK2 and the edge of the divided clocks G-VCOCK1 and G-VCOCK4 overlap, so that the divided clocks G-VCOCK1 and G-VCOCK4 are latched at the rising edge of the divided clock CK2. Are both “?” (Undefined). On the other hand, since the divided clocks G-VCOCK2 and G-VCOCK3 are stable at “L”, the results of latching the divided clocks G-VCOCK2 and G-VCOCK3 at the rising edge of the divided clock CK2 are both “L”. Become.

  At times t6, t8, t10, t12, t14, t16, t18, and t20, since the rising edge of the divided clock CK1 and the edges of the divided clocks G-VCOCK2 and G-VCOCK4 overlap, the divided clock G-VCOCK2, The result of latching G-VCOCK4 at the rising edge of the divided clock CK1 is “?” (Undefined). On the other hand, since the divided clock G-VCOCK1 is stable at “L” and the divided clock G-VCOCK3 is stable at “H”, the divided clock G-VCOCK1 is latched at the rising edge of the divided clock CK1. The result is “L”, and the result of latching the divided clock G-VCOCK3 at the rising edge of the divided clock CK1 is “H”.

  At times t7, t9, t11, t13, t15, t17, t19, and t21, the rising edge of the divided clock CK2 and the edges of the divided clocks G-VCOCK1 and G-VCOCK3 overlap, so that the divided clock G-VCOCK1, The result of latching G-VCOCK3 at the rising edge of the divided clock CK2 is “?” (Undefined). On the other hand, since the divided clock G-VCOCK2 is stable at “L” and the divided clock G-VCOCK4 is stable at “H”, the divided clock G-VCOCK2 is latched at the rising edge of the divided clock CK2. The result is “L”, and the result of latching the divided clock G-VCOCK4 at the rising edge of the divided clock CK2 is “H”.

  The synchronization state determination unit 146a latches the divided clocks G-VCOCK1 to G-VCOCK4 at the rising edge of the divided clock CK1, and latches the divided clocks G-VCOCK1 to G-VCOCK4 at the rising edge of the divided clock CK2. Among the results, at least one of the two conflicting combinations of the latch result sets in which the phases of the divided clocks G-VCOCK1 to G-VCOCK4 are shifted by π is inconsistent between “H” and “L” for a certain period. When the value is detected, it is determined that the fluctuation of the received data has been determined, and the reset signal RES is asserted. The determination of a certain period is performed by counting the number of consecutive times when the polarity of the set of latch results of the divided clocks G-VCOCK1 to G-VCOCK4 whose phases are shifted by π is opposite, and the count value is determined in advance. Suppose that the criterion value is exceeded.

  In FIG. 10, in the period from time t6 to time t14, the synchronization state determination unit 146a sets the result of latching the divided clock G-VCOCK1 at the rising edge of the divided clock CK1 to "L" and the divided clock G- The result of latching VCOCK3 at the rising edge of the divided clock CK1 is “H”, the latch results of the divided clock G-VCOCK1 and the divided clock G-VCOCK3 are contradictory values, and from time t5 to time t15 In the period, the result of latching the divided clock G-VCOCK2 at the rising edge of the divided clock CK2 becomes “L”, and the result of latching the divided clock G-VCOCK4 at the rising edge of the divided clock CK2 becomes “H”. The latch results of the divided clock G-VCOCK2 and the divided clock G-VCOCK4 conflict with each other. Asserted (in this case, "H") to the reset signal RES is detected that Tsu to.

  In this way, the divided clocks CK1 and CK2 obtained by dividing the in-device reference clock CLK in consideration of the setup time and hold time of the flip-flop that latches the divided clocks G-VCOCK1 to G-VCOCKn and the pulse width distortion. Is shifted by π / 2, the divided clocks G-VCOCK1 to G-VCOCKn are latched at the rise and fall of the divided clock CK1, or the internal reference clock CLK is generated by the phase oscillator 142 with Gate. The synchronous state determination unit according to the second embodiment in which the frequency-divided clocks G-VCOCK1 to G-VCOCKn are latched at the rising edge or falling edge of the divided clock CK1 generated by dividing the clock. Compared to 146, it was confirmed that the fluctuation of the received data was stabilized by π / 2 earlier. Can be issued.

  As described above, in the third embodiment, the synchronization state determination unit 146a uses the divided clocks G-VCOCK1 to G-VCOCKn obtained by dividing the clocks of two or more phases generated by the phase oscillator 142 with Gate. The divided clocks G-VCOCK1 to G-VCOCKn are latched at the rising or falling edge of the divided clock CK2 whose phase is different from that of the divided clock CK1 and the divided clock CK1 obtained by dividing the internal reference clock CLK. Counting the number of consecutive times when the polarity of the set of latch results of the divided clocks G-VCOCK1 to G-VCOCKn whose phases are shifted by π is opposite to each other, and the count value exceeds a predetermined criterion value In this case, it is determined that the state is synchronized, so that it does not depend on the pattern of the received data by the burst signal. , It can be stably obtained the judgment result of the synchronization state of the received data.

  In the third embodiment, the number of clocks having different phases generated by the phase oscillator 142 with Gate is four, and two divided clocks having different phases for latching the divided clocks G-VCOCK1 to G-VCOCK4 are two. However, the number of clocks having different phases is not limited to this.

  In the third embodiment, the 1 / N2 frequency divider 144a generates the frequency-divided clock CK2 having a phase different from that of the frequency-divided clock CK1, but the frequency-divided clock CK2 is synchronized with the synchronization state determination unit 146a. You may make it produce | generate by. In this case, a 1 / N2 frequency divider 144 may be used instead of the 1 / N2 frequency divider 144a.

Embodiment 4 FIG.
A fourth embodiment of the present invention will be described with reference to FIG. 11 and FIG. FIG. 11 is a block diagram showing the configuration of the bit synchronization circuit according to the fourth embodiment of the present invention. In FIG. 11, the bit synchronization circuit includes a continuous clock generation circuit 10, a PLL 11, a Gate signal generation unit 18, a phase oscillator 19 with Gate, a 1 / N frequency divider 20, a reset signal generation unit 14b, a multiphase data sampling unit 15a, A continuous clock synchronization circuit 16A and an optimum phase selection unit 17a are provided.

  The continuous clock generation circuit 10 generates an in-device reference clock CLK that is a continuous clock used in the master station device 1. The PLL 11 generates a multiplier internal reference clock obtained by multiplying the internal reference clock CLK generated by the continuous clock generation circuit 10 by a predetermined value.

  The gate signal generation unit 18 extracts a signal synchronized with the received data as the gate signal, similarly to the gate signal generation unit 141 of the reset signal generation unit 14 of the first embodiment. Similarly to the phase oscillator 142 with gate of the reset signal generator 14 of the first embodiment, the gate-added phase oscillator 19 includes the gate signal generated by the gate signal generator 18 and the multiplication device generated by the PLL 11. Based on the reference clock, an N-phase recovery clock is generated by dividing the bit width of the received data into N in phase synchronization with the Gate signal. The 1 / N frequency divider 20 generates a divided clock obtained by dividing the N-phase reproduction clock generated by the gated phase oscillator 19 by 1 / N.

  The reset signal generation unit 14b stabilizes the fluctuation of the received data based on the N-phase recovered clock generated by the gated phase oscillator 19, the multiplier internal reference clock generated by the PLL 11, and the preamble of the received data. The timing to perform is detected. The reset signal generation unit 14b asserts a reset signal RES that is a control signal when a stable state is detected, and negates the reset signal RES when it is not in a stable state (in an unstable state).

  The multiphase data sampling unit 15a samples received data using n N-phase reproduction clocks generated by the phase oscillator 19 with Gate. The continuous clock synchronization circuit 16a synchronizes the sampling data sampled by the multiphase data sampling unit 15a with the in-device reference clock CLK based on the reset signal RES generated by the reset signal generation unit 14b and the in-device reference clock CLK. Output as the phase-synchronized data. The optimum phase selector 17a has the most phase margin with respect to the received data among the phase synchronization data input from the continuous clock synchronization circuit 16a based on the in-device reference clock CLK generated by the continuous clock generation circuit 10. Sampling data is selected as the optimum phase synchronization data string, and the selected optimum phase synchronization data string is output as output data.

  FIG. 12 is a diagram showing in more detail the configuration of the bit synchronization circuit of the fourth embodiment. The reset signal generation unit 14 of the bit synchronization circuit of the first embodiment shown in FIG. 3 includes a gate signal generation unit 141, a phase oscillator 142 with gate, a 1 / N1 frequency divider 145, and a 1 / N2 frequency divider 144. , And a synchronization state determination unit 146. As shown in FIG. 11, the bit synchronization circuit according to the fourth embodiment includes a gate signal generation unit 18 and a phase oscillator 19 with gate, and functions as a gate signal generation unit 141 and a phase with gate. It is the same as the oscillator 142. Therefore, the reset signal generation unit 14b of the fourth embodiment includes only the 1 / N1 frequency divider 145, the 1 / N2 frequency divider 144, and the synchronization state determination unit 146, and includes the Gate signal generation unit 18 and the phase with Gate. By using the oscillator 19 in place of the gate signal generation unit 141 and the gated phase oscillator 142 of the first embodiment, the same function as the reset signal generation unit 14 of the first embodiment is realized.

  Note that the determination method of the synchronization state determination unit 146 may be any method of the first to third embodiments, and when the method of the third embodiment is used, the reset signal generation unit 14b Instead of the 1 / N2 frequency divider 144 and the synchronization state determination unit 146, a 1 / N2 frequency divider 144a and a synchronization state determination unit 146a may be provided.

  Further, the N-phase clock generated by the phase oscillator 19 with Gate or a clock obtained by dividing the N-phase clock is latched with the in-device reference clock CLK or the in-device reference clock CLK, and the latch As long as it is a method for determining that the fluctuation of the received data is stable based on the result, it may not be the method of any of the first to third embodiments.

  Next, the operation of the bit synchronization circuit according to the fourth embodiment will be described. Since the operation of the reset signal generation unit 14b of the bit synchronization circuit of the fourth embodiment is the same as that of any of the first to third embodiments, the description thereof is omitted here and the received data is sampled. Only the operation will be described.

  The continuous clock generation circuit 10 generates the in-device reference clock CLK, and outputs the generated in-device reference clock CLK to the PLL 11, the continuous clock synchronization circuit 16a, and the optimum phase selection unit 17a. The PLL 11 generates a multiplier internal reference clock obtained by multiplying the internal reference clock CLK by a predetermined value. The PLL 11 outputs the generated multiplier internal reference clock to the reset signal generator 14 b and the phase oscillator 19 with Gate.

  The Gate signal generation unit 18 extracts a signal synchronized with the received data as a Gate signal. The Gate signal generator 18 outputs the extracted Gate signal to the phase oscillator 19 with Gate. The phase oscillator 19 with Gate generates n N-phase reproduction clocks obtained by dividing the bit width of received data into N in synchronization with the Gate signal based on the Gate signal and the multiplier internal reference clock. The gated phase oscillator 19 outputs the generated N-phase recovered clock to the multiphase data sampling unit 15a, the 1 / N frequency divider 20, and the 1 / N1 frequency divider 145.

  The 1 / N1 frequency divider 145 divides the N-phase clock into 1 / N1 to generate frequency-divided clocks G-VCOCK1 to G-VCOCKn. The 1 / N1 divider 145 outputs the generated divided clocks G-VCOCK1 to G-VCOCKn to the synchronization state determination unit 146. On the other hand, the 1 / N2 divider 144 divides the in-device reference clock CLK by 1 / N2 to generate a divided clock CK1. The 1 / N2 frequency divider 144 outputs the generated frequency-divided clock CK1 to the synchronization state determination unit 146.

  The synchronization state determination unit 146 latches and synchronizes the divided clocks G-VCOCK1 to G-VCOCKn generated by the 1 / N1 divider 145 with the divided clock CK1 generated by the 1 / N2 divider 144. The state is determined, and a reset signal RES indicating the determination result is output to the continuous clock synchronization circuit 16a.

  On the other hand, the multi-phase data sampling unit 15a samples received data using n N-phase reproduction clocks generated by the phase oscillator 19 with Gate. The multiphase data sampling unit 15a outputs the sampled received data to the continuous clock synchronization circuit 16a as sampling data.

  The continuous clock synchronization circuit 16a outputs the sampling data as phase synchronization data synchronized with the in-device reference clock CLK. Specifically, the continuous clock synchronization circuit 16a holds sampling data in a buffer (not shown) by the frequency-divided clock generated by the 1 / N frequency divider 20, and is a device generated by the continuous clock generation circuit 10. The sampling data held in the buffer by the internal reference clock CLK is output to the optimum phase selector 17a. That is, the continuous clock synchronization circuit 16a replaces the sampling data from the divided clock obtained by dividing the reproduction clock with the in-device reference clock CLK.

  Further, when the reset signal RES input from the synchronization state determination unit 146 is asserted, the continuous clock synchronization circuit 16a initializes a buffer that holds sampling data. As described above, the sampling data input from the continuous clock synchronization circuit 16a is sampled by the reproduction clock generated by the phase oscillator 19 with Gate. The recovered clock is a clock generated in synchronization with bursty received data transmitted from the subscriber units 2-1 to 2-3. The recovered clock and the in-device reference clock CLK generated by the continuous clock generating circuit 10 are used. The phase relationship differs for each received data. Therefore, the continuous clock synchronization circuit 16a initializes the buffer with the reset signal RES indicating that the fluctuation of the received data is stable, and optimizes the buffering size.

  The optimum phase selection unit 17a selects, as the optimum phase synchronization data string, sampling data having the most phase margin with respect to the received data from the phase synchronization data input from the continuous clock synchronization circuit 16a, and the selected optimum phase synchronization data. Output columns as output data.

  As described above, in the fourth embodiment, the multi-phase data sampling unit 15a samples the received data using the N-phase reproduction clock generated by the gated phase oscillator 19, and the continuous clock synchronization circuit 16a The reception data sampled by the multiphase data sampling unit 15a is held by a reproduction clock, and a buffer for outputting the held data as phase synchronization data synchronized with the in-device reference clock CLK is provided. The optimum phase selection unit 17a has phase synchronization data. When the phase synchronization data having the most phase margin with respect to the received data is selected and output as the reproduction data, the buffer is set by the reset signal RES indicating that the determination result of the synchronization state determination unit 146 is the synchronization state. Since it is initialized, playback starts from the received data. When optimal phase data selection is performed using multiphase data sampled by the clock, a buffer reset signal for transferring the received data from the recovered clock to the in-device reference clock CLK must be generated regardless of the data pattern of the received burst signal. Therefore, it is possible to optimize the buffer replacement buffer size in the bit synchronization circuit.

  As described above, the bit synchronization circuit according to the present invention is useful for reproducing received data using a burst signal in a point-to-multipoint communication system, and in particular, needs to detect the synchronization state of received data stably at high speed. Suitable for some systems.

It is a figure which shows the structure of the PON system which is one of the point-to-multipoint communication systems to which the bit synchronization circuit in this invention is applied. 1 is a block diagram showing a configuration of a first embodiment of a bit synchronization circuit according to the present invention. FIG. FIG. 3 is a block diagram illustrating a configuration of a reset signal generation unit illustrated in FIG. 2. 3 is a timing chart for explaining a detailed operation of the operation state determination of the reset signal generation unit according to the first embodiment. 3 is a timing chart for explaining a detailed operation of the operation state determination of the reset signal generation unit according to the first embodiment. 3 is a timing chart for explaining a detailed operation of the operation state determination of the reset signal generation unit according to the first embodiment. 10 is a timing chart for explaining detailed operation of the operation state determination of the reset signal generation unit of the second embodiment. 10 is a timing chart for explaining detailed operation of the operation state determination of the reset signal generation unit of the second embodiment. FIG. 10 is a block diagram illustrating a configuration of a reset signal generation unit according to a third embodiment. 12 is a timing chart for explaining detailed operations of the operation state determination of the reset signal generation unit according to the third embodiment. It is a block diagram which shows the structure of Embodiment 4 of the bit synchronous circuit in this invention. It is a figure which shows the structure of the bit synchronous circuit of Embodiment 4 in detail.

Explanation of symbols

1 Master station equipment (OLT: Optical Line Terminal)
2-1, 2-2, 2-3 Subscriber equipment (ONU: Optical Network Unit)
3 optical fiber 4 optical coupler 10 continuous clock generation circuit 11 PLL
12 Multiphase clock generation unit 13, 20 1 / N frequency divider 14, 14a, 14b Reset signal generation unit 15, 15a Multiphase data sampling unit 16, 16a Continuous clock synchronization circuit 17, 17a Optimal phase selection unit 18, 141 Gate Signal generation unit 19, 142 Phase oscillator with Gate 144, 144a 1 / N2 frequency divider 145 1 / N1 frequency divider 146, 146a Synchronization state determination unit

Claims (7)

In the bit synchronization circuit that samples and reproduces the received data by the burst signal,
A continuous clock generation circuit for generating a reference clock used in the circuit;
A Gate signal generator for extracting a Gate signal synchronized with the received data;
A phase oscillator with a gate that generates an N-phase clock in which the bit width of the received data is divided into N (1 <N, N is a natural number) in phase with the Gate signal extracted by the Gate signal generation unit;
A synchronization state determination unit that determines a synchronization state of the received data based on a result of latching an N-phase clock generated by the gated phase oscillator with a reference clock generated by the continuous clock generation circuit;
With
Reproducing the received data based on a determination result of the synchronization state determination unit;
A bit synchronization circuit characterized by the above. A multi-phase clock generation unit for generating a multi-phase clock in which the phase of the reference clock generated by the continuous clock generation circuit is different by 1 / N;
A multiphase data sampling unit that samples the received data using a multiphase clock generated by the multiphase clock generation unit;
A continuous clock synchronization circuit that outputs sampling data sampled by the multiphase data sampling unit as phase synchronization data synchronized with a reference clock generated by the continuous clock generation circuit;
After the determination result of the synchronization state determination unit indicates that it is in the synchronization state, the optimum phase synchronization data having the phase margin with respect to the received data is selected from the phase synchronization data and output as reproduction data A phase selector;
The bit synchronization circuit according to claim 1, further comprising: A multiphase data sampling unit that samples the received data using an N-phase clock generated by the phase oscillator with Gate;
The received data sampled by the multiphase data sampling unit is held by an N-phase clock generated by the phase oscillator with Gate, and the held data is synchronized with a reference clock generated by the continuous clock generation circuit. A continuous clock synchronization circuit having a buffer for outputting data;
An optimum phase selection unit that selects phase synchronization data having the most phase margin with respect to the reception data from the phase synchronization data and outputs it as reproduction data;
Further comprising
The continuous clock synchronization circuit includes:
Initializing the buffer when the determination result of the synchronization state determination unit indicates a synchronization state;
The bit synchronization circuit according to claim 1. The synchronization state determination unit
The clocks of two or more phases generated by the phase oscillator with Gate at the rising or falling of the reference clock generated by the continuous clock generating circuit are latched, and the number of consecutive times in which the polarities of the latch results are contradictory are set. Counting and determining that it is in a synchronized state when the count value exceeds a predetermined criterion value;
The bit synchronization circuit according to any one of claims 1 to 3. The synchronization state determination unit
Two or more phase clocks generated by the phase oscillator with the gate are latched at the rise and fall of the reference clock generated by the continuous clock generation circuit, and the phase oscillator with the gate whose phase is shifted by π is generated among the latch results The number of consecutive times in which the polarities of the sets of the latch results of the clocks of two or more phases are opposite to each other is counted, and when the count value exceeds a predetermined determination reference value, it is determined that the state is synchronized thing,
The bit synchronization circuit according to any one of claims 1 to 3. The synchronization state determination unit
The two or more phase clocks generated by the phase oscillator with the gate are latched at the rising or falling edge of the reference clock having a frequency twice that of the two or more phase clocks generated by the gated phase oscillator. Counts the number of consecutive times when the polarity of the set of latch results of two or more clocks generated by the phase oscillator with Gate shifted by π is opposite, and the count value exceeds a predetermined criterion value To determine that it is in a synchronized state,
The bit synchronization circuit according to any one of claims 1 to 3. The synchronization state determination unit
Latching and latching two or more clocks generated by the gated phase oscillator at the rising or falling edge of the reference clock generated by the continuous clock generation circuit and the rising or falling edge of a clock having a phase different from that of the reference clock Among the results, the number of consecutive times when the polarities of the sets of the results of latching the clocks of two or more phases generated by the above-mentioned phase oscillator with gate shifted by π are counted and the count value is determined in advance. Determining that it is in a synchronized state when the criterion value is exceeded,
The bit synchronization circuit according to any one of claims 1 to 3.

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