JP5580439B2 - Method for separating a semiconductor wafer into individual semiconductor dies using implanted impurities - Google Patents

Description

  The present invention generally relates to a method for separating a semiconductor wafer into individual semiconductor dies, and more specifically, a method for separating a semiconductor wafer into individual semiconductor dies using implanted impurities and a semiconductor using the same. It relates to a method of manufacturing.

  During integrated circuit fabrication, multiple integrated circuits (semiconductor dies) are simultaneously formed on a single semiconductor wafer through a series of material deposition and removal processes. Individual semiconductor dies are separated from the wafer by a process called dicing. Wafer dicing generally involves cutting using a circular saw blade or by scribing and breaking the wafer (if the wafer is crystalline). The portion of the semiconductor wafer from which the dies are separated is known as a nick, and in terms of semiconductor manufacturing, it is known as street or scribe street. The scribe street width is governed by wafer properties, blade dimensions and properties, scribe tool dimensions and properties, and the like.

  One skilled in the art will recognize that a conventional scribe street can have a street width of about 62 microns. With a blade or scribe tool width of about 30 microns and a street width of 62 microns, there will be only 16 microns of clearance on one side of the blade or scribe tool. However, the semiconductor manufacturing industry is moving towards narrow scribe streets of, for example, 52 microns or less, in an effort to increase die yield per wafer. To work with a 52 micron street width, the blade or scribe tool must be 20 microns thick or less and the same clearance must be maintained on one side of the blade. However, there is a practical limit to reducing the thickness of the saw blade or scribe tool in order to allow narrow marks.

  Therefore, what is needed in this technique is a method of separating a semiconductor wafer into individual dies that is not constrained by the above thickness.

  To address the above disadvantages of the prior art, a method is provided for separating a semiconductor wafer into individual semiconductor dies. The method of separating a semiconductor wafer includes, among other processes, placing an impurity in a region of the semiconductor wafer adjacent to the junction where the semiconductor dies are joined together, and the impurity breaks bonds in the semiconductor wafer adjacent to the junction. Configured to provide a weakened area. The method of separating the semiconductor wafer further includes the step of separating the semiconductor wafer having impurities into individual semiconductor dies along the weakened region.

  In addition, a method of manufacturing a semiconductor die is provided. The method includes, but is not limited to, obtaining a semiconductor wafer and forming a plurality of semiconductor structures in or on the semiconductor wafer. The method of manufacturing a semiconductor die further includes the step of placing impurities in a region of the semiconductor wafer proximate to a junction where the semiconductor dies are joined together, the impurities splitting bonds in the semiconductor wafer proximate to the junction and causing weakened regions. And then separating the semiconductor structure and the semiconductor wafer having impurities into individual semiconductor dies along the weakened region.

  For a more complete understanding of the invention, reference is made to the following description in connection with the accompanying drawings.

FIG. 1 illustrates a flow diagram illustrating an embodiment of a method of manufacturing a semiconductor die. 2A-B illustrate process steps illustrating an embodiment of a method for separating a semiconductor wafer into individual semiconductor dies. 3A-B illustrate process steps illustrating an embodiment of a method for separating a semiconductor wafer into individual semiconductor dies. 4A-B illustrate process steps illustrating an embodiment of a method for separating a semiconductor wafer into individual semiconductor dies.

  The present disclosure is based on the recognition that at least to some extent, impurities can be implanted into a semiconductor wafer near the junction where the semiconductor dies join together to help separate the semiconductor wafer into its individual semiconductor dies. The disclosure further recognizes that the implanted impurity breaks bonds in the semiconductor wafer proximate the junction resulting in a weakened region and that the semiconductor wafer is separated along its weakened region into its individual semiconductor dies. It is.

  FIG. 1 shows a flow diagram 100 illustrating an embodiment of a method of manufacturing a semiconductor die. The flow diagram includes a subset that includes a method for separating a semiconductor wafer into individual semiconductor dies in addition to a method for manufacturing a semiconductor die. Accordingly, the flow diagram 100 should not be used to limit the present disclosure to any particular process.

  Flow diagram 100 begins at step 105. Thereafter, in step 110, a semiconductor wafer is obtained. Semiconductor wafers consist of a number of different materials. For example, among other things, semiconductor wafers consist of semiconductor, conductor or insulator materials used in microelectronics or similar technical fields. For example, a (III)-(V) group semiconductor such as GaAs, InP or GaN, a (III)-(V) group alloy semiconductor, silicon germanium, silicon carbide, synthetic quartz and fused silica, or a combination of these materials Materials other than those described above can be used.

  The resulting semiconductor wafer may be in any of a number of different manufacturing stages. For example, in one embodiment, the semiconductor wafer is a bare semiconductor that contains only a single layer and does not have a functional structure therein (eg, taken directly from an ingot). In other embodiments, the semiconductor wafer consists of multiple layers, one of which may be embedded oxygen (eg, silicon on insulator (SOI)). In yet another embodiment, the semiconductor wafer consists of a plurality of layers, some of which may be the same as the materials described above. In this embodiment, the semiconductor wafer may already include one or more functional structures (eg, active structures) in or on it.

  Thereafter, in step 120, one or more different semiconductor structures may be formed on, in or over the semiconductor wafer. This step 120 may include many different processing steps. For example, step 120 can include forming one or more active structures (eg, transistor structures, capacitor structures, inductor structures, etc.) on, in, or over a semiconductor wafer. it can. Step 120 may also include patterning one or more photoresist structures on, in, or over the semiconductor wafer. Nevertheless, step 120 is not limited to any single step or combination of processing steps.

  After step 120, in step 130, the resist is patterned to expose a region of the semiconductor wafer adjacent to the junction where the semiconductor dies are joined together. Those skilled in the art will understand the process of patterning a resist (eg, photoresist in one embodiment). For example, the process of patterning a resist begins with applying a layer of resist material to a semiconductor wafer, followed by selective exposure of the resist layer to an energy source, which changes the properties of portions of the resist layer. After such exposure, in order to selectively remove portions of the resist, the resist layer is grown by a “wet growth process” using, for example, a liquid chemical solvent. The result is the desired pattern in the resist, which in this embodiment exposes the area of the semiconductor wafer that is close to the junction where the semiconductor dies join together. In other embodiments, the resist will expose at least a portion of the scribe street in the semiconductor wafer.

  In step 140, impurities are placed in a region of the semiconductor wafer (eg, an exposed region in this example). In one embodiment, the impurities are configured to break bonds in the semiconductor wafer proximate the junction, resulting in a weakened region. There are many impurities used to ultimately form the weakened region. For example, in one embodiment, the impurity is one or more noble gas ions. For example, it has been observed that one or a combination of hydrogen ions and helium ions perform well as impurities. Nevertheless, the impurities may be other ions such as boron or phosphorus, or may be a combination of these ions and the ions described above. However, in some applications, boron and phosphorus should be avoided to prevent counter-doping of the peripheral region. Other impurities can also be used.

While impurities can be placed in a semiconductor wafer using a variety of different processes, in one embodiment, impurities are placed in a semiconductor wafer using an implant technique. For example, in one embodiment, the impurities are implanted into the semiconductor wafer with an implantation energy in the range of about 10 keV to about 1000 keV and an implantation dose in the range of about 1E12 atoms / cm ³ to about 1E16 atoms / cm ³ . In other embodiments, the implantation conditions are selected such that the weakened region extends from the surface of the semiconductor wafer that the implantation first contacts to the opposite surface. Nevertheless, other implantation conditions such as implantation methods that do not require the resist described above can also be used.

  Thereafter, in step 150, the semiconductor wafer having impurities therein is separated into its individual semiconductor dies along the weakened region. The separation of the semiconductor wafer into individual dies can include a number of different processes or combinations of processes. For example, in one embodiment, a semiconductor wafer having a weakened region is subjected to thermal stress to break the weakened region, thereby allowing the semiconductor die to be separated. Thermal stress is applied, among other things, by annealing a semiconductor wafer having impurities contained therein at an appropriate temperature. Those skilled in the art understand the proper temperature (still within the temperature budget to be met) required to fold a semiconductor.

  Similarly, a semiconductor wafer having a weakened region may be exposed to mechanical stress to break the weakened region. Mechanical stress can be applied, inter alia, by mechanical devices that roll over the surface of the semiconductor wafer. In an alternative embodiment, both mechanical and temperature stresses are used to assist in the separation of the semiconductor die. After the step of folding the semiconductor wafer into individual dies, the process stops at step 155.

  The flow diagram 100 of FIG. 1 includes certain steps used to manufacture a semiconductor die according to one embodiment of the disclosure. In alternative embodiments, fewer or additional steps may be used to manufacture a semiconductor die in accordance with the disclosed alternative embodiments. Furthermore, the specific order in which each step is performed can be changed. Thus, for example, in some embodiments, steps 130 and 140 may be performed before step 120.

  2A-4B illustrate process steps illustrating an embodiment of a method for separating a semiconductor wafer from individual semiconductor dies. FIG. 2A first shows a semiconductor wafer 210. The wafer 210 shown in FIG. 2A includes a notch 260 and one or more die regions 270. The notch 260 is centered on the wafer 210 (or other known points) to adjust various different configurations on the wafer 210, such as the position of a particular semiconductor structure, die region 270, etc., as would be expected by one skilled in the art. ) Used along.

  One or more die regions 270 represent die boundaries for different dies on the semiconductor wafer 210. These die boundaries eventually become scribe streets where the wafer 210 is diced into individual semiconductor dies. Furthermore, the die region 270 may or may not be visible to the naked eye, regardless of whether or not the enlargement means is used. The number of die areas 270 on a given wafer 210 will generally vary based on the size of the wafer 210 and the desired size for the individual die area 270.

  Proceeding to FIG. 2B, an enlarged view of a portion of the semiconductor wafer 210 of FIG. 2A is shown. As shown, the semiconductor wafer 210 includes a collection of different materials, layers and structures. For example, the semiconductor wafer 210 includes a base layer 212 (eg, single crystal silicon in one embodiment), an active structure layer 214 (eg, a transistor device in one embodiment), and an interconnect structure layer 216 (eg, in one embodiment). One or more interconnect layers). Base layer 212, active structure layer 214, and interconnect structure layer 216 may comprise, among other things, any one or collection of the above materials. Similarly, additional layers may be present on the semiconductor wafer 210 during this manufacturing stage.

  As shown in FIG. 2B, a patterned resist 220 is formed on the semiconductor wafer 210 to expose the region 230 of the semiconductor wafer 210. A process similar to that described above can be used to pattern the resist 220. The exposed region 230, in one example, is positioned proximate to a junction where the semiconductor dies 270 are joined together. In other embodiments, the exposed region 230 exposes at least a portion of the scribe street in the semiconductor wafer 210.

  In one embodiment, exposed region 230 has a width (w) that is less than about 5 microns. Exposed portion 230 has a width (w) less than about 1 micron in an alternative embodiment. The width (w) described above is much smaller than the width of a saw blade or scribe tool as previously used to dice the semiconductor wafer 210 into individual semiconductor dies. Therefore, a considerable substrate space of the semiconductor wafer 210 is saved.

  FIG. 2B further shows that impurities 240 are introduced into the exposed region 230 through openings in the resist 220. Impurity 240 may be disposed in the semiconductor using a process similar to that described above, among others. As described above, the impurities 240 are configured to break bonds in the semiconductor wafer 210 proximate to the junction where the semiconductor dies 270 are joined together. Impurities 240 can further result in weakened regions 250 in the semiconductor wafer 210. The weakened region 250, in one embodiment, extends substantially perpendicular to the initial surface on which the impurities 240 are disposed. This is a direct difference from other processes that create weakened regions that extend substantially parallel to the surface.

  The example of FIGS. 2A and 2B shows that resist 220 is used to precisely place impurities 240 in semiconductor substrate 210. Nevertheless, there are other embodiments that do not require a resist. For example, there are known examples in which a direct write injection method is used. For example, a photon beam driven by an xy stage can be used to include the impurities 240 in the semiconductor substrate 210.

  FIGS. 3A and 3B show the semiconductor wafer 210 of FIGS. 2A and 2B after removal of at least a portion of the back side of the semiconductor wafer 210 (eg, the surface opposite the surface where the impurities 240 were originally disposed). In one embodiment, a conventional wafer backgrind is used to reduce the thickness of the semiconductor wafer 210 to a value in the range of about 200 microns to about 400 microns. In alternative embodiments, a larger or smaller back grind is used. The process of removing at least a portion of the backside of the semiconductor wafer 210 is designed to assist in separating the semiconductor wafer 210 into its individual semiconductor dies.

  4A and 4B show the semiconductor wafer 210 of FIGS. 3A and 3B after separating the semiconductor wafer 210 with impurities 240 into individual semiconductor dies 410 along the weakened region 250. As described above, the process of separating the semiconductor wafer 210 into individual semiconductor dies can be aided by the application of stress. The example shown in FIGS. 4A and 4B illustrates the use of mechanical stress applied using a roller 420. In this example, rollers 420 are used to apply stress, but those skilled in the art will appreciate that various other techniques and devices can be used. It should be noted again that thermal stress or other types of stress (eg, acoustic stress) can be used.

  The process described above with respect to FIGS. 1-4B shows that impurities are disposed in a semiconductor wafer after forming one or more structures therein, particularly after forming an interconnect structure. In some embodiments, impurities may be included in the semiconductor wafer before any structure is formed thereon or therein. Similarly, in some embodiments, impurities are included in the semiconductor wafer immediately after the active structure is formed on or in it.

  Aspects of the invention provide certain benefits over other conventional processes. For example, according to the above disclosure, the die lanes can be smaller than allowed by other sawing and scribing techniques, so that more silicon can be utilized. Furthermore, the use of an implantation method to separate the semiconductor wafer into individual dies is lower in cost compared to the purchase and maintenance of conventional saws and scribe tools, and ultimately lower in processing costs.

  Further details regarding the inclusion of impurities, as well as other relevant information, are disclosed in U.S. Pat. Nos. 6,335,258, 6020252, 5877070, and 6372609, and U.S. Patent Application Publication Nos. 2004/0171232 and 2004/0166649, all of which are incorporated herein by reference. Are incorporated herein by reference as if they were all included.

  Those skilled in the art to which the above disclosure pertains will understand that other and further additions, deletions, substitutions and modifications may be made to the above embodiments without departing from the scope of the invention.

Claims (10)

A method of separating a semiconductor wafer into individual semiconductor dies,
Placing an impurity configured to split a bond in a semiconductor wafer adjacent to the junction to provide a weakened region in a region of one surface of the semiconductor wafer adjacent to a junction where the semiconductor dies are joined together;
Removing at least a portion of the opposite surface of the semiconductor wafer after the impurity is disposed in the region of the semiconductor wafer, and separating the semiconductor wafer having the impurity and the removed portion along the weakened region With a process,
METHOD mechanical Also, including the step of separating the semiconductor wafer using an acoustic stress without a step saw blade or scribe tool for separating the semiconductor wafer.   2. The method of claim 1, wherein the step of disposing the impurities includes the step of implanting noble gas ions into the region.   The method of claim 1, wherein the region has a width less than about 5 microns.   The method of claim 1, wherein the impurities are disposed in scribe streets in the semiconductor wafer.   The method of claim 1, wherein at least a portion of the portion removed from the opposite surface corresponds in position to a weakened region on the one surface.   2. The method of claim 1, wherein the step of separating the semiconductor wafer includes the step of separating the semiconductor wafer using a roller for generating the mechanical stress.   The method of claim 1, wherein the region has a width less than about 1 micron. The method of claim 1, wherein the region has a width less than 5 microns . A method of separating a semiconductor wafer into individual semiconductor dies,
Constructed to split a bond in a semiconductor wafer proximate to the junction into a region having a width of less than 5 microns on one surface of the semiconductor wafer adjacent to the junction where the semiconductor dies are bonded to each other to provide a weakened region A step of arranging impurities,
Removing at least a portion of the opposite surface of the semiconductor wafer after the impurities are disposed in the region of the semiconductor wafer, and mechanical or acoustical along the weakened region without the use of a saw blade or scribe tool Separating the semiconductor wafer having the impurity and the removed portion using a mechanical stress .   10. The method of claim 9, wherein the region has a width that is less than about 5 microns.

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