CN105206572A - Method separating semiconductor wafer into single semiconductor tube cores through impurity injection - Google Patents
Method separating semiconductor wafer into single semiconductor tube cores through impurity injection Download PDFInfo
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- CN105206572A CN105206572A CN201510500717.7A CN201510500717A CN105206572A CN 105206572 A CN105206572 A CN 105206572A CN 201510500717 A CN201510500717 A CN 201510500717A CN 105206572 A CN105206572 A CN 105206572A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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Abstract
The invention relates to a method separating a semiconductor wafer into single semiconductor tube cores through impurity injection. The method for separating the semiconductor wafer comprises steps that, zones of mutually-connected connection positions of adjacent semiconductor tube cores of the semiconductor wafer are injected with impurity, the impurity is configured to damage bonding of the semiconductor wafer at the adjacent connection positions to generate weakening areas. The method further comprises a step that the semiconductor wafer containing the impurity is separated into single semiconductor tube cores along the weakening areas.
Description
The divisional application that the application is the applying date is on May 17th, 2007, application number is 200780053007.8, denomination of invention is the Chinese invention patent application of " using implanted dopant semiconductor wafer to be separated into the method for single semiconductor element ".
Technical field
A kind of method semiconductor wafer being separated into single semiconductor element of relate generally to of the present invention, more specifically, relate to a kind of method using implanted dopant semiconductor wafer to be divided into single semiconductor element, and a kind of method using implanted dopant to manufacture semiconductor element.
Background technology
In the manufacture process of integrated circuit, by a series of deposition of material and Transformatin, multiple integrated circuit (semiconductor element) is formed on a single semiconductor wafer simultaneously.Then, in the process being called as cutting, single semiconductor element is gone out from wafer-separate.Wafer cutting generally include use circular saw blade cut saw wafer or by rule and broken wafers (if wafer is crystalline solid).The part isolating the semiconductor wafer at tube core place is considered to otch, or is called as in the saying of semiconductor manufacturing: road (street) or road plan.The combination of the size and characteristic etc. of the size of wafer characteristics, saw blade and characteristic, scoring tool determines the width of road plan.
It will be understood by those of skill in the art that traditional road plan can have the road width of about 62 microns.When using the road of the saw blade of about 30 microns wide or scoring tool and 62 microns wide, in the either side just only space of remaining 16 microns of saw blade or scoring tool.But under the effort obtaining every block wafer higher tube core output, semiconductor manufacturing industry is just trending towards narrower road plan, such as, 52 microns or lower.In order to use the road plan of 52 microns, saw blade or scoring tool must not be greater than 20 micron thickness, to keep space identical on saw blade either side.But minimizing saw blade or scoring tool thickness obtain narrower otch and there is the restriction on putting into practice.
Therefore, required for this field is a kind of method by the restriction of thickness above-mentioned, semiconductor wafer not being separated into singulated dies.
Summary of the invention
For solving the shortcoming of above-mentioned prior art, the invention provides a kind of method for semiconductor wafer being separated into single semiconductor element.The method of this separating semiconductor wafer, wherein step can comprise: be placed on by impurity in the region of the semiconductor wafer of the interconnective link position of contiguous semiconductor element, and this impurity is configured to the bonding that destroys in the semiconductor wafer of contiguous link position and becomes atenuator region.Method for separating of semiconductor wafer can also comprise, along atenuator region, the semiconductor wafer with impurity is separated into single semiconductor element.
Present invention also offers a kind of method manufacturing semiconductor element.The method can not comprise acquisition semiconductor wafer with limiting to, and among this semiconductor wafer or on form multiple characteristic of semiconductor.The method of this manufacture semiconductor element can also comprise the region of semiconductor wafer impurity being placed in the interconnective link position of contiguous semiconductor element, impurity is placed on the region of the interconnective nearest link position of semiconductor wafer semiconductor-on-insulator tube core, this impurity is configured to the bonding that destroys in the semiconductor wafer of contiguous link position and produces atenuator region, and then along atenuator region, the semiconductor wafer with characteristic of semiconductor and impurity is separated into single semiconductor element.
Accompanying drawing explanation
In order to understand the present invention more up hill and dale, carry out following explanation, in accompanying drawing below in conjunction with accompanying drawing:
Fig. 1 shows the flow chart represented for the manufacture of the embodiment of the method for semiconductor element; And
Fig. 2 A-4B shows display for semiconductor wafer being separated into the treatment step of the embodiment of the method for single semiconductor element.
Embodiment
The disclosure can be injected into based on impurity in the semiconductor wafer of the interconnective link position of contiguous semiconductor element at least in part to contribute to semiconductor wafer to be separated into the understanding of single semiconductor element.The disclosure also recognizes that the impurity of injection can destroy the bonding of the semiconductor wafer of contiguous link position, produce atenuator region, and semiconductor wafer can be separated into single semiconductor element along this atenuator region.
Fig. 1 shows the flow process Figure 100 represented for the manufacture of the embodiment of the method for semiconductor element.Except the method for the manufacture of semiconductor element, this flow chart comprises the subset of following method, and semiconductor wafer is separated into single semiconductor element by described method.Therefore, flow process Figure 100 should not be used to the disclosure to be restricted to any specific step.
Flow process Figure 100 from step 105 start.After this, in step 110, semiconductor wafer is obtained.This semiconductor wafer can comprise multiple different material.Such as, wherein, this semiconductor wafer can comprise for semiconductor, conductor or the insulating material in microelectronics or similar techniques field.Such as, (III)-(V) the race semiconductor of such as GaAs, InP or GaN, (III)-(V) alloy of race's semiconductor, SiGe, carborundum, synthetic quartz and fused silica, and the combination of these materials or other unlisted materials, can be used.
The semiconductor wafer obtained can be the different phase manufactured.Such as, in one embodiment, semiconductor wafer only has single layer and wherein without any the semiconductor wafer nude film (such as, directly obtaining from ingot) of functional character.In another embodiment, semiconductor wafer contains multiple layer, and one of them layer can be embedding oxide (such as, silicon-on-insulator (SOI)).And in other examples, semiconductor wafer comprises multiple layer, some layer wherein may be similar with above-mentioned material.In this embodiment, semiconductor wafer wherein or it has contained one or more functional character (such as, active feature).
Afterwards, in step 120, other characteristic of semiconductor one or more can be formed on the semiconductor wafer, among or top.Step 120 can comprise multiple different treatment step.Such as, step 120 can comprise on the semiconductor wafer, among or top form one or more active feature (such as, transistors characteristics, capacitor characteristic, inductor feature, etc.).Step 120 can comprise on the semiconductor wafer extraly, among or top formed interconnect feature.Step 120 also can comprise on the semiconductor wafer, among or the one or more photoresist feature of top patterning.But step 120 should not be restricted to the set of any independent treatment step or treatment step.
After step 120, in step 130, resist can be patterned the region close to the interconnective link position of semiconductor element exposing semiconductor wafer.Those skilled in the art are to be understood that the process of patterning resist (photoresist such as, in an embodiment).Such as, the process of patterning resist can start from layer of resist material and be applied in semiconductor wafer, and optionally resist layer is exposed to energy source subsequently, wherein part resist layer characteristically there occurs change owing to being exposed to energy source.After such exposure, resist layer may be developed subsequently, such as, by adopting " the wet development process " of aqueous chemical solvent to develop, thus optionally removes part resist.The result obtained is the pattern of resist expected, in this embodiment, pattern is by the region of the vicinity wherein interconnective link position of semiconductor element that exposes semiconductor wafer.In another embodiment, resist will to expose in semiconductor wafer road plan at least partially.
In step 140, impurity can be placed in the region (such as, exposed region) in this embodiment of semiconductor wafer.In one embodiment, impurity is configured to destroy the bonding of contiguous link position in semiconductor wafer and produces atenuator region.Impurity for finally forming atenuator region can change.Such as, in one embodiment, impurity is one or more noble gas ions.Such as, have been noted that hydrogen ion and helium ion (or independent or mixing) are well as impurity.But impurity can comprise other ions, such as boron or phosphorus, or the combination that can be these ions and ion previously discussed.But, in a particular application, boron and phosphorus should be avoided, thus prevent the contra-doping of peripheral region.Also other impurity can be used.
Multiple different process can be used to be placed in semiconductor wafer by impurity.But, in one embodiment, employ injection technique and impurity is placed in semiconductor wafer.Such as, in one embodiment, the scope that employs in the Implantation Energy of about 10keV to about 1000keV and scope at about 1E12atoms/cm
3to about 1E16atoms/cm
3implantation dosage impurity is injected in semiconductor wafer.In another embodiment, have selected injection condition and extend to apparent surface to make atenuator region from the surface of the semiconductor wafer injecting initial contact.But, also can use other injection condition, comprise the injection not needing above-mentioned resist.
Then, in step 150, the semiconductor wafer wherein with impurity is separated into single semiconductor element along atenuator region.Semiconductor wafer is separated into the combination that single tube core comprises multiple different step or step.Such as, in one embodiment, the semiconductor wafer with atenuator region stands thermal stress, causes atenuator region broken, thus semiconductor element is separated.Wherein, thermal stress can be applied by carrying out annealing with proper temperature to the semiconductor wafer with the impurity be included in wherein.Person of skill in the art will appreciate that and make proper temperature that is needed for semiconductor crystal fragmentation and that simultaneously remain among distributed hot nargin.
Similarly, the semiconductor wafer with atenuator region also can stand mechanical stress to make atenuator region broken.Wherein, mechanical stress can be applied by the mechanical device rolled through the surface of semiconductor wafer.In an alternate embodiment of the invention, mechanical stress and thermal stress can be used to help being separated of semiconductor element.After semiconductor wafer is broken for single semiconductor element, process can stop at stopping step 155 place.
According to an embodiment of the present disclosure, flow process Figure 100 of Fig. 1 comprises the particular step that can be used for manufacturing semiconductor element.In an alternate embodiment of the invention, according to alternative embodiment of the present disclosure, more or less step can be used to manufacture semiconductor element.In addition, the particular order that each step is performed can change.Therefore, such as, in certain embodiments, step 130 and step 140 can perform prior to step 120.
Fig. 2 A-4B shows the treatment step that semiconductor wafer is separated into the embodiment of the method for single semiconductor element by display.Fig. 2 A initially shows semiconductor wafer 210.The wafer 210 illustrated in fig. 2 comprises groove 260 and one or more die area 270.It will be appreciated by those skilled in the art that groove 260 may be used for the various different feature coordinated along the center (or other known points) of wafer 210 on wafer 210, comprise the position of particular semiconductor feature, die area 270 etc.
This one or more die area 270 represents the tube core border for different die on semiconductor wafer 210.These tube core borders finally can become the road plan that wafer 210 is cut into single semiconductor element.In addition, no matter whether use amplifying device, die area 270 all may or can not by human eye finding.The quantity of the die area 270 on given wafer 210 changes according to the size of wafer 210 and the expectation size of each independent die area 270 usually.
Turn back to Fig. 2 B, show the enlarged drawing of a part for the semiconductor wafer 210 of Fig. 2 A.As shown in the figure, semiconductor wafer 210 comprises the set of different materials, layer and feature.Such as, semiconductor wafer 210 comprises basalis 212 (such as, monocrystalline silicon in one embodiment), active characteristic layer 214 (such as, comprise transistor device in one embodiment), and interconnect feature layer 216 (such as, in one embodiment, comprising one or more interconnection layer).Except other possibilities, basalis 212, active characteristic layer 214 and interconnect feature layer 216 can comprise by arbitrary material above-mentioned or its set.Similarly, in this fabrication stage, in semiconductor wafer 210, other layers can be there are.
As shown in Figure 2 B, above semiconductor wafer 210, define the resist 220 of patterning, to expose the region 230 of semiconductor wafer 210.The process being similar to above-mentioned process may be used for patterning resist 220.In one embodiment, exposed region 230 is set to the link position that contiguous semiconductor element 270 is connected to each other.In another embodiment, exposed region 230 exposes each road plan in semiconductor wafer 210 at least partially.
In one embodiment, exposed region 230 has the width (w) being less than about 5 microns.In an alternate embodiment, exposed region 230 has the width being less than about 1 micron.Above-mentioned width (w) is significantly less than over the width of the saw blade that may use when semiconductor wafer 210 being separated into single semiconductor element or scoring tool.Therefore, the area occupied of semiconductor wafer 210 can significantly be saved.
Fig. 2 B be also show impurity 240 and is introduced in exposed region 230 by the split shed of resist 220.Except other possibility, can use and be similar to process discussed above impurity 240 is placed in semiconductor.As discussed above, impurity 240 is configured to the bonding in the interconnective link position of contiguous semiconductor element 270 of destruction semiconductor wafer 210.Impurity 240 can cause the atenuator region 250 in semiconductor wafer 210 further.In one embodiment, atenuator region 250 is essentially perpendicular to the initial surface extension being provided with impurity 240.This with may produce other that be substantially parallel to atenuator region that this surface extends and process and define striking contrast.
The embodiment of Fig. 2 A and 2B shows resist 220 and is used to impurity 240 to be accurately placed in Semiconductor substrate 210.But, there are other embodiments wherein not needing resist.Such as, existence wherein uses the known embodiment directly writing injection (directwriteimplant).Such as, the proton beam driven by XY platform can be used to impurity 240 to be included in Semiconductor substrate 210.
Fig. 3 A and 3B shows the semiconductor wafer 210 of Fig. 2 A and 2B after the region at least partially on the back side eliminating semiconductor wafer 210 (such as, relative with the surface that impurity 240 is set up at first surface).In one embodiment, traditional wafer back polishing is used to the thickness of semiconductor wafer 210 be reduced to about 200 microns of numerical value to about 400 micrometer ranges.In an alternate embodiment, more or less back side polishing can be used.The process at least partially at the back side of this removal semiconductor wafer 210 is designed to contribute to semiconductor wafer 210 to be separated into single semiconductor element.
Fig. 4 A and 4B shows the semiconductor wafer 210 with impurity 240 along the semiconductor wafer 210 in Fig. 3 A and 3B after atenuator region 250 is separated into single semiconductor element 410.As previously mentioned, semiconductor wafer 210 is separated into the process of single semiconductor element by means of increase stress.The embodiment of Fig. 4 A and 4B shows the application of the mechanical stress using roller 420 to apply.Although in this embodiment use roller 420 stress is provided, it will be understood by those of skill in the art that various other technology and device also can be used.Should again note, thermal stress or other forms of stress (such as, acoustics stress) also all can be used.
After showing to form one or more feature in the semiconductor wafer above with reference to the process disclosed in Fig. 1 to 4B, especially after defining interconnection structure, impurity is placed in semiconductor wafer.Some embodiment may be there is, wherein, on the semiconductor wafer or among form any feature before impurity is comprised in the semiconductor wafer.Similarly, some embodiment may be there is, wherein, on the semiconductor wafer or among form active feature after soon impurity is comprised in the semiconductor wafer.
Above-mentioned disclosed aspect of the present invention provides some benefit compared with other conventional process.Such as, above-mentioned open because tube core passage can be less than the passage allowed in other saw blade and ruling, thus can obtain the utilization rate of higher silicon.In addition, relative to buying and the saw blade that upholds one's heritage and scoring tool, institute uses the injection for semiconductor wafer being separated into singulated dies can be less, and therefore this may finally have lower processing cost.
About comprising the more details of impurity and other relevant informations, can at United States Patent (USP) the 6th, 335, No. 258, the 6th, 020, No. 252,5th, 877, No. 070,6th, find in 372, No. 609 and U.S. Patent Application Publication No. 2004/0171232 and No. 2004/0166649, above full content is incorporated herein by reference.
Relating to above-mentioned of the present disclosure it will be understood by those of skill in the art that is not deviating from the basis of protection scope of the present invention, can make other and further interpolation, deletion, substitutions and modifications to above-described embodiment.
Claims (9)
1., for semiconductor wafer being separated into a method for single semiconductor element, comprising:
The surf zone of the link position that contiguous semiconductor element impurity being placed in semiconductor wafer is connected to each other, described impurity is configured to destroy the bonding of contiguous described link position in described semiconductor wafer and produces atenuator region; And
After described region impurity being placed in semiconductor wafer, remove the apparent surface at least partially of described semiconductor wafer; And
To there is described impurity and the described described semiconductor wafer being removed part is separated into single semiconductor element along described atenuator region, be wherein separated described semiconductor wafer and comprise and utilize mechanical stress or acoustics stress to be separated described semiconductor wafer.
2. method according to claim 1, wherein, arranges impurity and comprises and being injected in described region by noble gas ion.
3. method according to claim 1, wherein, described region has the width being less than 1 micron.
4. method according to claim 1, wherein, described region has the width being less than 5 microns.
5. method according to claim 1, wherein, described impurity is placed in described semiconductor wafer by the opening in resist.
6. method according to claim 1, wherein, described impurity is placed in the road plan in described semiconductor wafer.
7. method according to claim 1, wherein, is separated described semiconductor wafer and comprises use roller generation mechanical stress to be separated described semiconductor wafer.
8. method according to claim 1, wherein, the width in described region is significantly less than the width of saw blade or scoring tool.
9. method according to claim 1, wherein, the position being at least partially removed part of apparent surface corresponds to the position of the atenuator region in described surface substantially.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200780053007A CN101809732A (en) | 2007-05-17 | 2007-05-17 | Method for separating a semiconductor wafer into individual semiconductor dies using an implanted impurity |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200780053007A Division CN101809732A (en) | 2007-05-17 | 2007-05-17 | Method for separating a semiconductor wafer into individual semiconductor dies using an implanted impurity |
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| CN105206572A true CN105206572A (en) | 2015-12-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201510500717.7A Pending CN105206572A (en) | 2007-05-17 | 2007-05-17 | Method separating semiconductor wafer into single semiconductor tube cores through impurity injection |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6372610B1 (en) * | 1999-12-20 | 2002-04-16 | Industrial Technology Research Institute | Method for die separation of a wafer by ion implantation |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6372610B1 (en) * | 1999-12-20 | 2002-04-16 | Industrial Technology Research Institute | Method for die separation of a wafer by ion implantation |
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