KR20100010841A

KR20100010841A - Semiconductor chip layout and semiconductor chip with chip seperation region

Info

Publication number: KR20100010841A
Application number: KR1020080071901A
Authority: KR
Inventors: 조윤래
Original assignee: 삼성전자주식회사
Priority date: 2008-07-23
Filing date: 2008-07-23
Publication date: 2010-02-02

Abstract

PURPOSE: A semiconductor chip layout and a semiconductor chip with a chip separation region are provided to separate a semiconductor chips from a semiconductor layout by forming a metal layer on a chip separation region of a scribe lane. CONSTITUTION: A scribe lane(20) is formed between main chips(10). A chip separation region(22) is formed within the scribe lane. Process patterns(12,14,16,18) are separated from the chip separation region and are arranged within the scribe lane. The process pattern comprises a test pattern or a photolithography pattern. The photolithography process pattern comprises an overlay key or an align key. The chip separation region has a linear type. The chip separation region is interposed between process patterns and main chip.

Description

Semiconductor chip layout and semiconductor chip with chip seperation region

The present invention relates to a semiconductor device, and more particularly, to a scribe lane structure for sawing of a semiconductor chip.

A semiconductor wafer, in which an integrated circuit is formed through a series of manufacturing processes, is separated into individual semiconductor chips, which is called a wafer sawing process. Conventional wafer sawing is accomplished by cutting a wafer along a scribe lane between semiconductor chips using a diamond wheel blade rotating at high speed. However, as the size of the semiconductor chip is reduced and the thickness of the wafer becomes thin, problems such as chipping, cracking, and peeling have occurred during sawing the wafer. This was developed.

1 is a view for explaining stealth laser sawing of the sawing technique using a laser. Referring to FIG. 1, stealth laser sawing focuses the laser light 3 on the inside of the wafer 1 to irradiate the laser light to the wafer 1 along the scribe lane to selectively modify the inside of the wafer 1. 2) form. Then, the tape supporting the wafer is extended to exert a force on the wafer, and the wafer is cut using the crystallinity of the wafer to be separated into individual semiconductor chips. Stealth laser sawing only selectively modifies the inside of the wafer and hardly absorbs the laser light on the wafer surface, so that the wafer surface is not melted and the wafer can be cut cleanly to separate the semiconductor chip.

In general, various test patterns (TEG) and photolithography patterns such as overlay keys or alignment keys are formed in the scribe lanes. These process patterns can be cut during wafer sawing as they are in the scribe lane after being used in the fabrication and testing process of the semiconductor chip. These process patterns may be formed of various materials, in particular test patterns include those made of a metallic material. However, if the metal patterns are continuously present on the way in which the wafer in the scribe lane is cut, the metal patterns may not be torn or cut, so that a portion of the wafer may not be completely separated from the wafer.

An object of the present invention is to provide a semiconductor chip and a semiconductor chip layout having a scribe lane structure that can prevent the tearing or unseparation of the metal layer in the wafer sawing process.

The layout of a semiconductor chip for achieving the purpose of the present invention is a scribe lane between the main chip; A chip isolation region in the scribe lane; Process patterns disposed in the scribe lane away from the chip isolation region; It includes.

The process patterns may include a test pattern or a pattern for photolithography, and the photolithography process pattern may include an overlay key or an alignment key.

The chip isolation region may be located between the process patterns and the main chip, and the chip isolation region may have a straight line shape.

A semiconductor chip for achieving another object of the present invention is a main chip formed on a substrate; A scribe lane between the main chips; A chip isolation region in the scribe lane; And process patterns disposed in the scribe lane away from the chip isolation region.

A semiconductor chip for achieving another object of the present invention is a main chip formed on a substrate; A scribe lane between the main chips; A chip isolation region in the scribe lane; Process patterns disposed in the main chips; It may include.

The process patterns may include a test pattern or a pattern for photolithography, and the pattern for photolithography may include an overlay key or an alignment key.

The test pattern may include a metal material.

The chip isolation region may be located between the patterns and the main chip, and the chip isolation region may have a straight line shape.

The chip isolation region may include a material layer of silicon, silicon oxide, silicon nitride, or silicon oxynitride.

The chip isolation region may have a width of 3-5 μm.

According to the present invention, a chip isolation region having no process patterns formed in the scribe lane is secured to prevent the semiconductor material from being torn or separated when the wafer is cut along the chip isolation region in stealth laser sawing. It can be separated cleanly and completely.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the present invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

In the present specification, the semiconductor chip sometimes includes a scribe lane between the main chip and the main chip on which the semiconductor element is formed, and also means only the main chip. For example, the expression that the semiconductor chip is separated is used to mean that the main chip is separated without including the scribe lane, and the expression of the layout of the semiconductor chip is used to mean the main chip and the scribe lane.

On the other hand, the layout in this specification does not mean the layout of the layer corresponding to one photo mask, but the layout of the entire component of the semiconductor chip including the scribe lane after the elements are formed on the semiconductor chip.

2 is a schematic plan view of a semiconductor wafer having a plurality of semiconductor chips according to embodiments of the present invention. Referring to FIG. 2, semiconductor chips 10 are repeatedly formed on the semiconductor wafer 100, and a scribe lane 20 is formed between the semiconductor chips 10.

3 is an enlarged view of a portion indicated by a square A in FIG. 2 of the present invention. Referring to FIG. 3, some of the main chips 10 face each other with the scribe lane 20 therebetween. The main chips 10 shown in FIG. 3 may be cell regions or other regions of the semiconductor chip. Process patterns such as the test pattern 12, the overlay key 14, the array key 16, and the metal bar pattern 18 are formed close to one side 20a of the scribe lane 20. The other side 20b of the scribe lane 20 is provided with a chip separation region 22 in which a laser beam is irradiated, the semiconductor wafer 100 is cut, and the main chips 10 are separated. Process patterns 12, 14, 16, and 18 are not formed in the chip isolation region 22, so that the process patterns 12, 14, 16, and 18 are not cut when the semiconductor wafer 100 is cut. The main chip 10 can be separated cleanly without taking.

As the semiconductor chip manufacturing process proceeds, various kinds of material layers may be stacked on the process patterns 12, 14, 16, and 18. In particular, the test pattern 12 and the metal bar pattern 18 may include metal layers among these material layers. The metal layers may include materials used for electrodes or wiring contacts, for example, aluminum, tungsten, copper, and the like. If metal layers are formed in the chip isolation region 22, as described above, the metal layers may be torn apart or unseparated without being separated cleanly, which may cause a defect.

In the scribe lane 20 of the semiconductor wafer of the present invention, the chip isolation region 22 and the process patterns 12, 14, 16, and 18 are disposed apart from each other, so that metal layers are not formed in the chip isolation region 22. For example, when the semiconductor wafer is a silicon wafer, the chip isolation region 22 may include a silicon-based material layer, that is, a silicon substrate, polysilicon, epitaxial silicon, a silicon oxide film, or a silicon nitride film. These silicon-based material layers can be cleanly separated together with the silicon wafer when a force is applied to the wafer after laser light irradiation inside the wafer by stealth laser sawing. Meanwhile, when the semiconductor wafer is made of another semiconductor material, the chip isolation region may be formed of layers of the semiconductor material series.

The use of stealth laser sawing can significantly reduce the width of the chip isolation area required compared to using diamond wheel blades. For example, when the width of the chip isolation region of about 3-5 mu m is secured, the semiconductor chip can be separated. Accordingly, the process patterns in the scribe lanes may be disposed to one side in the scribe lanes to provide chip separation regions in the spaces secured.

In the above embodiment, a test pattern, an overlay key, a photolithography pattern such as an alignment key, a metal bar pattern, and the like are used as the process pattern, but the process pattern includes various patterns including a laser ripping key used for laser fuse blowing. It may include.

4 is a view illustrating a portion of semiconductor chips formed on a semiconductor wafer according to another embodiment of the present invention. Referring to FIG. 4, main chips 30 are surrounded by scribe lanes 40, and process patterns 32, such as test patterns and photolithography patterns, are formed in the main chips 30. In the main chip 30, there is a free space except for a region where circuit patterns are formed, and process patterns 32 may be disposed in the free space. The scribe lane 40 in which the process patterns 32 are not formed may be reduced to a width that is required for the chip isolation region, for example, about 3-5 μm. If the width of the scribe lane 40 is reduced, more semiconductor chips can be formed in the semiconductor wafer, thereby effectively using the area of the semiconductor wafer.

According to the layout of the semiconductor chip according to the embodiments of the present invention, the process patterns in the scribe lane are disposed close to one side of the scribe lane, so that a chip isolation region having no pattern formed on the other side of the scribe lane may be secured. have. Alternatively, the process patterns may be arranged in the free space of the main chip to leave only the chip isolation region in the scribe lane.

In the stealth sawing process, the laser beam is irradiated to the chip isolation region (generally, the laser beam is irradiated from the back side of the wafer) to form a modified layer inside the semiconductor wafer. Then, by attaching a tape to the backside of the semiconductor wafer and extending the tape to apply a force to the semiconductor wafer, the semiconductor wafer is cut along the chip isolation region where the modification is deformed therein to separate the semiconductor chips individually.

Since there are no metal layers in the chip isolation region where the process patterns are not formed, the semiconductor wafer is cleanly cut without the problem that the metal layer on the chip isolation region is torn or unseparated when cutting the semiconductor wafer by applying force to the semiconductor wafer. Can be

Although the embodiments of the present invention have been described in detail above, the present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes without departing from the technical spirit of the present invention are made. It will be apparent to one of ordinary skill in the art that this is possible.

1 is a view for explaining stealth laser sawing.

2 is a schematic plan view of a semiconductor wafer having a plurality of semiconductor chips according to embodiments of the present invention.

FIG. 3 is an enlarged view of a portion indicated by a box A in FIG. 2.

4 is a view illustrating a portion of semiconductor chips formed on a semiconductor wafer according to another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10, 30: main chip 12, 14, 16, 18: process patterns

20, 40: scribe lane 22: chip separation region

Claims

Scribe lanes between main chips;

A chip isolation region in the scribe lane; And

Process patterns disposed in the scribe lane away from the chip isolation region; The layout of a semiconductor chip comprising a.

The layout of claim 1, wherein the process patterns include a test pattern or a pattern for photolithography.

The layout of claim 2, wherein the photolithography process pattern comprises an overlay key or an alignment key.

The layout of claim 1, wherein the chip isolation region is positioned between the process patterns and the main chip.

The layout of claim 4, wherein the chip isolation region has a straight line shape.

Main chips formed on the substrate;

A scribe lane between the main chips;

A chip isolation region in the scribe lane; And

Process patterns disposed in the scribe lane away from the chip isolation region; Semiconductor chip comprising a.

Main chips formed on the substrate;

A scribe lane between the main chips;

A chip isolation region in the scribe lane; And

Process patterns disposed in the main chips; Semiconductor chip comprising a.

The semiconductor chip of claim 6, wherein the process patterns include a test pattern or a pattern for photolithography.

The semiconductor chip of claim 6, wherein the photolithography pattern comprises an overlay key or an alignment key.

The semiconductor chip of claim 6, wherein the test pattern comprises a metal material.

The semiconductor chip of claim 6, wherein the chip isolation region is positioned between the patterns and the main chip.

The semiconductor chip of claim 11, wherein the chip isolation region has a straight line shape.

The semiconductor chip of claim 6, wherein the chip isolation region does not include a metal layer.

The semiconductor chip of claim 13, wherein the chip isolation region comprises a material layer of silicon, silicon oxide, silicon nitride, or silicon oxynitride.

The semiconductor chip of claim 6, wherein the chip isolation region has a width of 3-5 μm.

The semiconductor chip of claim 7, wherein the process patterns are formed in free spaces of the main chips.

The semiconductor chip of claim 7, wherein the process patterns are formed at edges of the main chips.