JP5271279B2 - Method for manufacturing a high heat dissipation substrate - Google Patents

Description

  The present invention relates to a method for producing a composite structure having high heat dissipation properties, which is provided for a substrate as a crystal growth of a single crystal layer intended to receive an electronic device or component or a substrate comprising such a single crystal layer.

  These structures would be particularly useful for dissipating heat generated by the above components in operation.

  Such components are particularly useful when generating a large amount of thermal energy, such as high power frequency components (typically 900 MHz and above). Indeed, if the temperature of the single crystal layer is higher than the threshold temperature, the component can be disturbed or even damaged.

  In order to overcome this obstacle, the single crystal layer typically has better charge transport properties (such as high voltage charge saturation, high breakdown voltage, etc.) than materials such as AsGa nitride semiconductor materials It is made with. This is especially true for HEMT (High Electron Mobility Semiconductor) type components.

A growth substrate made of bulk SiC single crystal, bulk <111> silicon or bulk sapphire (Al ₂ O ₃ ) is used to form this type of nitride semiconductor layer.

  However, the thermal impedance of <111> Si and sapphire is too high for some applications at high power frequencies where more of the released heat needs to be dissipated. Components can still be disturbed or damaged.

  Single crystal bulk SiC is a costly material, but is a reference material in terms of heat dissipation.

  Thus, there is a need for a substrate that sufficiently dissipates thermal energy at a low cost.

For this purpose, Patent Document 1 and Patent Document 2 disclose the creation of a composite structure using the following wafer bonding technique. That is,
-Providing the substrate and wafer on the upper single crystal layer;
Forming an oxide layer on the substrate and / or the upper layer,
Bonding the substrate and wafer such that the oxide layer and the top layer are at the bonding interface;
Reducing the wafer to remove the upper layer bonded to the substrate through the oxide layer to form the structure;
It is disclosed that the structure is heat treated to strengthen the bond.

  Currently, different techniques for shrinking wafers such as Smart Cut ™ (general description is described in Non-Patent Document 1) have been developed.

  The final structure has an upper layer on the oxide layer on the substrate.

  The top layer is composed of sapphire, Si <111>, SiC, or any other semiconductor material that ensures the growth quality of the useful layer composed of high frequency component materials such as GaN. May be.

  Additionally, the substrate is selected to have a high heat dissipation characteristic, for example-high heat conductivity-to dissipate the heat generated by the component.

  While growing on the composite layer, it is not necessary to provide a high crystal quality substrate, since the crystal quality of the useful layer is guaranteed by the top layer. For example, it is possible to provide a substrate made of a polycrystalline material such as polycrystalline SiC (poly SiC).

  Therefore, these types of composite structures are less expensive than single crystal SiC composite structures, are structures suitable for subsequent growth of useful layers, and have good heat dissipation characteristics.

US Pat. No. 6,328,796 US Patent Application Publication No. 2003/0064735

SILICON-ON-INSULATOR TECHNOLOGY: Materials to VLSI, 2nd Edition (Jean-Pierre COLINGE) or BESOI (Bond Etch Silicon On Insulator) “Semiconductor Wafer Bonding Science and Technology” by Q.-Y. Tong and U. Gosele-a Wiley Interscience publication, Johnson Wiley & Sons, Inc

  However, some designed components require good heat dissipation. The object of the present invention is to further increase the heat dissipation while producing the structure at low cost.

In order to achieve the above object and overcome the drawbacks of the prior art, according to a first aspect, the present invention is a method of manufacturing a composite structure having high heat dissipation characteristics, the structure comprising a support substrate and A top layer and an oxide layer between the support substrate and the top layer, the method comprising:
a) providing an upper layer of crystalline material;
b) a support made from a polycrystalline material having greater heat dissipation properties than a bulk single crystal silicon substrate having the same dimensions, such that an oxide layer is formed at the bonding interface to obtain the above structure; Bonding the upper layer with the substrate,
Characterized in that it further comprises a heat treatment of the structure in an inert gas atmosphere or a reducing atmosphere at a predetermined temperature and a predetermined duration for increasing the heat dissipation characteristics by decomposing at least part of the oxide layer,
Other optical properties of the above method are:
-Step b) forming an oxide layer on the substrate and / or on the upper layer, and contacting the upper layer with the substrate such that the oxide layer is the interface;
-Step a) providing a donor substrate with an upper layer, the method further comprising reducing the thickness of the donor substrate only to hold the upper layer bonded to the support substrate between step b) and the thermal treatment including,
-Before step a), a step of embedding atomic grains into the donor substrate to form a weak zone under the upper layer, the reduction of the donor substrate detecting the upper layer from the donor in the weak zone Including supplying energy to
The thickness of the support substrate is reduced by heat treatment and / or chemical treatment and / or application of mechanical force (CMP ...) before bonding;
The predetermined temperature is between 1100 ° C. and 1300 ° C., preferably between 1200 ° C. and 1300 ° C.,
-The predetermined duration is about 2 hours;
The oxide layer after bonding has a thickness between 10 nm and 1000 nm, more preferably between 25 nm and 50 nm;
The upper layer after the transition has a thickness between 25 nm and 1000 nm, preferably about 100 nm;
The substrate is made of polycrystalline silicon carbide;
The heat treatment is in a non-oxidizing atmosphere, eg hydrogen or argon.

According to a second aspect, the present invention proposes a structure with high heat dissipation characteristics, including:
-Consists of upper layer, crystalline material-Support substrate made of polycrystalline material having thermal conductivity greater than that of single crystal silicon substrate having the same dimensions

The selective features of this structure are shown below:
The support substrate and the top layer are in direct contact;
The support substrate is made of silicon carbide,
The upper layer consists of single crystal silicon <111> or SiC.

  According to a third aspect, the present invention proposes to use the above structure as a substrate for crystal growth of at least one layer of material for high frequency applications.

  Other features, objects, and advantages of the invention illustrated in the following drawings will become apparent in the following description.

It is sectional drawing of the structure according to a prior art. FIG. 4 shows a process with a process of manufacturing the structure of the present invention. It is a figure which shows the other process of the process which manufactures the structure of this invention. It is a figure which shows the other process of the process which manufactures the structure of this invention. FIG. 3 exemplarily illustrates steps of a process for manufacturing the structure of the present invention.

  Referring to FIG. 1, a structure 50 is shown in which processing according to the present invention is performed.

  The structure 50 is a composite structure arranged for high heat dissipation and can dissipate more heat than, for example, a bulk single crystal structure having the same dimensions.

  The structure 50 includes a support substrate 20, an oxide layer 30, and a semiconductor upper layer 10.

  The support substrate 20 reinforces the entire structure 50. For this purpose, it has a sufficient thickness, typically 100 micrometers.

  The support substrate 20 is made from a material having good heat dissipation properties and can dissipate more heat than a bulk single crystal structure having the same dimensions, for example. This material is further comprised of low cost materials such as low quality crystalline materials. It can be formed by stacking polycrystalline SiC, polycrystalline diamond, or at least two of these materials with the other material. The upper layer 10 is made of at least one crystalline material.

  The top layer 10 can be made of SiC, Si <111>, or other crystalline material. The advantages of Si <111> material can be used for further GaN growth, compatible with GaN lattices.

  The top layer 10 may alternatively consist of a combination or superposition of at least two of these materials and / or superposition of several sublayers.

  The top layer 10 may be suitable to be a substrate for secondary growth of useful layers, such as useful layers for receiving electronic or optoelectronic components or for high frequency applications.

  According to the invention, the top layer 10 is advantageously thin. Its thickness is advantageously about 1000 nm or less. For example, the top layer 10 has a thickness between about 25 nm and 1000 nm, preferably about 100 nm.

  Insulating layer 30 is an oxide layer, embedded in structure 50 and located between support substrate 20 and upper layer 10.

  The oxide layer 30 is composed of the crystal material of the upper layer 10 and / or the oxide of the upper portion of the support substrate 20.

For example, when the upper layer 10 is made of silicon, the oxide layer 30 is made of SiO ₂ .

  Its thickness is between 50 nm and below, and more particularly between about 10 nm and 100 nm.

  Referring to FIGS. 2A-2C, manufacturing this structure 50 can be done by wafer bonding techniques.

  In particular, referring to FIG. 2A, it can be implemented first by providing a wafer 70 having the top layer 10 therein. The top layer 10 on the surface of the wafer 70 defines a front layer on the rear portion 60 of the wafer 70.

  The second step consists of bonding the wafer 70 to the support substrate 20 so that the upper layer 10 is adjacent to the bonding interface.

  As an advantage, the coupling is first realized by well-known coupling techniques (for example, see Non-Patent Document 2 for details). Thus, for example, a molecular bond of a hydrophilic surface or a surface involved in hydrophilicity will be made.

  A known cleaning step may be performed immediately prior to bonding.

  Optionally, the plasma treatment of one and / or the other of the two surfaces is combined, followed by annealing or RTA treatment (rapid thermal annealing).

  Prior to bonding, the oxide layer 30 is formed on the top layer 10 and / or the substrate 20 and is bonded and then buried at the bonding interface.

  The oxide layer 30 may be formed by oxidation of the upper layer 10 and / or the substrate 20.

For example, when the upper layer 10 is Si (111) or SiGe (111), the SiO ₂ layer 30 can be formed on the surface by deposition or thermal oxidation.

For example, SiO ₂ aggregates can be deposited.

  Alternatively, both the top layer 10 and the surface of the substrate 20 also comprise an oxide layer formed by deposition or by oxidation.

  The oxide configuration parameters are adjusted so that the oxide layer 30 has a predetermined thickness to provide a thermal barrier between the top layer 10 and the substrate 20.

  As described above with reference to FIG. 2B, substrate 20 and wafer 70 are bonded such that oxide layer 30 is at the interface.

  Optionally, at least one step of the heat treatment is additionally performed to strengthen the bond at the interface.

  Referring to FIG. 2C, the wafer 70 is reduced so that all the rear portions 60 are removed. Only the upper layer 10 is kept.

  Any of the wafer reduction techniques can be adopted, chemical etching technique, lapping and polishing, Smart Cut (trademark) technique well known to those skilled in the art (for example, see pages 50 and 51 of Non-Patent Document 1) alone or in combination. Adopted.

  In particular, when employing Smart Cut ™, atoms (such as hydrogen, helium, a combination of the two, and / or atoms) are weak in energy and quantity at depths close to the thickness of the top layer 10. With the wafer selected to form a zone, the wafer 70 is embedded prior to bonding. The embedding can be performed before or after the thin oxide layer 30 is formed. Eventually, once the bond is performed, the Smart Cut ™ technology will supply the appropriate energy (heat and / or mechanical energy) to break the bond in the weak zone and then back from the top layer 10. Including separating the portion 60.

  An additional step that ends not only to have a smooth and homogeneous top layer 10 but also to resolve potential deficiencies for the embedding step (by CMP polishing, RTA cleaning, etc.) is performed after the reduction step. Can be done.

  According to the present invention, other steps may be provided without limitation.

  The resulting structure 50 comprises an upper layer 10, an oxide layer 30 and a support substrate 20 in succession.

  The heat treatment is performed in an inert gas atmosphere or a reducing atmosphere such as an argon or hydrogen atmosphere or a mixture thereof.

  The heat treatment is processed by oxygen dissipation through the upper layer 10 so that the thickness of the oxide layer 30 is reduced. The temperature and duration of the heat treatment are selected to stimulate the dissipation of the total amount of oxygen in the oxide layer 30 through the upper layer 10 than in the bulk substrate 20.

  Additionally, the thickness of the top layer 10 can be selected to stimulate the dissipation when formed. In fact, the thinner the top layer 10, the faster the dissipation.

  This dissipation can also be accelerated by the fact that the atmosphere is selected from an inert gas, as estimated from the boundary conditions.

In particular, when the inert atmosphere contains argon and the upper layer 10 is made of silicon, the following reaction occurs on the surface of the semiconductor layer 10.
Si + Oi → SiO ↑

  In order to increase the performance of this dissipation, the aforementioned deoxygenation of the surface of the semiconductor layer 10 can be performed.

  However, the main parameters that affect the dissipation time are the annealing temperature and the thickness of the semiconductor layer 10.

For example, the minimum annealing condition for decomposing ₂ nm of the SiO ₂ interface with respect to 100 nm of the upper Si <111> layer 10 in an Ar or H ₂ atmosphere is as follows:
-2 hours at 1100 ° C, or 10 minutes at 1200 ° C, or 4 minutes at-1250 ° C

  The temperature and duration of the heat treatment is selected to stimulate the total oxygen content of the oxide layer 30 to dissipate through the upper layer 10.

  Then, the thickness of the oxide layer 30 decreases for each predetermined value.

  Additionally, the thickness of the top layer 10 can be selected to stimulate the dissipation when formed.

  In particular, the thickness of the upper layer 10 and the heat treatment temperature determine the mean reduction rate of the oxide layer 30. The rate decreases as the thickness increases. The higher the temperature, the higher the rate.

  For example, the thickness and temperature described above can be predetermined to reach at least about 0.5 angstroms per minute of a small reduction rate of the oxide layer 30. For this purpose, for about 1200 ° C., the thickness of the Si single crystal layer 10 is selected to be lower than 2500 angstroms.

  It is only necessary to control the duration of the heat treatment so that the thickness of the oxide layer 30 is accurately reduced by a predetermined value.

  Alternatively, the thickness of the upper layer 10 is selected to reduce the oxide layer 30 by a predetermined value by performing a heat treatment at a predetermined duration and at a predetermined temperature.

  The predetermined temperature is selected from about 1000 ° C. to 1300 ° C., particularly in the vicinity of 1200 ° C. and / or 1300 ° C.

  The thickness of the top layer 10 is between about 25 and about 1000 nanometers, the predetermined temperature is about 1200 ° C., and the predetermined duration is between about 5 minutes and 5 hours.

  The heat treatment is performed so as to remove the entire oxide layer 30 or a part thereof.

  The final structure 50 after the heat treatment no longer includes only a part of the oxide layer 20 or only a thin oxide layer 20 between the upper layer 10 and the substrate 20. Since the oxide material has low heat dissipation, the heat dissipation of the entire structure 50 is improved after removing at least a portion of the oxide layer 30.

Another advantage of oxygen dissipation under a hydrogen atmosphere is the dissipation of deposited particles, such as boron atoms that are tapered at the bond boundary. In practice, a heat treatment under a hydrogen atmosphere will lead to the dissipation of boron atoms via evaporation at the top layer 10 and the surface of the top layer 10.
2B + 3H ₂ → B ₂ H ₆ ↑
Since boron reduces the resistance of HR silicon, the final structure 50 has a better interface with improved electronic properties.

  Furthermore, due to the low crystal quality of the polycrystalline material constituting the support substrate 20 and its thermal conductivity, the final temperature of the heat treatment is a slip line configuration (the final temperature can be up to 1300 ° C.) A steep rise in temperature (or temperature drop) can be reached without leading to slip line formation. Thanks to the reduced manufacturing time and the choice of bulk structure, the heat dissipation properties of the final structure 50 are increased while the manufacturing cost is consequently reduced.

  Finally, silicon HR (high resistivity) is not necessary. There may also be applications that require electronic conductivity in the substrate, thus including the use of other materials.

Specific Embodiment Details Referring to FIG. 3, a poly SiC substrate 20 is bonded to a Si (111) wafer 70.

Oxide layer 30 is formed on silicon wafer 70 and / or poly SiC substrate 20. The oxide layer 30 on the wafer 70 is formed thermally or by deposition, while the oxide layer 30 on poly SiC is deposited by PECVD (Plasma-Enhanced Chemical Vapor Deposition) or LPCVD (Low Pressure Chemical Vapor Deposition). It is formed. The thickness of the global oxide layer, here SiO ₂ , is between about 25 nm and 50 nm.

  Smart Cut ™, implantation of the donor of the substrate 20 prior to bonding leads to the formation of a weak zone 15. And the transfer from the thin Si (111) layer 10 to the substrate 20 is acquired by heat to break the mechanical bond in the weak zone 15 after the application of mechanical force and / or. .

  Since poly SiC may have a coarse bond, the LPCVD oxide 30 is preferably polished to reduce its roughness before being bonded to the Si (111) wafer 70.

  Bonds are acquired by molecular bonds and the interface is reinforced by heat treatment. This heat treatment decomposes the insulating layer 30 by diffusion of oxygen. This heat treatment is caused at a temperature comprised between 1150 ° C. and 1250 ° C., more precisely at 1200 ° C., for about 5 minutes to 5 hours (preferably 2 hours) in an atmosphere containing hydrogen or argon or an atmosphere containing both. .

  As a result, the oxide layer 30 is completely decomposed.

Claims (13)

A method for improving the high heat dissipation characteristics of a composite structure, the structure comprising:
A supporting substrate having higher heat dissipation characteristics than a bulk single crystal silicon substrate of the same size;
An upper layer of crystalline material;
Comprising an oxide layer between the support substrate and the top layer, the method comprising:
Decomposing at least a portion of the oxide layer by subjecting the structure to an internal heat treatment in a reducing atmosphere at a predetermined temperature and for a predetermined duration.   The method of claim 1, further comprising forming an oxide layer on the substrate and / or the upper layer prior to the decomposing step, and bonding the upper layer to the substrate such that the oxide layer is at the interface. the method of.   3. The method of claim 1 or 2, further comprising providing a donor substrate having the upper layer and reducing the thickness of the donor substrate only to hold the upper layer coupled to the support substrate. Method.   Embedding atomic grains in the donor substrate to form a weak zone below the upper layer, wherein the reducing of the donor substrate provides energy to separate the upper layer from the donor in the weak zone The method according to claim 3, further comprising:   The method according to any one of claims 1 to 4, wherein the predetermined temperature is between 1100 ° C and 1300 ° C.   6. The method of claim 5, wherein the predetermined temperature is between 1200 <0> C and 1300 <0> C.   7. A method according to any one of claims 1 to 6, characterized in that the predetermined duration is 2 hours.   7. A method according to claim 1, wherein the combined oxide layer has a thickness between 10 nm and 100 nm.   9. The method of claim 8, wherein the combined oxide layer has a thickness between 25 nm and 50 nm.   10. A method according to any of claims 1 to 9, characterized in that the upper layer after transfer has a thickness between 25 nm and 1000 nm.   The method of claim 10, wherein the upper layer after the transfer has a thickness of 100 nm.   12. The method according to claim 1, wherein the upper layer is made of silicon carbide and / or silicon <111>. The heat treatment method according to any one of claims 1 to 12 under a hydrogen atmosphere, was or that being a mixed atmosphere of hydrogen and argon.

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