FR2845523B1 - METHOD FOR MAKING A SUBSTRATE BY TRANSFERRING A DONOR WAFER HAVING FOREIGN SPECIES, AND ASSOCIATED DONOR WAFER - Google Patents

METHOD FOR MAKING A SUBSTRATE BY TRANSFERRING A DONOR WAFER HAVING FOREIGN SPECIES, AND ASSOCIATED DONOR WAFER

Info

Publication number
FR2845523B1
FR2845523B1 FR0212405A FR0212405A FR2845523B1 FR 2845523 B1 FR2845523 B1 FR 2845523B1 FR 0212405 A FR0212405 A FR 0212405A FR 0212405 A FR0212405 A FR 0212405A FR 2845523 B1 FR2845523 B1 FR 2845523B1
Authority
FR
France
Prior art keywords
donor wafer
thin layer
substrate
foreign species
thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0212405A
Other languages
French (fr)
Other versions
FR2845523A1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to FR0212405A priority Critical patent/FR2845523B1/en
Priority to US10/678,127 priority patent/US7008859B2/en
Priority to AT03292465T priority patent/ATE477589T1/en
Priority to DE60333712T priority patent/DE60333712D1/en
Priority to EP03292465A priority patent/EP1408545B1/en
Priority to JP2003348741A priority patent/JP4854921B2/en
Publication of FR2845523A1 publication Critical patent/FR2845523A1/en
Application granted granted Critical
Publication of FR2845523B1 publication Critical patent/FR2845523B1/en
Priority to US11/274,264 priority patent/US7535115B2/en
Priority to US12/139,609 priority patent/US7645684B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2258—Diffusion into or out of AIIIBV compounds

Abstract

The invention provides a method of producing a substrate comprising a thin crystalline layer transferred from a donor wafer onto a support, said thin layer including one or more foreign species intended to modify its properties, the method being characterized in that it comprises the following steps in sequence: implanting atomic species into a zone of the donor wafer (20) that is substantially free of foreign species (24), to form an embrittlement zone (22) below a bonding face, the embrittlement zone and the bonding face delimiting a thin layer (23) to be transferred; bonding the donor wafer (20), at the level of its bonding face, to a support (10); applying stresses in order to produce a cleavage in the region of the embrittlement zone (22) to obtain a substrate comprising the support (10) and the thin layer (23); and in that it further comprises a step of diffusing foreign species (24) into the thickness of the thin layer (23) prior to implantation or after fracture, suited to modify the properties of the thin layer, in particular its electrical or optical properties. <??>Application to producing substrates with a thin InP layer rendered semi-insulating by iron diffusion.
FR0212405A 2002-10-07 2002-10-07 METHOD FOR MAKING A SUBSTRATE BY TRANSFERRING A DONOR WAFER HAVING FOREIGN SPECIES, AND ASSOCIATED DONOR WAFER Expired - Fee Related FR2845523B1 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR0212405A FR2845523B1 (en) 2002-10-07 2002-10-07 METHOD FOR MAKING A SUBSTRATE BY TRANSFERRING A DONOR WAFER HAVING FOREIGN SPECIES, AND ASSOCIATED DONOR WAFER
US10/678,127 US7008859B2 (en) 2002-10-07 2003-10-06 Wafer and method of producing a substrate by transfer of a layer that includes foreign species
DE60333712T DE60333712D1 (en) 2002-10-07 2003-10-07 Method for the production of a substrate by the transfer of a donor wafer with foreign atoms, and a corresponding donor wafer
EP03292465A EP1408545B1 (en) 2002-10-07 2003-10-07 A method of producing a substrate by transferring a donor wafer comprising foreign species, and an associated donor wafer
AT03292465T ATE477589T1 (en) 2002-10-07 2003-10-07 METHOD FOR PRODUCING A SUBSTRATE BY TRANSFERRING A DONOR WAFER WITH FOREIGN ATOMS, AND A CORRESPONDING DONOR WAFER
JP2003348741A JP4854921B2 (en) 2002-10-07 2003-10-07 Method of manufacturing a substrate by transferring a donor wafer containing foreign species and associated donor wafer
US11/274,264 US7535115B2 (en) 2002-10-07 2005-11-16 Wafer and method of producing a substrate by transfer of a layer that includes foreign species
US12/139,609 US7645684B2 (en) 2002-10-07 2008-06-16 Wafer and method of producing a substrate by transfer of a layer that includes foreign species

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0212405A FR2845523B1 (en) 2002-10-07 2002-10-07 METHOD FOR MAKING A SUBSTRATE BY TRANSFERRING A DONOR WAFER HAVING FOREIGN SPECIES, AND ASSOCIATED DONOR WAFER

Publications (2)

Publication Number Publication Date
FR2845523A1 FR2845523A1 (en) 2004-04-09
FR2845523B1 true FR2845523B1 (en) 2005-10-28

Family

ID=32011448

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0212405A Expired - Fee Related FR2845523B1 (en) 2002-10-07 2002-10-07 METHOD FOR MAKING A SUBSTRATE BY TRANSFERRING A DONOR WAFER HAVING FOREIGN SPECIES, AND ASSOCIATED DONOR WAFER

Country Status (6)

Country Link
US (3) US7008859B2 (en)
EP (1) EP1408545B1 (en)
JP (1) JP4854921B2 (en)
AT (1) ATE477589T1 (en)
DE (1) DE60333712D1 (en)
FR (1) FR2845523B1 (en)

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US6912330B2 (en) * 2001-05-17 2005-06-28 Sioptical Inc. Integrated optical/electronic circuits and associated methods of simultaneous generation thereof
FR2845523B1 (en) * 2002-10-07 2005-10-28 METHOD FOR MAKING A SUBSTRATE BY TRANSFERRING A DONOR WAFER HAVING FOREIGN SPECIES, AND ASSOCIATED DONOR WAFER
FR2856192B1 (en) * 2003-06-11 2005-07-29 Soitec Silicon On Insulator METHOD FOR PRODUCING HETEROGENEOUS STRUCTURE AND STRUCTURE OBTAINED BY SUCH A METHOD
US7538010B2 (en) * 2003-07-24 2009-05-26 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating an epitaxially grown layer
FR2857983B1 (en) * 2003-07-24 2005-09-02 Soitec Silicon On Insulator PROCESS FOR PRODUCING AN EPITAXIC LAYER
EP1571705A3 (en) * 2004-03-01 2006-01-04 S.O.I.Tec Silicon on Insulator Technologies Process of making a semiconductor structure on a substrate
WO2006082467A1 (en) * 2005-02-01 2006-08-10 S.O.I.Tec Silicon On Insulator Technologies Substrate for crystal growing a nitride semiconductor
US7244630B2 (en) * 2005-04-05 2007-07-17 Philips Lumileds Lighting Company, Llc A1InGaP LED having reduced temperature dependence
FR2890489B1 (en) * 2005-09-08 2008-03-07 Soitec Silicon On Insulator METHOD FOR MANUFACTURING A SEMICONDUCTOR TYPE HETEROSTRUCTURE ON INSULATION
CN1992173B (en) * 2005-11-30 2010-04-21 硅起源股份有限公司 Method and structure for implanting bonded substrates for electrical conductivity
CN101573786B (en) * 2007-02-08 2011-09-28 硅绝缘体技术有限公司 Method of fabrication of highly heat dissipative substrates
US20090092159A1 (en) * 2007-05-28 2009-04-09 Sumitomo Electric Industries, Ltd. Semiconductor light-emitting device with tunable emission wavelength
US20090174018A1 (en) * 2008-01-09 2009-07-09 Micron Technology, Inc. Construction methods for backside illuminated image sensors
FR2926674B1 (en) 2008-01-21 2010-03-26 Soitec Silicon On Insulator METHOD FOR MANUFACTURING COMPOSITE STRUCTURE WITH STABLE BONDING OXIDE LAYER
KR101595307B1 (en) * 2008-02-26 2016-02-26 소이텍 Method for fabricating a semiconductor substrate
US20100044827A1 (en) * 2008-08-22 2010-02-25 Kinik Company Method for making a substrate structure comprising a film and substrate structure made by same method
EP2202795A1 (en) * 2008-12-24 2010-06-30 S.O.I. TEC Silicon Method for fabricating a semiconductor substrate and semiconductor substrate
FR2953328B1 (en) * 2009-12-01 2012-03-30 S O I Tec Silicon On Insulator Tech HETEROSTRUCTURE FOR ELECTRONIC POWER COMPONENTS, OPTOELECTRONIC OR PHOTOVOLTAIC COMPONENTS
US8748288B2 (en) * 2010-02-05 2014-06-10 International Business Machines Corporation Bonded structure with enhanced adhesion strength
EP2654075B1 (en) * 2010-03-31 2016-09-28 EV Group E. Thallner GmbH Method for permanently connecting two metal surfaces
FR2961948B1 (en) * 2010-06-23 2012-08-03 Soitec Silicon On Insulator PROCESS FOR TREATING A COMPOUND MATERIAL PART
FR2977069B1 (en) 2011-06-23 2014-02-07 Soitec Silicon On Insulator METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE USING TEMPORARY COLLAGE
RU2469433C1 (en) * 2011-07-13 2012-12-10 Юрий Георгиевич Шретер Method for laser separation of epitaxial film or layer of epitaxial film from growth substrate of epitaxial semiconductor structure (versions)
US8872189B2 (en) 2011-08-05 2014-10-28 Sumitomo Electric Industries, Ltd. Substrate, semiconductor device, and method of manufacturing the same
FR2982071B1 (en) * 2011-10-27 2014-05-16 Commissariat Energie Atomique METHOD FOR SMOOTHING A SURFACE BY THERMAL TREATMENT
FR2994766B1 (en) * 2012-08-23 2014-09-05 Commissariat Energie Atomique METHOD FOR TRANSFERRING INP FILM
FR3007892B1 (en) * 2013-06-27 2015-07-31 Commissariat Energie Atomique METHOD FOR TRANSFERRING A THIN LAYER WITH THERMAL ENERGY SUPPLY TO A FRAGILIZED AREA VIA AN INDUCTIVE LAYER
CN105374664A (en) * 2015-10-23 2016-03-02 中国科学院上海微系统与信息技术研究所 Preparation method of InP film composite substrate
FR3045678B1 (en) * 2015-12-22 2017-12-22 Soitec Silicon On Insulator METHOD FOR MANUFACTURING A MONOCRYSTALLINE PIEZOELECTRIC LAYER AND MICROELECTRONIC, PHOTONIC OR OPTICAL DEVICE COMPRISING SUCH A LAYER
US10985204B2 (en) * 2016-02-16 2021-04-20 G-Ray Switzerland Sa Structures, systems and methods for electrical charge transport across bonded interfaces
CN113223928B (en) * 2021-04-16 2024-01-12 西安电子科技大学 Gallium oxide epitaxial growth method based on transfer bonding

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FR2845523B1 (en) * 2002-10-07 2005-10-28 METHOD FOR MAKING A SUBSTRATE BY TRANSFERRING A DONOR WAFER HAVING FOREIGN SPECIES, AND ASSOCIATED DONOR WAFER
US7169226B2 (en) * 2003-07-01 2007-01-30 International Business Machines Corporation Defect reduction by oxidation of silicon

Also Published As

Publication number Publication date
EP1408545B1 (en) 2010-08-11
JP2004179630A (en) 2004-06-24
DE60333712D1 (en) 2010-09-23
US20060060922A1 (en) 2006-03-23
US20080248631A1 (en) 2008-10-09
US7535115B2 (en) 2009-05-19
JP4854921B2 (en) 2012-01-18
EP1408545A3 (en) 2004-08-04
US20040121558A1 (en) 2004-06-24
US7645684B2 (en) 2010-01-12
EP1408545A2 (en) 2004-04-14
US7008859B2 (en) 2006-03-07
FR2845523A1 (en) 2004-04-09
ATE477589T1 (en) 2010-08-15

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Legal Events

Date Code Title Description
CD Change of name or company name

Owner name: SOITEC, FR

Effective date: 20120423

Owner name: COMMISSARIAT A L ENERGIE ATOMIQUE, FR

Effective date: 20120423

ST Notification of lapse

Effective date: 20160630