CN1992173B - Method and structure for implanting bonded substrates for electrical conductivity - Google Patents
Method and structure for implanting bonded substrates for electrical conductivity Download PDFInfo
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- CN1992173B CN1992173B CN2006101629001A CN200610162900A CN1992173B CN 1992173 B CN1992173 B CN 1992173B CN 2006101629001 A CN2006101629001 A CN 2006101629001A CN 200610162900 A CN200610162900 A CN 200610162900A CN 1992173 B CN1992173 B CN 1992173B
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
A partially completed multi-layered substrate, e.g., silicon on silicon. The substrate has a thickness of material from a first substrate. The thickness of material comprises a first face region. The substrate has a second substrate having a second face region. Preferably, the first face region of the thickness of material is joined to the second face region of the second substrate. The substrate has an interface region formed between the first face region of the thickness of material and the second face region of the second substrate. A plurality of particles are implanted within a portion of the thickness of the material and a portion of the interface region to electrically couple a portion of the thickness of material to a portion of the second substrate.
Description
The cross reference of related application
The application is the non-temporary patent application of submitting on November 15th, 2005 the 11/280th of the U.S., the part continuity of No. 016 (application attorney docket 018419-017710 number), and require its priority, this non-temporary patent application requires the U.S. Provisional Patent Application the 60/630th of submission on November 24th, 2004, the priority of No. 800 (application attorney docket 018419-017700 number), above-mentioned patent is transferred the possession of separately jointly, and content separately is incorporated herein by reference.
Technical field
The present invention relates to the manufacturing of substrate.More specifically, the invention provides a kind of technology, it comprises that utilization for example is used for injection technique that semiconductor integrated circuit makes forms conduction region between bonded substrate method and apparatus.But will recognize that the present invention has wideer range of application; It may be used on being used for other substrate of the three-dimension packaging of multilevel integration device and integrated-semiconductor device, photonic device, piezoelectric device, MEMS (micro electro mechanical system) (" MEMS "), transducer, actuator, solar cell, flat-panel monitor (for example, LCD, AMLCD), biology and biomedical articles etc.
Integrated circuit is formed on the chip of semi-conducting material.These integrated circuits comprise several thousand even millions of transistors and other device usually.Particularly, be desirably in and put transistor as much as possible in the given semiconductor regions, because more transistor generally provides more function, and less chip means more chip and lower cost on each wafer.
Some integrated circuits can be made on the monocrystalline that is commonly referred to " body " silicon wafer (that is monocrystal) silicon.The general mutual isolation of device on this " body " silicon wafer.Proposed or used multiple technologies that these devices on the body silicon wafer are isolated mutually, as local oxidation of silicon (" LOCOS ") technology, trench isolations etc.Yet these technology are not hard-core.For example, traditional isolation technology need use useful wafer surface quite a large amount of on the chip long-pending, and usually can produce uneven surface owing to the product of isolation technology.These considerations arbitrary or both have generally limited attainable integrated level on given chip.In addition, trench isolations need be utilized reactive ion etching process usually, and it is very consuming time and be difficult to accurately realize.Greater than 200 millimeters body silicon wafers be not do not have a defective and can reduce total device yield etc.
A kind ofly realize that the method for ultra-large integrated (" VLSI ") or integrated very on a large scale (" ULSI ") is to utilize epitaxial silicon wafer, it is commonly referred to " epitaxial wafer ".Epitaxial wafer has the high quality single crystal silicon materials that one deck limits the surface that covers the body substrate usually.The high-quality silicon layer is provided for making the good locations of device, has the rate of finished products higher than the body silicon wafer material of routine usually.The epitaxial silicon process reactor that the high quality silicon material can utilize the ASM in the Applied Material company in Santa Clara city or Phoenix, AZ city to make usually deposits.
Epitaxial wafer also has other advantage that is better than the body silicon technology.For example, epitaxial wafer has almost ideal crystal property, and it can improve speed, function and the reliability of device.In addition, epitaxial wafer can provide the device yield higher than traditional body wafer usually.Yet, on epitaxial silicon wafer, making device, also wait to solve about a lot of settled problem of on the piece silicon wafer, making device.Epitaxial silicon wafer can utilize epitaxial reactor to form, and epitaxial reactor is bought costliness usually and is difficult to maintenance.The technology that forms epitaxial silicon is also very slow and consuming time.Therefore, the epitaxial silicon wafer of gained is usually expensive and can not be used for making such as dynamic random access memory (that is, a lot of commerce DRAM) and so on or general device.
The another kind of substrate of realizing that extensive integrated method utilizes bonding to be formed by the silicon supporting material usually.This bonding wafer utilizes layer transfer technology to form usually, United States Patent (USP) the 6th as the Silicon Genesis company that transfers the San Jose city jointly, describe in 013, No. 563 people such as (" ") Henley, its content is incorporated herein by reference.People such as Henley have narrated the controlled separating technology that is used to make MULTILAYER SUBSTRATE.This bonded substrate comprises silicon on the insulator that is commonly referred to SOI and other.Though making existing a lot of improvement on the substrate, some restriction that should overcome in addition.In specification full text, these restrictions and hereinafter more concrete have been described.
As mentioned above, can find out that the improved technology that is used to make multi-layer crystal chip makes us expecting very much.
Summary of the invention
According to the present invention, provide the manufacturing technology that is used for substrate.More specifically, the invention provides a kind of technology, it comprises that utilization for example is used for injection technique that semiconductor integrated circuit makes forms conduction region between the substrate of bonding method and apparatus.But will recognize that the present invention has wideer range of application, it also may be used on being used for other substrate of the three-dimension packaging of multilevel integration device and integrated-semiconductor device, photonic device, piezoelectric device, MEMS (micro electro mechanical system) (" MEMS "), transducer, actuator, solar cell, flat-panel monitor (for example, LCD, AMLCD), biology and biomedical articles etc.
In specific embodiment, the invention provides the technology that is used to form MULTILAYER SUBSTRATE (for example, silicon-silicon).This technology comprises provides first substrate, and it has one deck with the material of removing.In specific embodiment, the thickness of material can be about 8000 dusts or bigger.This floor comprises the first surface district with the material of removing.Technology comprises that the first surface district with first substrate engages with the second surface district of second substrate, so that form the boundary zone between the second surface district of the first surface district of first substrate and second substrate.Preferably, according to specific embodiment, can utilize the bonding technology that has insulating barrier etc. to form joint.Perhaps, can not have insulating material according to the specific embodiment boundary zone but have resistance characteristic.This technology comprises from first substrate removes second surface district bonding that layer of material keeps the first surface district of first substrate and second substrate simultaneously.Preferably, this layer material can utilize layer transfer process or similar technology to remove.In preferred embodiment, according to specific embodiment, particle be conduction or also can have other characteristic so that electrically contacting or be coupled between first surface district and the second surface district.
In specific embodiment, this method forms the mask layer of the surface region that covers layer of material, so that form a part of exposed region of this layer material.This method is injected into particle in the exposed region and passes a part of boundary zone and makes the layer of material of this part be coupled to second substrate to form the particle zone near this a part of boundary zone.In specific embodiment, this method causes comprising at least the formation of exposed region and this layer material injection region partly.This method also makes the injection region carry out at least Technology for Heating Processing so that the injection region crystallization at least.
In another specific embodiment, the invention provides the MULTILAYER SUBSTRATE that part is finished, for example silicon-silicon.This substrate have by first substrate constituted layer of material.This layer material comprises the first surface district.This substrate also has second substrate, and it has the second surface district.Preferably, the first surface district of layer of material joins the second surface district of second substrate to.Substrate has the boundary zone between the second surface district of the first surface district that is formed at layer of material and second substrate.A plurality of particles are injected in this layer material part and the boundary zone part, this layer material partly is electrically coupled to the second substrate part.
Can realize being better than the lot of advantages of routine techniques by the present invention.For example, present technique provides the wieldy technology that relies on conventional art.In certain embodiments, this method provides higher device yield.In addition, this method provides can be under the situation of traditional equipment and technology not being carried out substantial modification compatible mutually with traditional technology technology.Preferably, it is integrated to the invention provides the improved technology that is used for advanced integrated circuit (IC)-components.In addition, this technology provides the multi-layer substrate structure that is included in the electric coupling between first and second substrates.In specific embodiment, method and structure of the present invention also can reduce the bonding cavity at the place, boundary zone between two substrate member.The minimizing in bonding cavity can realize that by one or more injection particles are bonded on the H/H2 atom this obtains by existing hydrogen treatment process as an example, and the H/H2 atom may appear at the boundary zone and can impel the formation in this cavity in the boundary zone.Depend on embodiment, can realize one or more in these advantages.To describe these and other advantage and hereinafter more concrete in this specification in detail.
To more fully understand various other purpose of the present invention, feature and advantage with reference to detailed description and drawings.
Description of drawings
Fig. 1 is the schematic diagram that the method that is used to form multi-layer substrate structure according to one embodiment of present invention is shown;
Fig. 2 is applicable to the resistance of MULTILAYER SUBSTRATE and the simplification curve of the relation of injecting the degree of depth according to one embodiment of present invention;
Fig. 3 is the sketch of multi-layer substrate structure according to another embodiment of the invention;
Fig. 4 to 6 is schematic diagrames that the another kind of method that is used to form MULTILAYER SUBSTRATE according to another embodiment of the invention is shown.
Fig. 7 to 8 illustrates the schematic diagram that is used to form the another kind of method of multi-layer substrate structure according to embodiments of the invention.
Embodiment
According to the present invention, provide the technology that substrate is made that is used for.More particularly, the invention provides a kind of technology, it comprises that utilization for example is used for injection technique that semiconductor integrated circuit makes forms conduction region between bonded substrate method and apparatus.But will recognize that the present invention has wideer range of application; It also may be used on being used for other substrate of the three-dimension packaging of multilevel integration device and integrated-semiconductor device, photonic device, piezoelectric device, MEMS (micro electro mechanical system) (" MEMS "), transducer, actuator, solar cell, flat-panel monitor (for example, LCD, AMLCD), biology and biomedical articles etc.
The method that is used to make bonded substrate according to embodiments of the invention can be summarized as follows:
1. prepare first substrate, it has one deck with the material of removing;
2. the first surface district of first substrate is joined to the second surface district of second substrate;
3. between the second surface district of the first surface district of first substrate and second substrate, form the boundary zone;
4. remove second surface district bonding that layer of material keeps the first surface district of first substrate and second substrate simultaneously from first substrate;
5. inject particle to form the particle district near the boundary zone via the boundary zone so that this layer material is electrically coupled to second substrate;
6. handle the substrat structure of institute's bonding;
7. on layer of material, form integrated circuit device structure; And
8. as required, carry out other step.
The step of above order provides and has been used to make the method for substrate according to an embodiment of the invention.As implied above, this method has adopted the step combination that comprises the method for utilizing injection technique to form conductive layer between the bonded substrate district.Certainly, also can provide other selection, wherein can increase step, remove a step or a multistep step, perhaps under the situation that does not deviate from the described scope of the claims by the appended claims herein, one step or multistep step is set with different orders.Other details of this method can specification find in full and below more specifically.
Fig. 1 illustrates the signal Figure 100 that is used to form the method for MULTILAYER SUBSTRATE according to embodiments of the invention.This figure is an example only, and it should exceedingly not limit the scope of the appended claim of this paper.Those of ordinary skill in the art can recognize a lot of variants, modification and selection.In specific embodiment, the invention provides and for example be used to form on the substrat structure technology of MULTILAYER SUBSTRATE such as silicon-silicon, germanium-silicon, III/V family material.This technology comprises provides first substrate, and it has one deck with the material of removing 105.This layer material of removing is comprised the first surface district.In specific embodiment, this layer material can be silicon, germanium, III/V family material and other.Depend on embodiment, silicon substrate structure has { 100} face, { 110} face or { the oikocryst face of 111} face.
This technology comprises the second surface district that the first surface district of first substrate is joined to second substrate 101.Depend on embodiment, second substrate can be by forming such as multiple materials such as the material of first substrate and other materials.In specific embodiment, second substrate is to have { 100} face, { 110} face or the { silicon materials of the oikocryst face of 111} face.Preferably, joint utilizes bonding technology to realize, bonding technology can comprise that cleaning and/or plasma activation technology are to promote low-temperature bonding.Cleaning comprises plasma activation cleaning and/or other treatment technology.An example of this technology can be at United States Patent (USP) the 6th, 645, finds that this patent transfers SiliconGenesis company jointly in No. 828, and is therefore incorporated herein by reference.In a preferred embodiment, joint technology forms boundary zone 107 between the second surface district of the first surface district of first substrate and second substrate.In specific embodiment, according to specific embodiment, the boundary zone can comprise the insulating material such as oxide or silica.Depend on embodiment, also can use interface such as other types such as cementing layer, metal levels.According to specific embodiment, utilize oxide insulating layer and silicon substrate, can form the silicon structure on the insulating barrier.This technology comprises bonding to the second surface district of second substrate of first surface district that the layer of material with removing that is made of first substrate keeps first substrate simultaneously.In preferred embodiment, the method that is used to form the bonded substrate structure is to be called " layer shift " technology,, French SA described as people such as above Henley Soitec proposed is commonly referred to Smart-Cut
TM, these combination in any etc.Certainly, it will be appreciated by those skilled in the art that other variant, modification and selection.
In specific embodiment, this technology is passed the boundary zone and is injected particle 103 to form the particle district near the boundary zone.In preferred embodiment, injection can pass this layer material, pass the boundary zone and pass second substrate and partly realize.In specific embodiment, particle can be the conduction and/or present other characteristic to promote the electric coupling between this layer material and second substrate.Preferably, according to specific embodiment, particle can comprise the foreign particle that is selected from boron, arsenic, phosphorus and silicon.In concrete example, depend on embodiment, particle also can be silicon (for example, silicon ion), germanium (for example, germanium ion), other semiconductor and/or metal.In specific embodiment, particle can comprise about 10
18Particle/cm
3Concentration and according to using more or less.Can find some details of electric coupling according to the following drawings.
Fig. 2 is the resistance of suitable MULTILAYER SUBSTRATE according to an embodiment of the invention and the simplification curve 200 of the relation of injecting the degree of depth.This figure only is an example, and it should exceedingly not limit the scope of the appended claim of this paper.Person of skill in the art will appreciate that a lot of variants, modification and selection.As shown in the figure, vertical axis 201 expression resistivity 201, the injection degree of depth on its relative trunnion axis 205 is drawn.With reference to figure 1, according to specific embodiment, degree of depth surface region from the bonded substrate structure on the z-direction is measured to the center of bonded substrate, and this direction is vertical with surface region.As shown in the figure, according to specific embodiment, resistivity comprises for the peak 209 of preflood situation with for the decline peak 211 of the situation after injecting.According to specific embodiment, pass the decline peak or the continuous substantially conductivity of boundary zone, promote the layer of material of first substrate and electric coupling and/or the conductivity between a part of second substrate.Can find in full and hereinafter more specifically at specification in other embodiments of the invention.
In specific embodiment, this technology is carried out the processing of bonded substrate structure.According to specific embodiment, processing can comprise that thermal annealing is to remove in any defective of injecting the boundary zone.Heat treatment can provide by stove, rapid thermal annealing or their combination in any.According to preferred embodiment, this technology can form integrated circuit component and device on layer of material.Certainly, those of ordinary skill in the art can recognize a lot of variants, modification and selection.
In another specific embodiment, the invention provides and be used to form for example technology of the MULTILAYER SUBSTRATE of silicon-silicon, be summarized as follows:
1. first substrate is provided, and it has one deck with the material of removing;
2. the first surface district of first substrate is joined to the second surface district of second substrate;
3. between the second surface district of the first surface district of first substrate and second substrate, form the boundary zone;
4. remove bonding to the second surface district of second substrate of first surface district that this layer material keeps first substrate simultaneously from first substrate;
5. the boundary zone of passing between the second surface district of the first surface district of first substrate and second substrate in the mode of cavity forms a plurality of openings;
6. one or more with in the electric conducting material filling opening so that this layer material is electrically coupled to second substrate; And
7. randomly, inject particle so that the electric coupling between this layer material and second substrate to the boundary zone;
8. handle the bonded substrate structure.
9. on this layer material, form integrated circuit (IC)-components; And,
10. as required, carry out other step.
The step of above order provides the method that is used to make substrate according to embodiments of the invention.As shown in the figure, this method adopts the step combination that comprises the method for utilizing conductive plug district and optional injection technique to form conductive layer between the bonded substrate district.Certainly, also can provide other selection, wherein can increase step, remove a step or a multistep step, perhaps under the situation that does not deviate from the scope of the claims by the appended claims herein, one step or multistep step is set with different orders.Other details of this method can be found in full and hereinafter more specifically at specification.
Fig. 3 is the schematic diagram of sandwich construction 300 in accordance with another embodiment of the present invention.This figure only is an example, and it should exceedingly not limit the scope of the appended claim of this paper.Those of ordinary skill in the art can recognize a lot of variants, modification and selection.In another specific embodiment, the invention provides the technology that is used to form on the substrat structure such as MULTILAYER SUBSTRATE such as silicon-silicon, germanium-silicon, III/V family materials.This technology comprises provides first substrate, and it has one deck with the material of removing.This floor comprises the first surface district with the material of removing.In specific embodiment, this layer material can be silicon, germanium, III/V family material and other.Depend on embodiment, silicon substrate structure has { 100} face, { 110} face or { the oikocryst face of 111} face.
According to specific embodiment, this technology comprises that the first surface district with first substrate joins the second surface district of second substrate to.Depend on embodiment, second substrate can be by forming such as various materials such as the material of first substrate and other materials.In specific embodiment, second substrate is to have { 100} face, { 110} face or the { silicon materials of the oikocryst face of 111} face.Preferably, engage and utilize bonding technology to form, bonding technology can comprise that cleaning and/or plasma activation technology are to promote at low-temperature bonding.Cleaning comprises plasma activation cleaning and/or other treatment technology.An example of this technology can be at United States Patent (USP) the 6th, 645, finds that this patent transfers Silicon Genesis company jointly in No. 828, and is therefore incorporated herein by reference.In a preferred embodiment, joint technology forms the boundary zone between the second surface district of the first surface district of first substrate and second substrate.This technology comprises from first substrate removes bonding to the second surface district of second substrate, second substrate of first surface district that layer of material keeps first substrate simultaneously.In preferred embodiment, the method that is used to form the bonded substrate structure is to be called " layer shifts " technology, and Soitec described as people such as above Henley, French SA is commonly referred to Smart-Cut
TMDeng.Certainly, it will be appreciated by those skilled in the art that other variant, modification and selection.
In preferred embodiment, the boundary zone that this technology is passed in the mode of cavity between the second surface district of the first surface district of first substrate and second substrate forms a plurality of openings 307.This technology is one or more so that this layer material is electrically coupled to second substrate with in electric conducting material 305 filling openings also.Electric conducting material can comprise metal, doped semiconductor materials, these combination in any and other, comprise multilayer material etc.Conductive structure can be similar to the through-hole structure that is used as interconnection etc. in the traditional devices.As shown in the figure, electric conducting material is with this layer material and second substrate interconnection.Equally as shown in the figure, electric conducting material can form in well structure.Electric conducting material is filled whole opening with the electric and physical connection with two substrat structures.Certainly, it will be appreciated by those skilled in the art that a lot of variants, modification and selection.
In specific embodiment, this technology is carried out the processing of bonded substrate structure.According to specific embodiment, processing can comprise that thermal annealing is to remove any defective of injecting the boundary zone.Heat treatment can provide by stove, rapid thermal annealing or their combination in any.According to preferred embodiment, this technology has formed integrated circuit component and device on this layer material.Certainly, those of ordinary skill in the art can recognize a lot of variants, modification and selection.
In another specific embodiment, the invention provides and be used to form for example technology of the MULTILAYER SUBSTRATE of silicon-silicon, be summarized as follows:
1. first substrate is provided, and it has one deck with the material of removing;
2. the first surface district of first substrate is joined to the second surface district of second substrate;
3. between the second surface district of the first surface district of first substrate and second substrate, form the boundary zone;
4. remove bonding to the second surface district of second substrate of first surface district that this layer material keeps first substrate simultaneously from first substrate;
5. the boundary zone of passing between the second surface district of the first surface district of first substrate and second substrate in the mode of cavity forms a plurality of openings;
6. one or more with in the electric conducting material filling opening so that this layer material is electrically coupled to second substrate;
7. randomly, inject particle with the electric coupling between this layer material of same promotion and second substrate to the boundary zone;
8. utilize a part of boundary zone to remove this layer material of a part as the barrier layer;
9. selectively remove near interior a part of barrier layer, a part of boundary zone to expose a following part second substrate; And
10. on a part second substrate that exposes, form epitaxial loayer;
11. on this layer material and epitaxial loayer, form integrated circuit (IC)-components; And
12. as required, carry out other step.
The step of above order provides the method that is used to make substrate according to the embodiment of the invention.As shown in the figure, this method adopts and comprises that optional injection technique utilizes the conductive plug district forming conductive layer between the bonded substrate district and forming the step combination of the method that covers the epitaxial loayer on a part of second substrate.Certainly, also can provide other selection, wherein can increase some steps, remove a step or a multistep step, perhaps under the situation that does not deviate from the scope of the claims by the appended claims herein, one step or multistep step is set with different orders.Other details of this method can be found in full and hereinafter more specifically at specification.
Fig. 4 to 6 is sketches 400, and they show the method that is used to form multi-layer substrate structure according to another embodiment of the invention.This figure only is an example, and it should exceedingly not limit the scope of claim herein.Those of ordinary skill in the art can recognize a lot of variants, modification and selection.In another specific embodiment, the invention provides be used to form on the substrat structure such as the SiGe on silicon-silicon, germanium-silicon, III/V family material, silicon or other material, on the insulator carborundum, GaN sandwich construction, these combination and other etc. the another kind of technology of MULTILAYER SUBSTRATE.This technology comprises provides first substrate, and it has one deck with the material of removing.This floor comprises the first surface district with the material of removing.In specific embodiment, this layer material can be silicon, germanium, III/V family material and other.Depend on embodiment, silicon substrate structure has { 100} face, { 110} face or { the oikocryst face of 111} face.
According to specific embodiment, this technology comprises that the first surface district with first substrate joins the second surface district of second substrate to.Depend on embodiment, second substrate can be by forming such as the material of first substrate and the various materials other material.In specific embodiment, second substrate is to have { 100} face, { 110} face or the { silicon materials of the oikocryst face of 111} face.Preferably, engage and utilize bonding technology to form, bonding technology can comprise that cleaning and/or plasma activation technology are to promote at low-temperature bonding.Cleaning comprises plasma activation cleaning and/or other treatment technology.An example of this technology can be at United States Patent (USP) the 6th, 645, finds that this patent transfers Silicon Genesis company jointly in No. 828, and is therefore incorporated herein by reference.In preferred embodiment, joint technology forms the boundary zone between the second surface district of the first surface district of first substrate and second substrate.This technology comprises from first substrate removes bonding to the second surface district of second substrate, second substrate of first surface district that layer of material keeps first substrate simultaneously.In preferred embodiment, the method that is used to form the bonded substrate structure is to be called " layer shifts " technology, is commonly referred to Smart-Cut as described, the French Soitec SA of people such as above Henley
TMDeng.Certainly, it will be appreciated by those skilled in the art that other variant, modification and selection.
In preferred embodiment, the boundary zone that this technology is passed in the mode of cavity between the second surface district of the first surface district of first substrate and second substrate forms a plurality of openings 307.This technology is one or more so that this layer material is electrically coupled to second substrate with in electric conducting material 305 filling openings also.Electric conducting material can comprise metal, doped semiconductor materials, these combination in any and other, comprise multilayer material etc.Conductive structure can be similar to the through-hole structure that is used as interconnection etc. in traditional devices.As shown in the figure, electric conducting material is with this layer material and second substrate interconnection.Equally as shown in the figure, electric conducting material can form in well structure.Electric conducting material is filled whole opening with the electric and physical connection with two substrat structures.Certainly, it will be appreciated by those skilled in the art that a lot of variants, modification and selection.
With reference to figure 4, according to specific embodiment, this method forms the mask arrangement 401 that covers this layer material in the bonded substrate structure.As shown, this layer material comprises exposed region 403.Exposed region can be the silicon supporting material, and it can utilize the ground etching of etching type selecting.According to specific embodiment, exposed region is this layer material of a part.According to specific embodiment, normally the boundary zone 405 of insulating material (for example, oxide) can be used as and stops layer.As shown in the figure, according to specific embodiment, trench area forms in this layer material by removing this layer material of a part.
As shown in Figure 5, this method is optionally removed insulating barrier.The optionally removal of insulating barrier has exposed silicon supporting material 501, and it is substantially without any defective.In preferred embodiment, optionally remove to utilize comprise wet etching type etc. optionally etchant form.Only, depend on application, can use such as the chemical substance based on fluorine such as hydrofluoric acid (HF), buffered hydrofluoric acid (BHF), buffer oxide etch (BOE) and other as an example.Because the expose portion of optionally removing technology second substrate, is optionally removed normally wet etching or such as dry etching optionally such as plasma of technology substantially without any damage.With reference to figure 6, this method forms the epitaxial loayer 601 that covers with second substrate zone that exposes.{ 110} compares epitaxial loayer can have such as { the different crystalline lattice orientation of the silicon the 100} with layer of material.Epitaxial loayer can utilize such as forming at doping processs such as original place doping.In specific embodiment, epitaxial loayer is a monocrystal silicon structure.As shown in the figure, nmos device can form on the epitaxial loayer of silicon, germanium or other type, and the PMOS device can form on layer of material.Certainly, it will be appreciated by those skilled in the art that a lot of variants, selection and modification.Other details of method and resulting structures has according to an embodiment of the invention below been described.
Fig. 7 and 8 illustrates the sketch that is used to form the another kind of method of multi-layer substrate structure according to the embodiment of the invention.These figure only are example and the scope that should exceedingly not limit the appended claim of this paper.It will be appreciated by those skilled in the art that a lot of variants, selection and modification.As another kind of method (the above describing) conduct that forms epitaxial loayer comprises that the technology of injecting particle 711 illustrates to form injection region 707.In specific embodiment, the opening that passes mask layer 705 provides particle.In specific embodiment, particle can comprise silicon, germanium, arsenic any other kind described herein and other.
In specific embodiment, according to specific embodiment, mask layer 705 can be lithography layer and/or hard mask.According to specific embodiment, an example of hard mask is silicon nitride layer and/or oxide layer.It should be noted that and depend on specific embodiment that mask layer also comprises the lithography layer of individual layer and sandwich construction.Mask layer cover according to specific embodiment separately or the layer of material 703 that shifts of layer form.Layer of material covers backing material 701, and this had before described.In specific embodiment, this layer material can comprise monocrystalline silicon and other material.Certainly, other variant, modification and selection can be arranged.
In specific embodiment, injection region 707 comprise a part of layer of material and this layer material and below backing material between interface 708 near in the zone.In specific embodiment, the injection region becomes amorphous areas and/or presents other characteristic.That is, according to specific embodiment, the injection region can have the amorphous state characteristic, and it also can comprise other characteristic, but mainly is amorphous state.As shown in Figure 7, the injection region has defined new orientation.
With reference to figure 8, according to specific embodiment, this method comprises Technology for Heating Processing 803.Technology for Heating Processing can be by providing such as suitable technology such as furnaceman's skill, rapid thermal annealing and/or other technologies.Certainly, can there be other variant to revise and selection.
In a specific embodiment, Technology for Heating Processing is used in injection region crystallization and/or regrowth crystal.As shown in the figure, according to specific embodiment, crystalline material can be and have { the second substrate same type of 100} crystal lattice orientation.According to specific embodiment, can in about 1250 ℃ temperature range, take place from about 600 ℃ for the silicon materials thermal annealing.
Annealing can be carried out list annealing or a plurality of cyclic annealing under identical or different condition.For example, an annealing cycle can be used for crystallization again, and another annealing cycle is used to remove defective.According to one embodiment of present invention, the recrystallization annealing cycle can carry out under 650-800 ℃, and the annealing cycle of removal defective can carry out under 1000-1250 ℃.
According to specific embodiment, annealing can continue under vacuum and/or atmospheric pressure.Annealing also can and contain in the environment of the etching gas such as H and HCl at vacuum environment, inert environments (for example, comprising argon and/or nitrogen), ambient containing hydrogen, forming gas (for example, hydrogeneous/argon or other similar mixture) and continues.Annealing can begin before or after removing lithography layer or hard mask.Annealing also can be carried out in oxidation environment with at the exposed surface grow oxide.Annealing can be in conjunction with United States Patent (USP) the 6th, 103, and the technology of describing in No. 599 is carried out, and its content is incorporated herein by reference.Annealing heat treatment can finish when the surface covers with the oxide of deposition or other passivation layer.Other variant, modification and selection can be arranged certainly.
In specific embodiment, this technology is carried out the processing of bonded substrate structure.Processing can comprise that thermal annealing is to remove any defective of injecting the boundary zone according to specific embodiment.Heat treatment can provide by stove, rapid thermal annealing or their combination in any.Integrated circuit component and device on layer of material, have been formed according to this technology of preferred embodiment.Certainly, those of ordinary skill in the art can recognize a lot of variants, modification and selection.
The step of above order provides the method that is used to make substrate according to the embodiment of the invention.As shown in the figure, this method adopts and comprises that optional injection technique utilizes the conductive plug district to cover the combination of the step of the epitaxial loayer method on a part of second substrate what form conductive layer between the bonded substrate district with formation.Certainly, also can provide other selection, wherein increase some steps, remove a step or a multistep step, perhaps under the situation of the scope that does not deviate from this paper appended claims, one step or multistep step is set with different orders.
Though above illustrate, other variant, modification and selection can be arranged according to specific embodiment.For example, according to specific embodiment, this layer material can be a strain gauge material.That is, according to specific embodiment, strain gauge material can be twin shaft or single shaft.In addition, according to specific embodiment, strain gauge material can be graphical and/or complete.Depend on embodiment, strain gauge material can utilize the patterned strained technology of SiGe in the etching region in source/drain region of MOS device to form.In conjunction with or as selecting, strain gauge material can be by applying for PCT/US05/12410 number with " Method and System for Lattice Space Engineering " (the application attorney docket 018419-016410PC) of people's such as Francois J.Henley name and the PCT that submits on April 12nd, 2005 and applying for that with " A Method for Frabricating Semiconductor DeviceUsing Strained Silicon Bearing Materials " (the application attorney docket 018419-012110PC) of the name of Francois J.Henley and the PCT that submits on November 18th, 2004 strain gauge technique of describing in PCT/US04/38616 number forms, these two pieces of applications are transferred the possession of separately jointly, and incorporated herein by reference.Other variant, modification and selection can be arranged certainly.
Also should understand example described herein and embodiment and only be used for illustrative purposes, and those skilled in the art will associate according to it various modifications or variation and comprise the application's spirit and scope and the scope of claims in.
Claims (33)
1. technology that is used to form MULTILAYER SUBSTRATE, described technology comprises:
First substrate is set, and described first substrate comprises the layer of material that will remove, and described layer of material with removal comprises the first surface district;
Join the first surface district of described first substrate second surface district of second substrate to, with the boundary zone between the second surface district of the first surface district that is formed on described first substrate and described second substrate;
Remove described layer of material from described first substrate, keep second surface district bonding of the first surface district of described first substrate and described second substrate simultaneously;
The mask layer that forms the surface region that covers described layer of material is to form the exposed region of a part of described layer of material;
Particle injected described exposed region and pass the part boundary zone and near described part boundary zone, form the conducting particles district, thereby the described part of described layer of material is coupled to described second substrate to form the injection region that comprises described exposed region and described part boundary zone at least; And
At least technology is heat-treated so that the injection region crystallization in described injection region.
2. technology as claimed in claim 1 is characterized in that described particle has conductive characteristic near described boundary zone.
3. technology as claimed in claim 1 is characterized in that described particle comprises the doping particle.
4. technology as claimed in claim 3 is characterized in that, described doping particle is selected from boron, arsenic or phosphorus.
5. technology as claimed in claim 1 is characterized in that, described first substrate is a silicon wafer.
6. technology as claimed in claim 5 is characterized in that, described silicon wafer is that { the 100} face characterizes by the oikocryst face.
7. technology as claimed in claim 5 is characterized in that, described silicon wafer is that { the 110} face characterizes by the oikocryst face.
8. technology as claimed in claim 5 is characterized in that, described silicon wafer is that { the 111} face characterizes by the oikocryst face.
9. technology as claimed in claim 1 is characterized in that, described particle district has about 10
18Atom/cm
3Or higher concentration.
10. technology as claimed in claim 1 is characterized in that, described joint comprises the bonding mutually with described first surface district and described second surface district.
11. technology as claimed in claim 1 is characterized in that, described joint comprises the plasma activation processing in described at least first surface district and described second surface district.
12. technology as claimed in claim 1 is characterized in that, described joint comprises and utilizes oxide material with described first surface district and described second surface district bonding mutually.
13. technology as claimed in claim 1 is characterized in that, described boundary zone is characterized by insulating material.
14. technology as claimed in claim 1 is characterized in that, described particle district changes into conductive characteristic with described boundary zone from insulation characterisitic.
15. technology as claimed in claim 1 is characterized in that, described injection utilizes the high energy implanter to provide.
16. technology as claimed in claim 1 is characterized in that, described boundary zone comprises earth silicon material.
17. technology as claimed in claim 1 is characterized in that, described being infused in described layer of material and described second substrate of a part forms well region.
18. technology as claimed in claim 1 is characterized in that, comprises that also passing the boundary zone forms a plurality of through-hole structures described layer of material is electrically connected to described second substrate of a part.
19. technology as claimed in claim 1 is characterized in that, comprises that also passing described layer of material injects second particle to form well region at described layer of material.
20. technology as claimed in claim 1 is characterized in that, described layer of material has 8000 dusts or less than the thickness of 8000 dusts.
21. technology as claimed in claim 1 is characterized in that, described first substrate comprises silicon wafer, and described silicon wafer is characterized by first crystal lattice orientation, wherein makes the injection region crystallization form crystalline portion, and described crystalline portion is characterized by second crystal lattice orientation.
22. technology as claimed in claim 21 is characterized in that, the oikocryst face of described first crystal lattice orientation is { 110} a face, and the oikocryst face of described second crystal lattice orientation is { 100} a face.
23. technology as claimed in claim 1 is characterized in that, described a part of layer of material and a part of described first surface district and a part of described second surface district are passed in the injection of described particle.
24. technology as claimed in claim 1 is characterized in that, described particle has conduction property so that the electrical connection between described layer of material and described second substrate of a part to be provided.
25. technology as claimed in claim 1 is characterized in that, described particle comprises a plurality of silicon ions or a plurality of germanium ion.
26. technology as claimed in claim 1 is characterized in that, wherein makes the injection region crystallization form crystalline portion, described crystalline portion has the characteristic of the crystal lattice orientation of predefined type, and described predefined type is the crystal lattice orientation of described second substrate.
27. the MULTILAYER SUBSTRATE that part is finished, it comprises:
By the layer of material that first substrate constitutes, described layer of material comprises the first surface district;
Second substrate with second surface district, the first surface district of described layer of material engages with the second surface district of described second substrate;
The boundary zone that between the second surface district of the first surface district of described layer of material and described second substrate, forms; And
The a plurality of particles that inject in the described layer of material of a part and a part of described boundary zone are so that a part of described layer of material is electrically coupled to described second substrate of a part.
28. MULTILAYER SUBSTRATE as claimed in claim 27 is characterized in that, described first substrate comprises silicon materials.
29. MULTILAYER SUBSTRATE as claimed in claim 27 is characterized in that, described second substrate comprises silicon materials.
30. MULTILAYER SUBSTRATE as claimed in claim 27 is characterized in that, described a plurality of particles comprise electric conducting material.
31. MULTILAYER SUBSTRATE as claimed in claim 27 is characterized in that, described a plurality of particles are at least 10
18Particle/cm
3
32. MULTILAYER SUBSTRATE as claimed in claim 27 is characterized in that, the particle in described a part of layer of material causes the amorphous state characteristic in described a part of layer of material.
33. MULTILAYER SUBSTRATE as claimed in claim 32 is characterized in that, described a part of layer of material is converted to crystallization property from the amorphous state characteristic.
Applications Claiming Priority (2)
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|---|---|---|---|
| US11/292,395 | 2005-11-30 | ||
| US11/292,395 US7399680B2 (en) | 2004-11-24 | 2005-11-30 | Method and structure for implanting bonded substrates for electrical conductivity |
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| CN1992173A CN1992173A (en) | 2007-07-04 |
| CN1992173B true CN1992173B (en) | 2010-04-21 |
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| KR (1) | KR100853580B1 (en) |
| CN (1) | CN1992173B (en) |
| TW (1) | TWI447785B (en) |
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| FR2934925B1 (en) * | 2008-08-06 | 2011-02-25 | Soitec Silicon On Insulator | METHOD FOR MANUFACTURING A STRUCTURE COMPRISING A STEP OF ION IMPLANTATIONS TO STABILIZE THE BONDING INTERFACE. |
| KR101319252B1 (en) * | 2012-03-06 | 2013-10-23 | (주) 이피웍스 | Method for forming a through silicon via |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5141887A (en) * | 1990-07-02 | 1992-08-25 | Motorola, Inc. | Low voltage, deep junction device and method |
| CN1347146A (en) * | 2000-09-28 | 2002-05-01 | 日本电气株式会社 | Semiconductor device with silicon structure on insulator, and method for mfg. same |
| US6506664B1 (en) * | 1999-04-02 | 2003-01-14 | Imec Vzw | Method of transferring ultra-thin substrates and application of the method to the manufacture of a multi-layer thin film device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5841197A (en) | 1994-11-18 | 1998-11-24 | Adamic, Jr.; Fred W. | Inverted dielectric isolation process |
| US7052941B2 (en) * | 2003-06-24 | 2006-05-30 | Sang-Yun Lee | Method for making a three-dimensional integrated circuit structure |
| US6013563A (en) * | 1997-05-12 | 2000-01-11 | Silicon Genesis Corporation | Controlled cleaning process |
| AU9296098A (en) * | 1997-08-29 | 1999-03-16 | Sharon N. Farrens | In situ plasma wafer bonding method |
| WO2002015244A2 (en) * | 2000-08-16 | 2002-02-21 | Massachusetts Institute Of Technology | Process for producing semiconductor article using graded expitaxial growth |
| FR2845523B1 (en) * | 2002-10-07 | 2005-10-28 | METHOD FOR MAKING A SUBSTRATE BY TRANSFERRING A DONOR WAFER HAVING FOREIGN SPECIES, AND ASSOCIATED DONOR WAFER |
-
2006
- 2006-11-29 CN CN2006101629001A patent/CN1992173B/en active Active
- 2006-11-30 TW TW095144436A patent/TWI447785B/en active
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5141887A (en) * | 1990-07-02 | 1992-08-25 | Motorola, Inc. | Low voltage, deep junction device and method |
| US6506664B1 (en) * | 1999-04-02 | 2003-01-14 | Imec Vzw | Method of transferring ultra-thin substrates and application of the method to the manufacture of a multi-layer thin film device |
| CN1347146A (en) * | 2000-09-28 | 2002-05-01 | 日本电气株式会社 | Semiconductor device with silicon structure on insulator, and method for mfg. same |
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| Publication number | Publication date |
|---|---|
| KR100853580B1 (en) | 2008-08-21 |
| TWI447785B (en) | 2014-08-01 |
| CN1992173A (en) | 2007-07-04 |
| TW200802556A (en) | 2008-01-01 |
| KR20070057044A (en) | 2007-06-04 |
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