JPH11163363A - Semiconductor device and its forming method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a semiconductor device of low manufacturing cost by the use of a glass substrate the distortion spot of which is at least a specified temperature, protecting on outer peripheral surface of the high heat resistant glass substrate by using an insulating silicon film, and forming a single-crystal silicon thin film on the high heat resistant glass substrate wrapped with the insulating silicon film. SOLUTION: A glass substrate (glass substrate the distortion spot of which is at least 750 deg.C or higher), having heat resistance capable of enduring a temperature of at least 750 deg.C, is used as a substrate. An amorphous silicon film 102 is formed to crystallized glass 101. When the film 2 is formed through a low- pressure heat CVD method, the amorphous silicon film 102 can be formed on the surface, the back and the side surface of the substrate 101, which is wrapped with the film 102. By thermally oxidizing the amorphous silicon film 102, a thermal oxide film 103 is formed. A single-crystal silicon thin film 107 is formed on the crystallized glass 101 whose outer peripheral part is protected by the thermal oxide film 103.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD [0001] The invention disclosed in the present specification is:
The present invention relates to a semiconductor device using a single crystal semiconductor thin film formed over a substrate having an insulating surface. In particular, inexpensive and highly heat-resistant crystallized glass (also called ceramic glass) is used as the substrate.

[0002] In this specification, a thin film transistor (hereinafter, referred to as a TFT), a semiconductor circuit, an electro-optical device, and an electronic device are all included in the category of a “semiconductor device”. That is, all devices that can function by utilizing semiconductor characteristics are called semiconductor devices.

Accordingly, the semiconductor device described in the claims includes not only a single element such as a TFT but also a semiconductor circuit or an electro-optical device in which the device is integrated, and an electronic device in which these are mounted as components. I do.

[0004]

2. Description of the Related Art In recent years, a technique of forming a thin film transistor (TFT) using a semiconductor thin film (thickness of about several tens to several hundreds of nm) formed on a substrate having an insulating surface has attracted attention. In particular, the development of a thin film transistor as a switching element of an image display device (for example, a liquid crystal display device: LCD) has been rushed.

In the liquid crystal display device, a pixel matrix circuit for individually controlling pixels arranged in a matrix, a driver circuit for controlling the pixel matrix circuit, and a logic circuit (an arithmetic circuit, Attempts have been made to form memory circuits, clock generators, and the like) on the same substrate.

In order to realize such a monolithic LCD, a TFT circuit having a higher operation speed is required, and a semiconductor layer having extremely high carrier mobility is required.

[0007] In such a flow, SOI technology is receiving attention. In particular, a technique called a smart cut method has attracted attention as a technique for forming a single crystal silicon thin film on a substrate such as synthetic quartz.

[0008] Smart cut method (1996, SO in France
(Published by ITEC) is one of the bonding SOI technologies, which actively uses hydrogen embrittlement. Here, a simple procedure of the smart cut method will be described with reference to FIG.

First, a thermal oxide film 202 is formed by thermally oxidizing the bond wafer 201, and thereafter, hydrogen ions (H ⁺ ) are added by an ion implantation method.
A microcavity 20 terminated with hydrogen is formed in the bond wafer 201 by the process of adding hydrogen ions.
3 is formed. In this specification, this minute cavity 203
Is referred to as a hydrogen implanted layer. (Fig. 2 (A))

Next, the bond wafer 20 having been subjected to the above processing is
1 and a base wafer 204, which will later become a thin film support substrate, are bonded at room temperature and subjected to a heat treatment at about 500 ° C. By this heat treatment, hydrogen embrittlement occurs in the above-described hydrogen implanted layer, and a fracture layer 205 due to hydrogen embrittlement is formed.
(FIG. 2 (B))

When the fracture layer 205 is formed by hydrogen embrittlement, the bond wafer 201 is easily peeled off, leaving only the single crystal silicon thin film 206. (Fig. 2 (C))

Accordingly, a thermal oxide film 202 and a single crystal silicon thin film 206 serving as bases are formed on the base wafer 204. Note that the thickness of the single-crystal silicon thin film 206 at this time is determined by the thickness of the thermal oxide film 202 and the implantation depth of hydrogen ion implantation in FIG.

When the state shown in FIG. 2C is obtained,
Perform shallow polishing (touch polish) on the order of 10 nm,
Further, a heat treatment is performed at a temperature of about 1000 to 1100 ° C. for about 2 hours to obtain a single crystal silicon thin film 207 having a strong bonding force. (FIG. 2 (D))

As described above, the smart cut method has an advantage that a single crystal silicon thin film can be obtained by a very simple means. Further, since the thickness of the single crystal silicon layer is not affected by the polishing accuracy as compared with the past bonded SOI substrate, the uniformity of the thickness is extremely high.

Recently, attempts have been made to form a single-crystal silicon thin film on synthetic quartz using the smart cut method. (Takao Abe: 24th Seminar on Physical Properties and Application of Amorphous Materials, p.25-32,1997)

However, according to this report, when synthetic quartz and a silicon wafer (bond wafer) are bonded to each other, destruction occurs when heated at about 300 ° C. due to a large difference in thermal expansion coefficient. Therefore, according to the report, after bonding the bond wafers at about 200 ° C., the wafers are polished (or etched) to 50 μm, and then subjected to a heat treatment at 500 ° C. to complete the bonding.

[0017]

As described above, forming a single-crystal silicon layer on a synthetic quartz by using the smart cut method has a problem of a difference in thermal expansion coefficient, and the bonding step is complicated. Disadvantage.

Further, a TFT using a single crystal silicon layer is used.
In view of the object of forming a monolithic type LCD by using a quartz substrate, it is not preferable to use an expensive quartz substrate because the total cost is increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides a technique for realizing a semiconductor device using a single crystal silicon thin film obtained by a smart cut method at a low manufacturing cost. Make it an issue.

[0020]

Means for Solving the Problems The invention disclosed in the present specification comprises a glass substrate having a strain point of 750 ° C. or more, and an insulating silicon film formed on at least the front and back surfaces of the glass substrate. And a TFT having a single crystal silicon thin film formed on the insulating silicon film as a channel formation region.

In another embodiment of the invention, the strain point is 750 ° C.
A glass substrate as described above, an insulating silicon film formed so as to cover the outer periphery of the glass substrate, and a TFT having a single crystal silicon thin film formed on the insulating silicon film as a channel formation region. Is included.

In another embodiment of the invention, the strain point is 750 ° C.
A step of forming an amorphous semiconductor thin film over the entire surface of the glass substrate, a step of oxidizing the amorphous semiconductor thin film by a first heat treatment, and completely transforming the amorphous semiconductor thin film into a thermal oxide film, Forming a single-crystal silicon thin film on the main surface side of the glass substrate by a method.

In another embodiment of the invention, the strain point is 750 ° C.
A step of forming an insulating silicon film on the entire surface of the glass substrate by a low-pressure thermal CVD method, and a step of forming a single-crystal silicon thin film on the main surface side of the glass substrate by a smart cut method It is characterized by.

Important constituent elements of the present invention are as follows: (1) A glass substrate having a heat resistance capable of withstanding a temperature of 750 ° C. or more (a glass substrate having a strain point of 750 ° C. or more) is used. (2) The outer peripheral surface (at least the front and back surfaces, preferably the entire surface) of the high heat-resistant glass substrate is protected by an insulating silicon film. (3) A single-crystal silicon thin film is formed on the high heat-resistant glass substrate wrapped with the insulating silicon film by using a smart cut method. There are three points.

The single-crystal silicon thin film bonded on the substrate by the smart cut method is 800 to 1200 ° C. (preferably,
A complete bonding force can be obtained by performing a heat treatment at 900 to 1100 ° C. Therefore, it is necessary to use a substrate with a strain point of at least 750 ° C as a base substrate.

As such a substrate, a quartz substrate is first conceivable, but as described above, the quartz substrate is expensive, so that the overall cost is increased. The thermal expansion coefficient of quartz is 0.
48 × 10 ^-6 ℃ ^-1 and the coefficient of thermal expansion of silicon (about 4.15 ×
It is as small as about 1/10 of 10 ^-6 ℃ ^-1 ). That is, a stress is easily generated between the silicon and the silicon, and the silicon tends to peel (film peeling) during the heat treatment.

Therefore, in the present invention, the strain point is 750 ° C. or more (typically 800 to 1200 ° C., preferably 900 to 1100 ° C.).
Is used as the substrate.
Since crystallized glass can be made thinner than quartz, the manufacturing cost of LCD can be reduced. In addition, since it is a glass substrate, it is possible to increase the size of the plate, and it is possible to reduce the cost by obtaining multiple substrates.

Further, the coefficient of thermal expansion can be easily changed by appropriately setting the component composition of the crystallized glass, so that a coefficient close to the coefficient of thermal expansion of the single crystal silicon thin film can be selected. . That is, since the difference between the coefficients of thermal expansion can be made extremely small, film peeling and the like as in the prior art can be eliminated, and there is no need to perform complicated steps as described in the conventional example.

However, since crystallized glass has various component compositions, there is a concern that component materials may flow out during the manufacturing process of a semiconductor device. Therefore, it is important to protect the crystallized glass with an insulating film (an insulating silicon film is preferable in consideration of compatibility with a single crystal silicon thin film). For that purpose, it is necessary to protect at least the front surface (the side on which the element is formed) and the back surface of the crystallized glass in all process steps with an insulating film.

Incidentally, since the side surface of the crystallized glass has a very small area when viewed as a whole, it does not matter much even if it is exposed. However, it is needless to say that it is most preferable to completely cover the front surface, the side surface, and the back surface with the insulating film and completely prevent the outflow of the component material.

However, there is a portion where the film is not formed in the portion of the substrate supporting portion (such as a pusher pin) when the insulating film is formed. However, this is not a problem because the area is very small compared to the entire area.

In view of the above, the inventors of the present invention have made a single-crystal silicon formed by a smart cut method on a high heat-resistant glass substrate whose outer peripheral surface (preferably the entire surface) is protected by an insulating silicon film. This has led to the configuration of the present invention in which a thin film is provided.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail with reference to the following examples.

[0034]

[Embodiment 1] In this embodiment, steps up to forming a single-crystal silicon thin film on crystallized glass using a smart cut method will be described with reference to FIG.

First, a crystallized glass substrate 101 having a thickness of 0.5 to 1.1 mm (typically 0.7 mm) is prepared as a substrate.
Crystallized glass is also called glass ceramics, and is defined as a glass substrate obtained by uniformly growing fine crystals at the stage of glass formation. Such crystallized glass is characterized by high heat resistance and a small coefficient of thermal expansion.

The glass substrate used in the present invention is required to have high heat resistance having a strain point temperature of 750 ° C. or higher, preferably 900 to 1100. At present, the only glass material that achieves such heat resistance is crystallized glass. However, even if the glass substrate does not fall within the definition of crystallized glass (for example, a highly heat-resistant glass substrate in an amorphous state, etc.) Any substrate having properties can be used in the present invention.

The details of crystallized glass may be referred to "Glass Handbook: Saio Sakuhana et al., Pp. 197-217, Asakura Shoten, 1975".

There are various types of crystallized glass.
Quartz (SiO_Two), Alumina (Al _TwoO_Three )
Aluminosilicate glass, borosilicate glass (B_TwoO_ThreeBut
Included) is practical. However, semiconductive
Considering use as a substrate for body devices,
It is desirable to be re-glass, and in that sense, Mg
O-Al_TwoO_Three-SiO_TwoSystem, PbO-ZnO-B_TwoO_ThreeSystem, Al_TwoO_Three-B_TwoO_Three-SiO_Two 
System, ZnO-B_TwoO_Three-SiO_Two Systems and the like are preferred.

The MgO—Al ₂ O ₃ —SiO ₂ -based highly insulated crystallized glass contains nucleating agents such as TiO ₂ , SnO ₂ , ZrO _2, etc., and contains cordierite (2MgO.2Al ₂ O ₃ .5SiO ₂ ) Is a crystallized glass having a main crystal phase. This type of crystallized glass is characterized by high heat resistance and excellent electrical insulation even in a high frequency range. Table 1 shows composition examples and thermal expansion coefficients of cordierite-based crystallized glass.

[0040]

[Table 1]

Since the influence of shrinkage (shrinkage due to heat) due to heat decreases as the coefficient of thermal expansion decreases, it is preferable as a semiconductor substrate on which a fine pattern is processed. However, if the difference from the coefficient of thermal expansion of the semiconductor thin film is large, film peeling or the like is likely to occur. Considering such things, SiO ₂ is 45-57%, Al ₂ O ₃ is 20-27
%, It can be said that MgO is 11 to 18%, TiO ₂ is the 9-12% of cordierite based crystallized glass preferably.

For example, when a transmission type LCD is manufactured, the crystallized glass is required to have a light transmitting property. In such a case, an alkali-free transparent crystallized glass is preferably used.
For example, the crystal phase is a filled β-quartz solid solution and the thermal expansion coefficient is
As the crystallized glass at 1.1 to 3.0 × 10 ⁻⁶ ° C., there is a crystallized glass as shown in Table 2.

[0043]

[Table 2]

The first of the constituent requirements of the present invention is to use the above crystallized glass as a substrate. Of course, appropriate measures (such as complete protection with an insulating film as in the present invention)
Is applied to alkali-crystallized glass (Na ₂ O-Al ₂ O ₃ -SiO ₂
System, Li ₂ O—Al ₂ O ₃ —SiO ₂ system) can also be used. In addition, even for crystallized glass having a very low thermal expansion coefficient (or close to zero), glass having a thermal expansion coefficient of 2.0 to 3.0 × 10 ^-6 ° C is coated to reduce the difference between the thermal expansion coefficient and the semiconductor thin film. Mitigation is also possible.

After preparing the crystallized glass 101 having the above configuration, an amorphous silicon film 102 is formed on the crystallized glass 101. The film is formed by a low pressure thermal CVD method, and silane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used as a film forming gas.
Is used. The film thickness is 50 to 250 nm (typically 100 to 250 nm).
150 nm). (Fig. 1 (A))

As described above, when the film is formed by the low pressure thermal CVD method, the amorphous silicon film 102 can be formed on the front surface, the back surface, and the side surface so as to surround the substrate 101. Strictly speaking, the amorphous silicon film 102 is not formed in a portion where the pusher pin for holding the substrate is in contact. However, it is insignificant from the whole area.

Next, heat treatment is performed to completely oxidize the amorphous silicon film 102 to form a thermal oxide film 103. In this case, since the amorphous silicon film 102 is completely thermally oxidized and changes to the thermal oxide film 103, the thermal oxide film 103
Has a thickness of 100 to 500 nm (typically 200 to 300 nm).

The condition of the heat treatment is a known dry O ₂
Oxidation, wet O ₂ oxidation, steam oxidation, pyrogenic oxidation, oxygen partial pressure oxidation, or hydrochloric acid (HCl) oxidation may be used. Appropriate conditions may be set for the processing temperature and the processing time in consideration of the process.

It is preferable that the heat treatment is performed at a temperature not lower than the strain point of the crystallized glass and lower than the annealing point, and after the temperature is maintained, annealing is performed. By performing such processing, it is possible to take measures against glass shrinkage simultaneously with the formation of the thermal oxide film. That is, by shrinking the substrate sufficiently in advance by the above-described processing, the amount of shrinkage of the substrate due to the subsequent heat treatment can be reduced. A technique related to this is described in Japanese Patent Application Laid-Open No. 8-250744.

The thermal oxide film (silicon oxide film) 103 is formed as described above. Since the amorphous silicon film 102 is formed so as to surround the substrate 101 as described above, The film 103 is also formed so as to surround the substrate 101. That is, since the crystallized glass substrate 101 is completely covered with the insulating silicon film, it is possible to prevent the outflow of the component substances.

Although the silicon oxide film represented by SixOy is used here as the insulating silicon film,
It is also possible to use an insulating silicon film such as a silicon nitride film represented by SixNy or a silicon oxynitride film represented by SiOxNy.

In this manner, two of the important constitutions of the present invention, namely, the point of using crystallized glass and the point of enclosing the crystallized glass with the insulating silicon film are achieved.

Next, a bond wafer 104 is prepared. The surface of the bond wafer 104 is covered with a thermal oxide film 105, and a hydrogen implanted layer 106 is implanted by implanting hydrogen ions (H ⁺ ions) by an ion implantation method.
Are formed.

The thickness of the thermal oxide film 105 is 200 to 700.
nm (typically 400 to 500 nm), and the dose of hydrogen ions is 5 × 10 ¹⁵ to 1 × 10 ¹⁷ ions / cm ² (preferably 1 × 10
^{16 to} 5 × 10 ¹⁶ ions / cm ² ). If the dose is less than this, it is difficult to form a rupture layer.

Then, the bond wafer 10 is placed on the main surface side (the side on which the TFT is formed) of the crystallized glass 101 described above.
4 is bonded at room temperature, and then heat-treated at a temperature of 400 to 600 ° C (typically 500 ° C). At this time, since there is not much difference in the thermal expansion coefficient between the crystallized glass 101 and the bond wafer 104, peeling (film peeling) due to thermal stress is performed.
Such problems can be prevented.

When the heat treatment step is completed, the bond wafer 104 is separated, and the thermally oxidized film 105 which is a part of the bond wafer 104 is formed on the crystallized glass 101.
The single-crystal silicon thin film 107 is left. (Figure 2
(D))

This thermal oxide film 105 is integrated with the thermal oxide film 103 formed in the step of FIG.

Thereafter, a touch polishing step of about 10 nm is performed, and a heat treatment at 900 to 1200 ° C. (typically 950 to 1,050 ° C.) is performed to increase the bonding force of the single crystal silicon thin film 107. Thus, the single-crystal silicon thin film 10 is placed on the crystallized glass 101 whose outer periphery is completely protected by the thermal oxide film 103.
7 can be formed.

The crystallized glass substrate shown in FIG. 1D manufactured according to this embodiment is much lower in manufacturing cost than the conventional case using a quartz substrate. Further, since the outer periphery of the substrate is completely protected by the silicon oxide film, there is no occurrence of contamination by glass components in a later step.

Embodiment 2 In this embodiment, a manufacturing process of a semiconductor device having the structure of the present invention will be described with reference to FIGS. Specifically, NTFT (N-channel TFT)
An example is shown in which a drive circuit and a logic circuit composed of a CMOS circuit in which a TFT and a PTFT (P-channel TFT) are complementarily combined, and a pixel matrix circuit composed of an NTFT are integrally formed on the same substrate.

Note that a logic circuit is a signal processing circuit having a function different from that of a drive circuit represented by a shift register or the like, and includes a D / A converter circuit, a memory circuit, and a γ circuit.
Conventional external ICs such as correction circuits and arithmetic processing circuits
Means a circuit that performs signal processing as performed in the above.

First, the steps up to the formation of a single-crystal silicon thin film are completed according to the manufacturing process described with reference to FIG. Then, the obtained single crystal silicon thin film is patterned to form active layers 303 to 305. Reference numeral 303 denotes an active layer of a PTFT of a CMOS circuit, and reference numeral 304 denotes an NTF of a CMOS circuit.
The T active layer 305 is the active layer of the pixel matrix circuit, and each film is adjusted to have a thickness of 30 nm.

In this embodiment, the substrate 301 is made of Si
Crystallized glass having a composition of O ₂ : 65%, Al ₂ O ₃ : 25%, MgO: 10%, and ZrO ₂ : 10% is used. This substrate 301 is characterized in that it is transparent. Reference numeral 302 denotes a silicon oxide film obtained by thermally oxidizing an amorphous silicon film, and has a thickness of 400 nm.

Thus, the state shown in FIG. 3A is obtained. Next, a gate insulating film 306 made of a silicon oxide film
Is formed to a thickness of 120 nm. Note that a silicon oxynitride film or a silicon nitride film can also be used. Further, these insulating silicon films may be freely combined to form a laminated structure.

After the gate insulating film 306 is formed, a thermal oxidation step is performed in that state at a temperature in the range of 800 to 1100 ° C. (preferably 1000 to 1150 ° C.). At this time, since a thermal oxidation reaction proceeds at the interface between the active layer and the gate insulating film, the active layer is thinned, and the thickness of the gate insulating film increases. This configuration is effective in suppressing the dielectric breakdown of the gate insulating film due to the edge thinning phenomenon (phenomenon in which the thermal oxide film becomes extremely thin at the edge of the active layer).

At this time, the atmosphere for the heat treatment may be an inert atmosphere or an oxidizing atmosphere, but a dry O ₂ atmosphere is preferable for obtaining the most stable interface characteristics. Further, by performing the heat treatment at a high temperature, the film quality of the gate insulating film itself is also improved.

Next, a gate electrode 307 made of a crystalline silicon film having N-type conductivity is formed on the gate insulating film 306.
To 309 are formed. The thickness of the gate electrodes 307 to 309 may be selected in the range of 200 to 300 nm. (FIG. 3
(B))

After forming the gate electrodes 307 to 309,
The gate insulating film 306 is etched by a dry etching method using the gate electrodes 307 to 309 as a mask. In this embodiment, CH is used to etch the silicon oxide film.
F ₃ gas is used.

According to this step, the gate insulating film remains only immediately below the gate electrode (and the gate wiring).
Of course, the portion left under the gate electrode is a portion that actually functions as a gate insulating film.

Next, a region to be a PTFT is hidden by a resist mask 310, and an impurity for imparting N-type (phosphorus in this embodiment) is added by an ion implantation method or a plasma doping method. Part of the low-concentration impurity regions 311 and 312 formed at this time will be LDD (Light
y Doped Drain) 1 × 10 ¹⁷ to 5 × 10 ¹⁸
Phosphorus is added at a concentration of atoms / cm ³ . (FIG. 3
(C))

Next, after removing the resist mask 310, the region to be NTFT is hidden by the resist mask 313, and an impurity (boron in this embodiment) for imparting a P-type is added by an ion implantation method or a plasma doping method. . Also at this time, the low concentration impurity region 314 is formed as in the case of phosphorus. (FIG. 3 (D))

When the state shown in FIG. 3D is obtained,
After removing the resist mask 313, sidewalls 315 to 317 are formed by using an etch-back method. In this embodiment, the sidewalls 315 to 317 are formed using a silicon nitride film.

When a silicon oxide film is used as a material for the sidewall, if the silicon oxide film 302 for protecting the side surface of the crystallized glass 301 is thin, the silicon oxide film may not be formed in the etch back step. Although the outflow of the glass component does not matter much because the glass side surface is sufficiently smaller than the entire area, the silicon oxide film 30
2 may be made thicker so that it remains after the etch-back step.

After the sidewalls 315 to 317 are formed in this way, the region to be the PTFT is hidden again by the resist mask 318, and phosphorus is added. At this time, the dose is set higher than in the previous addition step.

The source region 319 and the drain region 3 of the NTFT constituting the CMOS circuit by the phosphorus doping process.
20, a low concentration impurity region (LDD region) 321 and a channel forming region 322 are defined. Further, a source region 323, a drain region 324, a low-concentration impurity region (LDD region) 325, and a channel formation region 326 of the NTFT constituting the pixel matrix circuit are defined. (FIG. 4 (A))

Next, after removing the resist mask 315, the region to be an NTFT is hidden by the resist mask 327, and boron is added at a higher dose than before. PTF forming a CMOS circuit by the boron addition process
T source region 328, drain region 329, low concentration impurity region (LDD region) 330, channel formation region 33
1 defines. (FIG. 4 (B))

As described above, after the step of adding impurities to the active layer is completed, heat treatment is performed by furnace annealing, laser annealing, or lamp annealing to activate the added impurities. At this time, damage to the active layer caused by the addition of the impurity is also recovered.

The channel forming regions 322, 326,
331 is an intrinsic or substantially intrinsic region to which no impurity element is added. Here, the term “substantially intrinsic” means that the impurity concentration imparting N-type or P-type is equal to or lower than the spin density of the channel formation region, or the impurity concentration is 1 × 10 ¹⁴ to 1 × 10 ¹⁷ atoms / cm 2. Indicates that it is within the range of ³ .

Next, a first interlayer insulating film 332 made of a laminated film of a silicon nitride film having a thickness of 25 nm and a silicon oxide film having a thickness of 900 nm is formed. And Ti / Al / Ti (film thickness is 100 /
Source electrode 3 composed of a laminated film consisting of 500/100 nm)
33 to 335 and drain electrodes 336 and 337 are formed.

Next, a 50 nm thick silicon nitride film 338, 20
A second interlayer insulating film having a stacked structure of a silicon oxide film (not shown) having a thickness of nm and a polyimide film 339 having a thickness of 1 μm is formed. Note that other organic resin films such as acrylic and polyamide can be used in addition to polyimide. Also,
In this case, the 20 nm thick silicon oxide film is a polyimide film 33.
9 functions as an etching stopper when dry-etching.

After the second interlayer insulating film is formed, an opening is provided by etching the polyimide film 339 in a region where an auxiliary capacitance will be formed later. At this time, only the silicon nitride film 338 is left at the bottom of the opening or the silicon nitride film 33
8 and the silicon oxide film (not shown) are left.

Then, a titanium film having a thickness of 300 nm is formed, and a black mask 340 is formed by patterning. The black mask 340 is arranged on a portion requiring light shielding, such as a TFT and a wiring portion, on the pixel matrix circuit.

At this time, in the above-described opening, the drain electrode 337 of the pixel matrix circuit and the black mask 340 are in proximity to each other with the silicon nitride film 338 (or a stacked film of the silicon nitride film and the silicon oxide film) interposed therebetween. . In this embodiment, the black mask 340 is held at a fixed potential,
Drain electrode 337 is used as a lower electrode, black mask 340
Constitutes an auxiliary capacitor 341 having the upper electrode as an upper electrode. In this case, since the dielectric is very thin and has a high relative permittivity, a large capacitance can be secured.

After the black mask 340 and the auxiliary capacitance 341 are formed, a polyimide film having a thickness of 1 μm is formed to form a third interlayer insulating film 342. Then, a contact hole is formed, and a pixel electrode 343 made of a transparent conductive film (typically, ITO) is formed to a thickness of 120 nm.

Finally, a heat treatment is performed at 350 ° C. for about 2 hours in a hydrogen atmosphere to hydrogenate the entire device. Thus, an active matrix substrate as shown in FIG. 4C is completed. Since the TFT formed in this embodiment uses a single crystal silicon thin film as an active layer, it has very high performance.

For example, a subthreshold coefficient (S value)
Is 60 to 80 mV / decade for both NTFT and PTFT.
TFT field-effect mobility (mobility) is 300-700cm ²
/ Vs, PTFT mobility of 200-400cm ² / Vs.

Further, since the single crystal silicon thin film is formed by the smart cut method, the uniformity of the thickness of the active layer on the substrate can be improved. In particular, pixel TFTs that require high uniformity (TFs forming pixel matrix circuits)
The present invention is very effective in suppressing the variation in the characteristic of T).

When the active matrix substrate is completed, an active matrix type liquid crystal display device (transmission type) is completed by sandwiching a liquid crystal layer between the active matrix substrate and a counter substrate by a known cell assembly process.

The structure of the active matrix substrate is not limited to this embodiment, but may be any structure. That is, the TFT structure, circuit arrangement, and the like can be freely designed by the practitioner as long as the structure can satisfy the constituent requirements of the present invention.

For example, in this embodiment, a transparent conductive film is used as the pixel electrode. However, if this is changed to a highly reflective material such as an aluminum alloy film, a reflection type active matrix type liquid crystal display device can be easily realized. Can be. In this case, the crystallized glass serving as the base of the active matrix substrate does not need to be transparent, and a light-shielding substrate may be used.

In this embodiment, since crystallized glass is used as the active matrix substrate, the compatibility is good when a glass substrate is used as the counter substrate. If quartz is used as the active matrix substrate, warpage may occur between the active matrix substrate and the counter substrate due to the difference in thermal expansion coefficient between quartz and glass.

[Embodiment 3] In this embodiment, an example in which an insulating silicon film for protecting crystallized glass in the structure of Embodiments 1 and 2 is formed by a low pressure thermal CVD method will be described.

First, SiO ₂ : 52.5, Al ₂ O ₃ : 26.
_{5, MgO: 11.9, TiO 2} : 11.4 to prepare a crystallized glass the composition components. This is an alkali-free cordierite crystallized glass using TiO ₂ as a nucleating agent.

Next, a silicon oxynitride film is formed on the front, back, and side surfaces of the crystallized glass. In this embodiment, a silicon oxynitride film is formed by a low-pressure thermal CVD method using silane (SiH ₄ ) and nitrous oxide (N ₂ O) as a deposition gas.

In this case, the film forming temperature is set at 800 to 850 ° C. (850 ° C. in this embodiment), and the flow rate of each film forming gas is
_{SiH 4: 10~30sccm, N 2 O} : the 300~900sccm. The reaction pressure may be set to 0.5 to 1.0 torr.

When silane and nitrogen dioxide (N ₂ O) or nitrogen monoxide (NO) are used as a film forming gas, a silicon oxynitride film can be formed at a temperature of 600 to 650 ° C. In that case, the reaction pressure was 0.1～1.0Torr, the gas flow rate is SiH _4: 10~30sccm, NO ₂ or NO: 300~900sccm
It is good.

In this embodiment, since the silicon oxynitride film is formed by the low pressure thermal CVD method, the whole surface of the crystallized glass is covered with the insulating film. Further, by using different deposition gases, a silicon nitride film can be formed as a protective film of crystallized glass.

In this case, 40-50 sccm of dichlorsilane (SiH ₂ Cl ₂ ) and 200-250 sccm of ammonia (NH ₃ ) are used as the film forming gas, the film forming temperature is 750-800 ° C., and the reaction pressure is 0.1. It should be ~ 0.5torr.

The silicon nitride film is the most suitable insulating film for preventing the outflow of the glass component, but is not suitable as a TFT base film because of a high stress. However, in the present invention, since the silicon nitride film is formed on at least the front surface and the rear surface of the crystallized glass, the stress of the silicon nitride film is offset between the front and the back of the substrate, and the substrate does not warp.

[Embodiment 4] This embodiment shows an example in which an insulating silicon film formed by a low pressure thermal CVD method is used as the gate insulating film in Embodiments 1 and 2. FIG. 5 is used for the description. The state shown in FIG. 5 is a state immediately after the gate insulating film is etched after the gate electrode is formed.

In FIG. 5, reference numeral 501 denotes crystallized glass;
Reference numeral 02 denotes a silicon oxynitride film serving as a protective film (base film) for preventing outflow of component substances from crystallized glass. Active layers 503 to 5 are provided on the surface side of crystallized glass 501.
After the gate insulating film 05 is formed and a gate insulating film is formed, gate electrodes 506 to 508 are formed.

By performing dry etching using the gate electrodes 506 to 508 as a mask, the gate insulating films 509 to 511 remain immediately below the gate electrodes.

The most important structure of this embodiment is that an insulating silicon film (in this embodiment, a silicon oxynitride film) formed by a low pressure thermal CVD method is used as a gate insulating film. That is, the gate insulating film also has a surface of the crystallized glass 501,
It is characterized in that a film is formed on all surfaces on the back and side surfaces.

Therefore, when the etching process of the gate insulating film (silicon oxynitride film) is completed (the state shown in FIG. 5), the front surface of the substrate is completely removed except for the portion masked by the gate electrode, and the back surface of the substrate is removed. The silicon oxynitride film 512 remains on the side surface. Note that the silicon oxynitride film formed on the side surface is removed depending on conditions, but there is no problem even if the side surface is removed.

In the structure of this embodiment, even if the back and side surfaces are exposed to an etchant or an etching gas capable of etching the silicon oxynitride film in a later step, the oxynitride film directly formed on the crystallized glass 501 is formed. Silicon film 50
2 can be left. That is, it is possible to thoroughly prevent the outflow of the component substances from the glass substrate.

[Embodiment 5] In Embodiment 2, a crystalline silicon film exhibiting N-type conductivity is used as a gate electrode, but any material having conductivity can be used. In particular, in the case of manufacturing a direct-view liquid crystal display device, it is preferable to use a material having low wiring resistance because the area of the pixel matrix circuit increases.

In such a case, it is desirable to use aluminum or a material containing aluminum as a main component for the gate electrode. In this embodiment, 2 wt.
% Of scandium is used.

In the case where a material containing aluminum as a main component is used as the gate electrode, the method disclosed in Japanese Patent Application Laid-open No.
It is preferable to use the technology described in JP-A-7-135318. In this publication, an anodic oxide film obtained by anodizing a gate electrode is used instead of the sidewall used in the first embodiment.

By using aluminum or a material containing aluminum as a main component as the gate electrode as in this embodiment, it is possible to form a gate wiring having a low wiring resistance, and to manufacture an active matrix substrate having a high response speed. Can be.

This embodiment can be combined with Embodiments 1 to 4.

[Embodiment 6] In Embodiment 2, it is effective to add an impurity element for controlling the threshold voltage (Vth) of the TFT to the active layer. Since the impurity element only needs to be added to at least the channel formation region, it may be added at any time before the formation of the gate electrode.

In the case of addition other than at the time of film formation, means such as addition by ion implantation or plasma doping, addition by diffusion from a gas phase, and addition by diffusion from a solid phase can be used. . These means are effective because they can be selectively added, for example, by making the impurities to be added different between the NTFT and the PTFT.

The impurity element to be added is Vth
To move to the plus side, a group 13 element (boron, gallium or indium) is used, and to move to the minus side, 15 elements (phosphorus, arsenic or antimony) are used.

This embodiment can be combined with the structures of the first to fifth embodiments.

[Embodiment 7] In this embodiment, in the active matrix substrate described in Embodiment 1, a DLC (Diamond Like Corbon) is used as a heat sink on the third interlayer insulating film 342 (see FIG. 4C). An example in which a film is used will be described.

The structure shown in FIG. 6 is basically similar to the structure shown in FIG.
Having the same structure as that of FIG.
The difference is that a C film 601 is provided.

DLC is carbon or a material having a high hardness containing carbon as a main component and exhibiting physical properties like diamond. It is also called i-carbon, and is mainly composed of sp ³ bonds.

Diamond is a material having the highest thermal conductivity at room temperature (about 10 to 20 W / cm · k at room temperature), and a DLC film having the same physical properties also exhibits high thermal conductivity. In the present embodiment, the high heat conductivity is used to function as a heat sink.

Further, since the DLC film has excellent adhesion to an organic resin film, it is a very effective material when an organic resin film is used as an interlayer insulating film and a heat sink is provided thereon.

As a means for forming the DLC film, a vapor phase film forming method such as a plasma CVD method, an ECR plasma CVD method, a sputtering method, an ion beam sputtering method, or an ionized vapor deposition method can be used.

Further, hydrocarbon is used as a source gas when forming the DLC film. Examples of the hydrocarbon include saturated hydrocarbons such as methane, ethane, and propane, and unsaturated hydrocarbons such as ethylene and acetylene. Alternatively, a halogenated hydrocarbon in which one or more hydrogen atoms of a hydrocarbon molecule are substituted with a halogen element may be used.

It is effective to add hydrogen in addition to hydrocarbons. When hydrogen is added, the number of hydrogen radicals in the plasma increases, and the effect of extracting excess hydrogen in the film and improving the film quality can be expected. At this time, the ratio of the hydrogen gas flow rate to the total gas flow rate is 30 to 90%, preferably 50 to 70%.
Is good. If the ratio is too large, the film formation rate is reduced, and if it is too small, the effect of extracting excess hydrogen is lost.

Further, helium can be added as a carrier gas for diluting the source gas, and in the case of a sputtering method, argon may be added as a sputtering gas. It is also effective to add an element belonging to Groups 13 to 15 as described in JP-A-6-208721.

The reaction pressure is 5 to 1000 mTorr, preferably 10 to 100 mTorr. 13.56 MHz is usually used for high frequency power. At this time, RF power to be applied 0.01~1W / cm ^2, preferably between 0.05 to 0.5 / cm ^2. It is also effective to add a 2.45 GHz microwave excitation effect to promote decomposition of the source gas, or to form a 875 Gauss magnetic field in the excitation space and use electron spin resonance.

In this embodiment, 50 sccm of methane gas and 50 g of hydrogen gas are used as raw material gases in the reaction space of the plasma CVD apparatus.
Introduce sccm, deposition pressure is 10mTorr, RF power is 100W,
The temperature of the reaction space is room temperature. Further, a DC bias of 200 V is applied as a substrate bias to form an electric field such that particles (ions) in the plasma are incident on the surface on which the film is to be formed, thereby improving the film quality and improving the hardness.

The DLC film has very high abrasion resistance even if the film thickness is about 10 nm. Therefore, the structure shown in FIG. 7 has an effect of protecting the third interlayer insulating film 342 from mechanical shock. This is very effective for a friction process such as a rubbing process.

The coefficient of friction depends on the DLC film thickness, and decreases as the DLC film thickness increases. Therefore, DL
It is sufficient that the thickness of the C film is 10 nm or more, but if it is too thick, the electric field applied to the liquid crystal is weakened.

It should be noted that a more detailed method and apparatus for forming a DLC film are described in Japanese Patent Publication No.
Reference should be made to JP-A-72711, JP-A-4-27690 and JP-A-4-27691.

In the structure shown in FIG. 7 obtained by the above-described structure, heat generated in the TFT is released with high efficiency.
Malfunction due to heat storage can be prevented. In particular, it is better to use such a heat-resistant structure for a liquid crystal display device used for a projection type electronic device.

[Embodiment 8] FIG. 7 shows an example in which a liquid crystal display device is constructed using the active matrix substrates having the constructions shown in Embodiments 1 to 7. FIG. 7 shows a portion corresponding to the main body of the liquid crystal display device, which is also called a liquid crystal module.

In FIG. 7, reference numeral 701 denotes crystallized glass;
Numeral 02 is an insulating silicon film formed so as to cover the entire surface of the crystallized glass. In the case where multiple active matrix substrates are cut out from a large-size substrate by cutting multiple substrates, there is no insulating silicon film on the side that will be the cut surface, but the insulating silicon film remains on the other side. This is a feature of the invention. Of course, since it is completed as an active matrix substrate, there is no fear that the component material flows out even if it is not protected by the insulating silicon film.

A plurality of TFTs are formed of a single-crystal silicon thin film on a substrate having such a structure. These TFTs constitute a pixel matrix circuit 703, a gate side drive circuit 704, a source side drive circuit 705, and a logic circuit 706 on a substrate. Then, a counter substrate 707 is attached to such an active matrix substrate. A liquid crystal layer (not shown) is sandwiched between the active matrix substrate and the counter substrate 707.

In the structure shown in FIG. 7, it is desirable that the side surfaces of the active matrix substrate and the side surface of the counter substrate are all aligned except for one side. This makes it possible to efficiently increase the number of multi-face removal from the large-size substrate. In addition, on one side described above, a part of the opposing substrate is removed to expose a part of the active matrix substrate, and the FPC is
(Flexible Print Circuit) 708 is attached. Here, an IC chip (semiconductor circuit including a MOSFET formed on single crystal silicon) may be mounted as needed.

Since the TFT constituting the circuit of this embodiment has an extremely high operation speed, several hundred MHz to several GHz
Can be integrally formed on the same substrate as the pixel matrix circuit. That is, the liquid crystal module shown in FIG. 7 embodies a system-on-panel.

Although the present embodiment describes a case in which the present invention is applied to a liquid crystal display device, an active matrix type EL (electroluminescence) display device or the like can be constructed. Further, an image sensor or the like including a photoelectric conversion layer can be formed over the same substrate.

A device having a function of converting an optical signal into an electric signal or a function of converting an electric signal into an optical signal, such as the above-described liquid crystal display device, EL display device, and image sensor, is defined as an electro-optical device. The present invention can be applied to any electro-optical device that can be formed using a semiconductor thin film on a substrate having an insulating surface.

[Embodiment 9] According to the present invention, not only the electro-optical device as shown in Embodiment 8 but also a thin film integrated circuit (or semiconductor circuit) in which functional circuits are integrated can be constructed. For example, an arithmetic circuit such as a microprocessor or a high-frequency circuit (MMIC: microwave module IC) for a portable device can be configured.

Furthermore, a semiconductor circuit having a three-dimensional structure can be formed by taking advantage of a TFT using a thin film, and a VLSI circuit integrated at an extremely high density can be formed.
As described above, a highly functional semiconductor circuit can be formed using the TFT of the present invention. Note that in this specification, a semiconductor circuit is defined as an electric circuit that controls and converts an electric signal using semiconductor characteristics.

[Embodiment 10] In this embodiment, FIG. 8 shows an example of an electronic apparatus (applied product) on which the electro-optical device and the semiconductor circuit shown in Embodiments 8 and 9 are mounted. Note that an electronic device is defined as a product equipped with a semiconductor circuit and / or an electro-optical device.

The electronic apparatus to which the present invention can be applied includes a video camera, an electronic still camera, a projector, a head mounted display, a car navigation, a personal computer, a portable information terminal (mobile computer, mobile phone, PHS, etc.).

FIG. 8A shows a mobile phone, and a main body 200.
1, audio output unit 2002, audio input unit 2003, display device 2004, operation switch 2005, antenna 2006
It consists of. The present invention can be applied to the audio output unit 2002, the audio output unit 2003, the display device 2004, and the like.

FIG. 8B shows a video camera,
101, display device 2102, audio input unit 2103, operation switch 2104, battery 2105, image receiving unit 210
6. The present invention can be applied to the display device 2102, the sound input unit 2103, the image receiving unit 2106, and the like.

FIG. 8C shows a mobile computer (mobile computer), which includes a main body 2201 and a camera section 2.
202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention is a camera unit 220.
2. Applicable to the image receiving unit 2203, the display device 2205, and the like.

FIG. 8D shows a head-mounted display, which includes a main body 2301, a display device 2302, and a band section 2.
303. The present invention can be applied to the display device 2302.

FIG. 8E shows a rear type projector, in which a main body 2401, a light source 2402, a display device 2403,
Polarizing beam splitter 2404, reflector 240
5, 2406 and a screen 2407. The invention can be applied to the display device 2403.

FIG. 8F shows a front type projector, which includes a main body 2501, a light source 2502, and a display device 250.
3. It comprises an optical system 2504 and a screen 2505. The invention can be applied to the display device 2503.

As described above, the applicable range of the present invention is extremely wide, and it can be applied to electronic devices in all fields. Further, the present invention can be applied to all products requiring an electro-optical device or a semiconductor circuit.

[0148]

According to the present invention, crystallized glass which is inexpensive and can be enlarged is used, and at least the front and rear surfaces (preferably, glass) are used in order to utilize the crystallized glass safely (without fear of contamination). A configuration is adopted in which the entire outer periphery is protected by an insulating silicon film.

Then, a system-on-panel is realized by manufacturing a TFT using a single-crystal silicon thin film formed thereon using a smart cut method, and a high-performance electro-optical device, a semiconductor circuit, Can provide electronic devices equipped with them at a low price.

[Brief description of the drawings]

FIG. 1 is a view showing a manufacturing process of a single crystal silicon thin film.

FIG. 2 is a diagram showing steps of a smart cut method.

FIG. 3 illustrates a manufacturing process of a thin film transistor.

FIG. 4 illustrates a manufacturing process of a thin film transistor.

FIG. 5 illustrates a structure of a thin film transistor.

FIG. 6 illustrates a structure of a thin film transistor.

FIG. 7 illustrates a configuration of a liquid crystal module.

FIG. 8 illustrates a structure of an electronic device.

Claims (6)

[Claims] 1. A glass substrate having a strain point of 750 ° C. or higher, an insulating silicon film formed on at least the front and back surfaces of the glass substrate, and a single crystal silicon formed on the insulating silicon film And a TFT having a thin film as a channel formation region. 2. A glass substrate having a strain point of 750 ° C. or higher, an insulating silicon film formed so as to cover the outer periphery of the glass substrate, and a single crystal silicon thin film formed on the insulating silicon film. A semiconductor device, comprising: a TFT serving as a channel formation region; 3. The semiconductor device according to claim 1, wherein the glass substrate is a crystallized glass. 4. A step of forming an amorphous semiconductor thin film over the entire surface of a glass substrate having a strain point of 750 ° C. or higher, and oxidizing the amorphous semiconductor thin film by a first heat treatment;
A method for manufacturing a semiconductor device, comprising: a step of completely transforming into a thermal oxide film; and a step of forming a single-crystal silicon thin film on a main surface side of the glass substrate by a smart cut method. 5. A step of forming an insulating silicon film on the entire surface of a glass substrate having a strain point of 750 ° C. or more by low pressure thermal CVD, and a step of forming a single crystal silicon on a main surface of the glass substrate by a smart cut method. A method for manufacturing a semiconductor device, comprising: forming a thin film. 6. The method for manufacturing a semiconductor device according to claim 4, wherein the glass substrate is crystallized glass.