JP4892852B2 - Serial interface control method - Google Patents

Description

  The present invention relates to a data input / output technology in a serial interface, and more particularly to a data input / output speed-up technology in a serial interface.

  The serial interface only needs to have at least one input terminal and one output terminal by serially transferring the input and output of signals such as data and addresses in time series. This is an interface technology that enables signal input / output with a minimum number of terminals as compared to a parallel interface that has a large number of terminals and performs signal input / output. When a large number of input / output terminals and power supply terminals for inputting / outputting other control signals are required, and / or in semiconductor integrated circuits, the number of terminals that can be mounted is limited due to chip size restrictions or mounting package restrictions. It is an effective interface technology that is applied when there are restrictions.

  However, in the serial interface, since signals such as data and addresses are transferred serially, much transfer time is required as compared with a parallel interface having a large number of terminals and transferring a large number of signals at once. If a large number of terminals are required or / and the number of mounted terminals is limited due to restrictions on the chip size or mounting package size, there is a possibility that it may not be possible to meet the demand for high-speed signal transfer.

  The present invention has been made in view of the problems of the background art described above, and a serial interface control method capable of responding to a request for high-speed signal transfer while enabling signal input / output with the minimum number of terminals. The purpose is to provide.

In order to achieve the above object, a serial interface control method according to the present invention includes a first signal path and a second signal path, and a signal transfer is performed in a first transfer direction or a second transfer direction. A control method for controlling an interface, wherein a control signal instructing to perform signal transfer by parallel transfer in which signals are transferred in parallel in the same direction via the first and second signal paths prior to signal transfer is provided in the first signal path. Forward through. When instructing parallel transfer, the least significant bit signal of the address signal indicating the storage address of the signal transferred in parallel is not input. Alternatively, among the address signals indicating the storage addresses of the signals transferred in parallel, the least significant bit signal is transferred through the second signal path, and the address signal excluding the least significant bit signal is transferred through the first signal path. Alternatively, among the address signals indicating the storage addresses of the signals transferred in parallel, a plurality of bit signals including the least significant bit signal are transferred through the second signal path, and the address signals excluding the plurality of bit signals are transferred to the first signal path. Transfer with.
Here, the step of performing signal transfer by parallel transfer via the first and second signal paths in response to the parallel transfer instruction is performed when the transfer direction of the signal transfer is opposite to the transfer direction of the control signal. After the signal is transferred through one signal path of the first and second signal paths, the control signal is transferred after signal transfer is started in the other signal path of the first and second signal paths. Also in the signal path, signal transfer is performed and parallel transfer is performed.

  Accordingly, in the serial interface that serially transfers signals such as data and addresses, the signal transfer in the first transfer direction and the signal transfer in the second transfer direction are performed according to the control signal in the first signal path or This can be done via the first and second signal paths, the second signal path or the first and second signal paths.

  In a serial interface that has a transfer path according to a transfer direction and performs signal transfer in time series, the signal transfer in the first or second transfer direction is performed in accordance with a control signal by the first signal path and the second signal path. The signal transfer speed can be improved by performing in parallel via the. Increase the signal transfer width even when a large number of signal paths are required or / and restrictions on equipment such as mounting limit the signal paths that can be mounted and a serial interface must be used. Can handle high-speed transfer.

  According to the present invention, it is possible to provide a serial interface control method capable of supporting high-speed signal transfer while having a necessary minimum signal path.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a serial interface control method according to the present invention will be described below in detail with reference to FIGS.

  FIG. 1 is a diagram illustrating a serial interface according to an embodiment of the present invention. In FIG. 1, the device 1 is, for example, a flash memory having a serial interface. Similar to a general serial interface, the device 1 includes a signal input terminal (SI) and a signal output terminal (SO). The signal input terminal (SI) is connected to the first signal path P1, and a signal is serially input in the serial transfer operation state. The signal output terminal (SO) is connected to the second signal path P2, and a signal is serially output in the serial transfer operation state.

  The device 1 includes a clock terminal (CLK), and a synchronous operation is performed according to an input clock signal (not shown). Specifically, a 1-bit signal is input / output from the signal input terminal (SI) or / and the signal output terminal (SO) every clock cycle. In the serial interface according to the embodiment, an input / output operation is performed with a group of 8-bit signals in units of transfer of 8 clock cycles. A so-called halfword boundary operation is performed. A signal for controlling activation / deactivation of the device 1 is input to the chip select terminal (CS).

  After the device 1 is activated in accordance with a chip select signal CS (for example, see FIG. 3) input to the chip select terminal (CS), the device 1 propagates through the first signal path P1 to the signal input terminal ( The control code OPC (for example, see FIG. 3) and the address signal ADDR (for example, see FIG. 3) are sequentially input via SI). The control code OPC that is input first is input to the control code decoder 15. After the input of the address signal ADDR, signal transfer attributes such as input / output data signals D0 to D3 (for example, see FIG. 5) are determined.

  In the device 1, the signal input terminal (SI) is provided with an output buffer 12 in addition to the input buffer 11. The signal output terminal (SO) includes an input buffer 13 in addition to the output buffer 14. The input buffer 11, the output buffer 12, the input buffer 13, and the output buffer 14 include an enable terminal (EN) that controls activation / deactivation of circuit operation. The control code OPC is decoded by the control code decoder 15, and activation signals EN1, EN2, EN3, and EN4 are output according to the attribute of signal transfer. The activation signals EN1, EN2, EN3, and EN4 are input to each enable terminal (EN).

  FIG. 2 is a diagram showing signal transfer attributes indicated by the control code OPC and activation signals EN1 to EN4 output from the control code decoder 15 for the respective signal transfer attributes.

  Regarding the attribute of signal transfer, in addition to reading (R) (output) and writing (W) (input) of a data signal, in the embodiment, as a transfer mode, an operation mode of serial transfer and an operation mode of parallel transfer are used. There is another.

  In the data read (R) operation in the serial mode, a data read operation is performed from the signal output terminal (SO) via the output buffer 14. The activation signal EN4 becomes high level (H), and the output buffer 14 is activated. On the other hand, the activation signals EN1 to EN3 are at a low level (L), and the input buffer 11, the output buffer 12, and the input buffer 13 are inactivated.

  In the data write (W) operation in the serial mode, a data write operation is performed from the signal input terminal (SI) via the input buffer 11. The activation signal EN1 becomes high level (H), and the input buffer 11 is activated. On the other hand, the activation signals EN2 to EN4 are at a low level (L), and the output buffer 12, the input buffer 13, and the output buffer 14 are inactivated.

  In the data read (R) operation in the parallel mode, data read operations are performed in parallel from the signal input terminal (SI) and the signal output terminal (SO) through the output buffers 12 and 14. Activation signals EN2 and EN4 become high level (H), and output buffers 12 and 14 are activated. On the other hand, activation signals EN1 and EN3 are at a low level (L), and input buffers 11 and 13 are inactivated.

  In the data write (W) operation in the parallel mode, data write operations are performed in parallel from the signal input terminal (SI) and the signal output terminal (SO) via the input buffers 11 and 13. Activation signals EN1 and EN3 become high level (H), and input buffers 11 and 13 are activated. On the other hand, activation signals EN2 and EN4 are at a low level (L), and input buffers 12 and 14 are inactivated.

  The signal transfer attribute can be determined by decoding the control code OPC, and a signal is written from the signal input terminal (SI) and a signal is read from the signal output terminal (SO) according to the signal transfer attribute. The serial interface operation can be performed. In addition, a parallel operation in which a signal is written or read out from the signal input terminal (SI) and the signal output terminal (SO) can be performed.

  A control method in the case where a parallel operation is performed on the serial interface of the embodiment will be described below with reference to timing charts shown in FIGS. In the following description, a data read operation will be described, but a similar control method can be used for a data write operation.

  In FIG. 3 to FIG. 7, after input of the control signal composed of the control code OPC and the address signal ADDR or ADDR1 and ADDR2 (step (I)), the data signals D0 to D2 or D3 are read out in parallel operation (step (I)). This is a case where step (II) is performed. This is a case where the transfer direction of the control signal and the transfer direction of the data signals D0 to D2 or D3 are reversed. In the signal input terminal (SI), it is necessary that the input buffer 11 is in the activated state and the output buffer 12 is in the inactivated state during the period in which the control signal is input. In the data signal output period, the output buffer 12 needs to be activated and the input buffer 11 must be deactivated. In the process from step (I) to step (II), it is necessary to switch the active state between the input buffer and the output buffer.

  In FIG. 3, at the start of step (II), while the data signal D0 of the 8-bit signal as the transfer unit is output from the signal output terminal (SO), the input / output buffer 11/12 at the signal input terminal (SI). Is a control method for switching the active state.

  The device 1 is activated in response to the signal input to the chip select terminal (CS) transitioning to a low level. Input of the control signal is started from the signal input terminal (SI) in synchronization with the clock signal input to the clock terminal (CLK). The first is the control code OPC. It is assumed that the control code OPC is composed of an 8-bit signal that constitutes a transfer unit in 8 clock cycles by the half word boundary operation.

  The attribute of signal transfer is determined according to the decoding of the control code OPC. In this case, since the data read (R) is performed in parallel operation, the activation signal EN4 immediately transitions to the high level to activate the output buffer 14 and wait for the data signal read timing. On the other hand, the deactivation of the input buffer 11 and the activation of the output buffer 12 wait until the input of the control signal is completed. This is because the input of the control code OPC from the signal input terminal (SI) and the subsequent input of the address signal ADDR are performed.

  After the input of the address signal ADDR from the signal input terminal (SI) is completed, a data signal read operation is performed. In the control method of FIG. 3, the read operation of the data signal is started in advance by the read operation of the data signal D0 from the signal output terminal (SO) not used for inputting the control signal ((III in FIG. 3). ) Step) Control is performed.

  During this time, the activation state of the input buffer 11 and the output buffer 12 connected to the signal input terminal (SI) is inverted. That is, in the device 1 that is the transfer destination of the control signal, the output buffer 12 is activated by the high-level transition of the activation signal EN2, and the signal output transitions to a possible state. Further, the input buffer 11 is deactivated by the low level transition of the activation signal EN1, and the signal input transitions to the disabled state. On the other hand, at the control signal transfer source (not shown), among the input / output buffers connected to the first signal path P1, the output buffer is deactivated, the signal output is changed to the disabled state, and the input buffer is activated. Transition to a signal input enabled state. This control is shown in step (IV) in FIG.

  If this control step (IV) is performed during a period in which the first 8-bit data signal D0 is output from the signal output terminal (SO) by the half word boundary operation, the signal input terminal is used in the next 8 clock cycles. The data signal D1 from (SI) can be output. At this time, the data signal D2 can also be output from the signal output terminal (SO). From the signal input terminal (SI) and the signal output terminal (SO), the data signal can be read out in a parallel operation.

  In FIG. 4, at the start of step (II), an 8-bit data signal D0 as a transfer unit is alternately output between the signal output terminal (SO) and the signal input terminal (SI) for each bit. . This is a control method for switching the active state of the input / output buffer 11/12 at the signal input terminal (SI) while the first bit is output from the signal output terminal (SO).

  Since the operation in step (I) is the same as that in FIG. 3, the description thereof is omitted here.

  After the input of the address signal ADDR from the signal input terminal (SI) is completed, a data signal read operation is performed. In the control method of FIG. 4, as in FIG. 3, the data signal read operation starts in advance with the read operation from the signal output terminal (SO) that is not used for the input of the control signal (in FIG. 4, (Step (III)) Control is performed.

  Here, the data signal read in advance from the signal output terminal (SO) at the start of step (II) is the entire data signal D0, which is an 8-bit signal in the transfer unit in the control method of FIG. In FIG. 4, this is the first bit of the data signal D0. Thereafter, the data signal D0 is alternately output for each bit with the signal input terminal (SI).

  While the first bit of the data signal D0 is being output from the signal output terminal (SO), the activation state of the input buffer 11 and the output buffer 12 connected to the signal input terminal (SI) is inverted. That is, in the device 1 that is the transfer destination of the control signal, the output buffer 12 is activated by the high-level transition of the activation signal EN2, and the signal output transitions to a possible state. Further, the input buffer 11 is deactivated by the low level transition of the activation signal EN1, and the signal input transitions to the disabled state. On the other hand, at the control signal transfer source (not shown), among the input / output buffers connected to the first signal path P1, the output buffer is deactivated, the signal output is changed to the disabled state, and the input buffer is activated. Transition to a signal input enabled state. This control is shown in step (IV) in FIG.

  Since this step (IV) is performed during the period when the first bit of the data signal D0 is output, the data signal can be output from the signal input terminal (SI) in addition to the signal output terminal (SO). It becomes. Thereby, a data signal can be alternately output for each bit from the signal input terminal (SI) and the signal output terminal (SO). From the signal input terminal (SI) and the signal output terminal (SO), the data signal can be read out in a parallel operation.

  In FIG. 5, the least significant bit signal of the address signal ADDR input in step (I) is not input. If the address signal ADDR is to be transferred to the lower level, a half-word boundary operation is performed, and the transfer of the address signal is ensured for each transfer unit of 8 bit cycles. In the final clock cycle of step (I), a cycle in which no signal is input can be generated (step (V) in FIG. 5). This control method uses this cycle to switch the active state of the input / output buffer 11/12 at the signal input terminal (SI). Here, the control for not inputting the least significant bit signal of the address signal ADDR is consistent with the control in the step (II) of outputting the data signal in a parallel operation. This is because if the least significant bit signal is not input, data signals stored in two adjacent addresses can be selected simultaneously.

  The other operations in step (I) are the same as those in FIG.

  While the least significant bit signal of the address signal ADDR is not input (during the step (V)), the activation state of the input buffer 11 and the output buffer 12 connected to the signal input terminal (SI) is inverted. . That is, in the device 1 that is the transfer destination of the control signal, the output buffer 12 is activated by the high-level transition of the activation signal EN2, and the signal output transitions to a possible state. Further, the input buffer 11 is deactivated by the low level transition of the activation signal EN1, and the signal input transitions to the disabled state. On the other hand, at the control signal transfer source (not shown), among the input / output buffers connected to the first signal path P1, the output buffer is deactivated, the signal output is changed to the disabled state, and the input buffer is activated. Transition to a signal input enabled state. This control is shown in step (VIII) in FIG.

  Since this step (VIII) is performed while the least significant bit signal of the address signal ADDR is not input (during the step (V)), it is added to the signal output terminal (SO) at the start of step (II). Thus, the data signal can also be output from the signal input terminal (SI). As a result, the data signal can be read from the signal input terminal (SI) and the signal output terminal (SO) in parallel operation. FIG. 5 shows a case where output is performed for each 8-bit data signal D0 to D3 which is a transfer unit from the signal input terminal (SI) and the signal output terminal (SO).

  In FIG. 6, in step (I), the least significant bit signal of the address signal ADDR is not input from the signal input terminal (SI), and the signal output terminal is within the period of the transfer unit to which the address signal ADDR is input. Input from (SO) (step (VI) in FIG. 6). That is, the address signal ADDR1 input from the signal input terminal (SI) is an address signal excluding the least significant bit signal, and the address signal ADDR2 input from the signal output terminal (SO) is the least significant bit signal.

  Since the half word boundary operation is performed and the transfer of the address signal is ensured for each transfer unit of 8 bit cycles, the signal input is performed in the final clock cycle of step (I) before proceeding to step (II). A cycle that is not missed can be generated (step (VI) in FIG. 6). This control method uses this cycle to switch the active state of the input / output buffer 11/12 at the signal input terminal (SI).

  In the final clock cycle of step (VI), the activation of the input buffer 11 and the output buffer 12 connected to the signal input terminal (SI) by the low level transition of the activation signal EN1 and the high level transition of the activation signal EN2 The control to reverse the state (step (VIII) in FIG. 6) is the same as in FIG.

  In FIG. 6, control is performed to input the address signal ADDR2 which is the least significant bit signal from the signal output terminal (SO) during the input period of the address signal ADDR1.

  The control code OPC input prior to the input of the address signals ADDR1 and ADDR2 is decoded by the control code decoder 15. In response to the decoding of the control code OPC, the activation signal EN3 transitions to a high level to activate the input buffer 13, thereby enabling the input of the address signal ADDR2. The activation signal EN3 changes to the low level after the input of the address signal ADDR2 and before the step (II) is started. The activation signal EN4 also transitions to a high level before step (II) is started. As a result, the signal output terminal (SO) is ready to output a data signal by the start of step (II). The timing at which the activation signal EN3 transitions to the low level and the timing at which the activation signal EN4 transitions to the high level may be set after counting a predetermined clock cycle according to the control code OPC.

  In FIG. 7, in step (I), the address signal ADDR is divided into two and input in parallel from the signal input terminal (SI) and the signal output terminal (SO) (step (VII) in FIG. 7). That is, in FIG. 7, the address signal ADDR2 input from the signal output terminal (SO) is limited to the least significant bit signal, and FIG. 7 shows a control method that does not provide this limitation.

  Since the half-word boundary operation is performed, a cycle in which no signal is input is generated in the period from the completion of the transfer of each of the divided address signals ADDR1 and ADDR2 to the end of the transfer unit of the 8-bit cycle. (Step (VII) in FIG. 7). In step (I) before the transition to step (II), a clock cycle without signal input is provided, and this cycle is used to determine the active state of the input / output buffer 11/12 at the signal input terminal (SI). This is a control method for switching.

  The input buffer 11 and the output buffer 12 connected to the signal input terminal (SI) by the low level transition of the activation signal EN1 and the high level transition of the activation signal EN2 in the clock cycle without the signal input of step (VII). The control for inverting the activation state is the same as in the case of FIG.

  Further, the activation signal EN3 is transited to a low level, and the activation signal EN4 is transited to a high level. Transition of the active state of the input / output buffer of each terminal (SI), (SO) accompanying the level transition of the activation signals EN1 to EN4 is performed (step (VIII) in FIG. 7).

  Here, the activation signal EN3 transitions to a high level when the device 1 is activated by a low level input to the chip select terminal (CS). This is because one of the divided address signals ADDR2 is input from the signal output terminal (SO) in step (I).

  As described above in detail, according to the control method of the serial interface according to the present embodiment, the signal input terminal (SI) and the signal output terminal 'SO) according to the control signal input from the signal input terminal (SI). Therefore, when data signals are input / output in parallel, reading of the data signals is preceded by the signal output terminal (SO) (FIGS. 3 and 4), or transfer secured as an input period of the address signal ADDR By not inputting an address signal in the subsequent clock cycle of the unit (FIGS. 5 to 7), the signal input / output can be switched at the signal input terminal (SI). It is possible to smoothly switch between the control signal input and the data signal input / output.

The present invention is not limited to the above-described embodiment, and it goes without saying that various improvements and modifications can be made without departing from the spirit of the present invention.
For example, for the activation signals EN3 and EN4 for controlling the input / output of the signal output terminal (SO), in FIG. 6, the activation signal EN3 transitions to a high level according to the control code OPC, and after the address signal ADDR2 is input. Although the activation signal EN3 has transitioned to a low level and the activation signal EN4 has transitioned to a high level during the period of step (I), the present invention is not limited to this. The activation signal EN3 can be set to the high level in response to the input of the low level signal to the chip select terminal (CS). Further, the low level transition of the activation signal EN3 and the high level transition of the activation signal EN4 can be performed at the same time as the transition period (step (VIII)) of the activation signals EN1 and EN2.
In FIG. 7 as well, the timing of the high level transition of the activation signal EN3 can be changed to an appropriate timing as long as the timing is prior to the input of the address signal ADDR2.
Although the case of outputting a data signal has been described in the present embodiment, it goes without saying that the same applies to the case of inputting a data signal.

Here, the means for solving the problems in the background art according to the technical idea of the present invention are listed below.
(Supplementary Note 1) A first signal path in which signal transfer is performed in a first transfer direction and a second signal path in which signal transfer is performed in a second transfer direction opposite to the first transfer direction are provided. A serial interface control method configured as follows:
Prior to the signal transfer, transferring a control signal indicating an attribute of the signal transfer;
Depending on the attribute of the signal transfer, the signal transfer is performed in the first transfer direction via the second signal path in addition to the first signal path, or the first signal path is added to the first signal path. And a step of performing the signal transfer in the second transfer direction via a signal path.
(Supplementary note 2) The serial interface control method according to supplementary note 1, wherein the attribute of the signal transfer includes selection of a transfer direction of the signal transfer and a signal path on which the signal transfer is performed.
(Supplementary Note 3) The step of performing the signal transfer via the first and second signal paths includes:
When the transfer direction of the signal transfer is opposite to the transfer direction of the control signal, after the control signal is transferred through one signal path of the first and second signal paths, the first and second The serial interface control method according to claim 1, further comprising a step of starting the signal transfer in advance in another signal path of the two signal paths.
(Supplementary Note 4) During the step in which the signal transfer is started in advance in the other signal path,
At the transfer source of the control signal in the one signal path, the signal output transitions to the disabled state and to the signal input enabled state, and at the transfer destination of the control signal in the one signal path, the signal output is possible The serial interface control method according to appendix 3, further comprising a step of transitioning to a state and a transition of a signal input to a disabled state.
(Supplementary note 5) The serial interface control method according to supplementary note 1, wherein the transfer of the control signal and the signal transfer are performed with a predetermined number of cycles as a transfer unit.
(Additional remark 6) The address signal which instruct | indicates the storage address of the said signal is allocated so that it should descend to the back | latter stage bit string in the said control signal,
The serial interface control method according to appendix 5, further comprising a step of not inputting the least significant bit signal of the address signals.
(Supplementary Note 7) An address signal that indicates a storage address of the signal is assigned to a downstream bit string in the control signal so as to fall.
(Supplementary note 5) including a step of transferring the least significant bit signal of the address signal and the address signal excluding the least significant bit signal through the first signal path and the second signal path, respectively. The serial interface control method described.
(Supplementary note 8) The serial interface control method according to supplementary note 5, further comprising a step of dividing the control signal into two parts and transferring the control signal in parallel through the first signal path and the second signal path.
(Supplementary Note 9) After the transfer of the control signal is completed and before the transfer unit at the completion of the transfer is completed, the signal output at the transfer source of the control signal is changed to the disabled state and the signal is input. Transition to a possible state, and at the transfer destination of the control signal, there is a step of transitioning the signal output to the possible state and the signal input to the impossible state. The serial interface control method according to the item.

It is a figure which shows the serial interface of embodiment. It is a figure which shows the attribute of signal transfer. It is a figure (1) which shows the control method of a serial interface. It is a figure (2) which shows the control method of a serial interface. It is a figure (3) which shows the control method of a serial interface. It is a figure (4) which shows the control method of a serial interface. It is a figure (5) which shows the control method of a serial interface.

1 device 11, 13 input buffer 12, 14 output buffer 15 control code decoder P1 first signal path P2 second signal path (CLK) clock terminal (CS) chip select terminal (SI) signal input terminal (SO) signal output terminal ADDR ADDR1, ADDR2 Address signal D0, D1, D2, D3 Data signal EN1, EN2, EN3, EN4 Activation signal OPC Control code

Claims (3)

A method for controlling a serial interface, comprising a first signal path and a second signal path, wherein signal transfer is performed in a first transfer direction or a second transfer direction,
Prior to the signal transfer, a pre-SL control signal for instructing to perform the signal transmission in parallel transfers a signal through the first and second signal paths in parallel transferred to the same direction through the first signal path Forward,
When instructing the parallel transfer, the least significant bit signal out of the address signal indicating the storage address of the signal to be transferred in parallel is not input ,
Performing the signal transfer in parallel transfer via the first and second signal paths in response to the parallel transfer instruction,
When the transfer direction of the signal transfer is opposite to the transfer direction of the control signal, after the control signal is transferred through one signal path of the first and second signal paths, the first and second characterized in that said control signal after the preceding to the signal transfer is started in the other signal paths of the two signal paths to have a step of performing said signal transfer is performed even parallel transfer in the signal path which is transferred The serial interface control method. A method for controlling a serial interface, comprising a first signal path and a second signal path, wherein signal transfer is performed in a first transfer direction or a second transfer direction,
Prior to the signal transfer, a pre-SL control signal for instructing to perform the signal transmission in parallel transfers a signal through the first and second signal paths in parallel transferred to the same direction through the first signal path Forward,
When instructing the parallel transfer, among the address signals indicating the storage addresses of the signals to be transferred in parallel, the least significant bit signal is transferred through the second signal path, and the address signal excluding the least significant bit signal is Forward on the first signal path ,
Performing the signal transfer in parallel transfer via the first and second signal paths in response to the parallel transfer instruction,
When the transfer direction of the signal transfer is opposite to the transfer direction of the control signal, after the control signal is transferred through one signal path of the first and second signal paths, the first and second characterized in that said control signal after the preceding to the signal transfer is started in the other signal paths of the two signal paths to have a step of performing said signal transfer is performed even parallel transfer in the signal path which is transferred The serial interface control method. A method for controlling a serial interface, comprising a first signal path and a second signal path, wherein signal transfer is performed in a first transfer direction or a second transfer direction,
Prior to the signal transfer, a pre-SL control signal for instructing to perform the signal transmission in parallel transfers a signal through the first and second signal paths in parallel transferred to the same direction through the first signal path Forward,
When instructing the parallel transfer, a plurality of bit signals including a least significant bit signal among the address signals instructing storage addresses of the signals to be transferred in parallel are transferred through the second signal path, and the plurality of bit signals Transferring the address signal except for the first signal path ,
Performing the signal transfer in parallel transfer via the first and second signal paths in response to the parallel transfer instruction,
When the transfer direction of the signal transfer is opposite to the transfer direction of the control signal, after the control signal is transferred through one signal path of the first and second signal paths, the first and second characterized in that said control signal after the preceding to the signal transfer is started in the other signal paths of the two signal paths to have a step of performing said signal transfer is performed even parallel transfer in the signal path which is transferred The serial interface control method.

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