JP2004054709A - Bus line control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bus line control circuit capable of preventing the increase of chip size. <P>SOLUTION: The bus line control circuit is provided with a first register circuit for writing write data in accordance with a write enable signal for enabling writing operation, a first selector for selecting either one of the write data and first read data read from the first register circuit, a second register circuit for writing the write data selected by the first selector in accordance with the write enable signal, and a second selector for selecting either one of the write data or the first read data which is selected by the first selector and the second read data read from the second register circuit. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a bus line configuration for facilitating the design of a system bus line in LSI design, reducing cost and improving performance, and a bus line control circuit for controlling the bus line.
[0002]
[Prior art]
FIG. 8 is a block diagram showing a configuration of a conventional bus line control circuit 90. The bus line control circuit 90 is connected to the bus line 12. The bus line 12 is connected to a CPU (not shown) and includes an address bus 13, a control bus 14, and a data bus 15.
[0003]
The bus line control circuit 90 includes a plurality of register circuits 2. Each register circuit 2 has a plurality of flip-flops each having a CPU bus width such as 8 bits, 16 bits, or 32 bits or a bit width of about half thereof. Each register circuit 2 receives write data from the data bus 15 forming the bus line 12.
[0004]
The bus line control circuit 90 includes an address decoder 94. The address decoder 94 decodes the address signal 16 received from the address bus 13 forming the bus line 12, and generates a register selection signal 97 for selecting one of the plurality of register circuits 2.
[0005]
The bus line control circuit 90 includes a plurality of write enable signal generation circuits 95 corresponding to the respective register circuits 2. Each write enable signal generation circuit 95 outputs a write enable signal to the corresponding register circuit 2 based on the write control signal 8 received from the control bus 14 and the register selection signal 97 generated by the address decoder 94. Each register circuit 2 writes the write data received from the data bus 15 according to the write enable signal output from the corresponding write enable signal generation circuit 95. A chip select signal and a chip enable signal other than the write control signal 8 may be separately used for write control.
[0006]
The bus line control circuit 90 is provided with a plurality of read enable signal generation circuits 96 corresponding to the respective register circuits 2. Each read enable signal generation circuit 96 generates a read enable signal based on the read control signal 9 received from the control bus 14 and the register selection signal 97 generated by the address decoder 94.
[0007]
The bus line control circuit 90 includes a plurality of output circuits 93 corresponding to the respective register circuits 2. Each output circuit 93 reads out the read data from the corresponding register circuit 2 and outputs it to the output circuit 84 according to the read enable signal generated by the corresponding read enable signal generation circuit 96. The output circuit 84 outputs the read data output from the output circuit 93 corresponding to the register 2 selected by the register selection signal 97 to the data bus 15.
[0008]
As in the case of writing, a chip select signal or a chip enable signal may be used for read control. In this example, when no read data is output from any of the register circuits 2, all the signals output LOW, and a signal from another block can be selected by OR logic. As another method, there is a method of selecting an output between blocks by setting the output to Hi-Z. However, usually, a selector configuration as shown in FIG. 8 is often used to prevent an intermediate potential from being generated inside the LSI.
[0009]
The reference circuit 17 is provided in the bus line control circuit 90. The reference circuit 17 refers to data written and held in each register circuit 2.
[0010]
[Problems to be solved by the invention]
In recent years, a process for manufacturing an LSI has been miniaturized, and this has led to an increase in development cost and an increase in circuit size. Therefore, it is necessary to reduce development costs, and it is necessary to develop an LSI that covers a plurality of systems with one LSI. In addition, functional competition is intensifying, and circuits are becoming more complex and larger. As described above, large-scale and general-purpose LSIs require a larger number of register circuits than conventional LSIs, and this trend will continue in functions other than those that can be processed only by software. Think. Therefore, an effective method of using the register circuit is required.
[0011]
FIG. 9 is a schematic diagram showing an arrangement of the register circuit 2 provided in the conventional bus line control circuit 90. As shown in FIG. Each register circuit 2 is connected to the output circuit 84 in parallel with each other. Such a conventional example has a simple basic configuration and is a very good logical configuration.
[0012]
However, in the case of using a large number of registers, there arises a problem that the use of the conventional technique requires a large amount of wiring resources in the placement and wiring of the LSI. In addition, there is a problem that wiring concentration occurs in the placement and wiring of the LSI.
[0013]
FIG. 9 shows an arrangement image at that time as an example when there are nine registers. This figure shows that the output circuit 84 selects the read data output from each of the register circuits 2 indicated by oblique lines.
[0014]
The read data shown in FIG. 9 is actually transmitted through a wiring composed of a plurality of bits. This wiring is configured to cover the entire bus line control circuit 90. In such a configuration, the length of the wiring for connecting each register circuit 2 and the output circuit 84 becomes long, so that the wiring efficiency is poor.
[0015]
With such a wiring arrangement, the input / output lines of each register circuit 2 occupy a large proportion of the wiring resources in the block of the LSI. In this example, each register circuit 2 has nine registers. However, in practice, there are many register circuits 2 in many cases. As the number of register circuits 2 increases, wiring resources are further consumed. When the wiring resources are consumed in this way, the wiring efficiency in the block decreases. As a result, there is a problem that the chip size increases.
[0016]
In addition to the above-mentioned problem, since final output signals are collected in the output circuit 84, the wiring density around the output circuit 84 becomes higher than the wiring density in other parts. Therefore, wiring resources to the periphery of the output circuit 84 are extremely smaller than wiring resources to other parts. Therefore, there is a problem that the wiring efficiency to the peripheral circuit is remarkably reduced, and this also eventually causes an increase in chip size.
[0017]
The present invention has been made to solve such a problem, and an object of the present invention is to provide a bus line control circuit capable of preventing an increase in chip size.
[0018]
[Means for Solving the Problems]
A bus line control circuit according to the present invention includes a first register circuit for writing write data supplied from a bus line in response to a write enable signal for enabling a write operation, and a read circuit for enabling a read operation. A first selector that selects one of the write data supplied from the bus line and first read data read from the first register circuit in response to an enable signal; A second register circuit for writing the write data selected by the first selector, and one of the write data and the first read data selected by the first selector in response to the read enable signal; 2nd read data read from the 2 register circuit Characterized by comprising a second selector for selecting one of.
[0019]
Another bus line control circuit according to the present invention enables a first register circuit that writes write data serially supplied from a bus line in response to a write enable signal for enabling a write operation, and a read operation. A first selector that selects one of the write data serially supplied from the bus line and first read data read from the first register circuit in response to a read enable signal for performing the read operation. A second register circuit that writes one of the write data and the first read data selected by the first selector in response to a write enable signal, and a second register circuit that is selected by the first selector in response to the read enable signal Any of the written write data and the first read data And a second selector for selecting any one of the second read data read from the second register circuit, and the write data selected by the second selector and the second read data in response to the write enable signal. A third register circuit for writing any one of the read data, and any one of the first read data and the second read data selected by the second selector according to the read enable signal and the third register circuit. A shift register among the first to third registers should be configured based on a third selector for selecting any of the read third read data and an address signal supplied from the bus line. An address decoder for selecting a plurality of registers; A plurality of selectors respectively corresponding to the plurality of register circuits selected by the address decoder select each read data read from each register circuit, and the plurality of register circuits selected by the address decoder are connected to the bus by the bus. The semiconductor device operates as a shift register in response to the write enable signal so that the plurality of write data serially supplied from a line are respectively written.
[0020]
Still another bus line control circuit according to the present invention enables a first register circuit that writes write data supplied from a bus line in response to a write enable signal for enabling a write operation, and enables a read operation. A first selector for selecting one of the write data supplied from the bus line and the first read data read from the first register circuit in accordance with a read enable signal for the read operation. A second register circuit for writing either the write data selected by the first selector or the first read data, and a second register circuit selected by the first selector in response to the read enable signal. One of the write data and the first read data and the second A second selector for selecting any of the second read data read from the register circuit; and a second selector for selecting the write data and the second read data selected by the second selector in response to the write enable signal. One of the first read data and the second read data selected by the second selector in accordance with the third register circuit for writing any of the read signals and the read enable signal, and read from the third register circuit. A third selector for selecting any of the third read data, and a plurality of registers to constitute a shift register among the first register to the third register should be read / written according to a mode selection signal. Having an address decoder for selecting one of the single registers And it features.
[0021]
A circuit description data automatic generation method according to the present invention is configured to enable a first register circuit for writing write data supplied from a bus line in response to a write enable signal for enabling a write operation, and to enable a read operation. A first selector configured to select one of the write data supplied from the bus line and the first read data read from the first register circuit in accordance with the read enable signal of A register unit, a second register circuit for writing the write data selected by the first selector according to the write enable signal, and the write data selected by the first selector according to the read enable signal And one of the first read data and the A second register unit constituted by a second selector for selecting any of the second read data read from the register circuit; and a first register circuit based on an address signal supplied from the bus line. Circuit description data automatic generation for automatically generating circuit description data for implementing a bus line control circuit having an address decoder for generating a register selection signal for selecting one of the second register circuits; Generating a circuit description data for forming the address decoder based on a bus interface specification of the bus line; and a connection relationship between the first register unit and the second register unit. Register map that defines the Circuit description data defining a connection relationship between the first register circuit and the first selector and the second register circuit and the second selector based on a module and circuit description data for forming the address decoder; And generating.
[0022]
The DMA circuit according to the present invention is a direct memory access (DMA) circuit connected to the bus line control circuit according to the present invention via the bus line, and includes a direct memory access (DMA) circuit provided in the bus line control circuit. Address signal supply means for supplying the address signal via the bus line; reading the write data from a memory connected to the bus line; and providing the bus to the first register circuit provided in the bus line control device. Write data supply means for supplying the write data via a line.
[0023]
The download circuit according to the present invention includes: an address signal download unit that directly downloads the address signal to the address decoder provided in the bus line control circuit according to the present invention; And write data download means for directly downloading the write data to the first register circuit provided in the first register circuit.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
In the bus line control circuit according to the present invention, the first register circuit for writing the write data supplied from the bus line, and the write data supplied from the bus line and the first read data read from the first register circuit. , A second register circuit for writing the write data selected by the first selector, and a second register circuit for selecting one of the write data and the first read data selected by the first selector. A second selector for selecting one of the read second read data. Therefore, the register unit formed by the first register circuit and the first selector and the register unit formed by the second register circuit and the second selector are serially connected. The total wiring length of input / output data lines for inputting / outputting data is shorter than the total wiring length in the conventional configuration in which each register unit is connected in parallel. Therefore, consumption of wiring resources for arranging the input / output data lines is suppressed. As a result, it is possible to prevent an increase in chip size in the LSI configuring the bus line control circuit.
[0025]
It is preferable to further include an address decoder that generates a register selection signal for selecting one of the first register circuit and the second register circuit based on an address signal supplied from the bus line.
[0026]
The bus line preferably has an address bus provided for supplying the address signal to the address decoder.
[0027]
A write enable signal generation circuit that generates the write enable signal based on a write control signal supplied from the bus line and the address selection signal generated by the address decoder; and a read control signal supplied from the bus line. Preferably, the apparatus further comprises a read enable signal generation circuit that generates the read enable signal based on the address selection signal generated by the address decoder.
[0028]
The bus line preferably has a control bus provided to supply the write control signal and the read control signal to the write enable signal generation circuit and the read enable signal generation circuit, respectively.
[0029]
A third register circuit that writes the write data selected by the second selector according to the write enable signal;
In accordance with the read enable signal, select one of the first read data and the second read data selected by the second selector and the third read data read from the third register circuit. The bus line control circuit according to claim 1, further comprising a third selector that performs the operation.
[0030]
It is preferable that the third selector outputs any one of the selected first read data, the second read data, and the third read data to the bus line.
[0031]
The bus line preferably has a data bus provided for receiving any of the first read data, the second read data, and the third read data output from the third selector. .
[0032]
It is preferable that the bus line has a data bus provided to supply the write data to the first register and the first selector.
[0033]
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0034]
(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of the bus line control circuit 100 according to the first embodiment. The bus line control circuit 100 is connected to the bus line 12. The bus line 12 is connected to a CPU (not shown) and includes an address bus 13, a control bus 14, and a data bus 15.
[0035]
The bus line control circuit 100 includes a plurality of register units 1 arranged at predetermined intervals along a direction parallel to the bus line 12. Each register unit 1 is provided with a register circuit 2 and a selector 3. Each register circuit 2 has a plurality of flip-flops each having a CPU bus width of 8 bits, 16 bits, 32 bits, or the like or a bit width of about half thereof.
[0036]
The bus line control circuit 100 includes an address decoder 4. The address decoder 4 decodes the address signal 16 received from the address bus 13 forming the bus line 12, and generates a register selection signal 7 for selecting one of the plurality of register circuits 2.
[0037]
The bus line control circuit 100 includes a write enable signal generation circuit 5 corresponding to each register circuit 2. Each write enable signal generation circuit 5 corresponds to a write enable signal 10 for enabling a write operation based on a write control signal 8 received from the control bus 14 and a register selection signal 7 generated by the address decoder 4. To each of the register circuits 2.
[0038]
The bus line control circuit 100 is provided with a read enable signal generation circuit 6 corresponding to each register circuit 2. Each read enable signal generation circuit 6 generates a read enable signal 11 for enabling a read operation based on the read control signal 9 received from the control bus 14 and the register selection signal 7 generated by the address decoder 4. Generate.
[0039]
The register circuit 2 and the selector 3 provided in the register unit 1 disposed at one end of the plurality of register units 1 receive write data from the data bus 15 configuring the bus line 12, respectively. The register circuit 2 writes the write data received from the data bus 15 according to the write enable signal 10 generated by the corresponding write enable signal generation circuit 5.
[0040]
The selector 3 provided in the register unit 1 disposed at one end receives the write data received from the data bus 15 forming the bus line 12 in accordance with the read enable signal 11 generated by the corresponding read enable signal generation circuit 6. And the read data read from the corresponding register circuit 2 are selected and output to the register circuit 2 and the selector 3 provided in the register unit 1 arranged next.
[0041]
The register circuit 2 provided in the register unit 1 disposed next to the selector unit provided in the register unit 1 disposed at one end in response to the write enable signal 10 generated by the corresponding write enable signal generation circuit 5. 3 is written.
[0042]
The selector 3 provided in the register unit 1 disposed at one end is provided in response to the read enable signal 11 generated by the corresponding read enable signal generation circuit 6. And the read data read from the register circuit 2 and the read data read from the corresponding register circuit 2 are selected, and the register unit 1 disposed next to the selected write data and the read data read from the corresponding register circuit 2 is selected. To the register circuit 2 and the selector 3 provided in the circuit.
[0043]
A register circuit 2 provided in a register unit 1 disposed at the other end of the plurality of register units 1 receives write data selected by a selector 3 provided in an adjacent register unit 1, and receives a corresponding write enable signal. The received write data is written according to the write enable signal 10 generated by the generation circuit 5.
[0044]
The selector 3 provided in the register unit 1 disposed at the other end is selected by the selector 3 provided in the adjacent register unit 1 in accordance with the read enable signal 11 generated by the corresponding read enable signal generation circuit 6. One of the read data read and the read data read from the corresponding register circuit 2 is selected and output to the data bus 15 constituting the bus line 12.
[0045]
FIG. 2 is a schematic diagram showing an arrangement of the register unit 1 provided in the bus line control circuit 100. Each register unit 1 constituted by the register circuit 2 and the selector 3 is serially connected to a data bus 15.
[0046]
The bus line control circuit 100 includes a reference circuit 17. The reference circuit 17 refers to data written and held in each register circuit 2.
[0047]
The operation of the bus line control circuit 100 thus configured will be described. First, the i-th (i is an integer greater than 1 and smaller than n) from one end of n (n is an integer of 3 or more) register units 1 arranged along a direction parallel to the bus line 12. The operation of writing the write data to the register circuit 2 provided in the register unit 1 arranged in the first embodiment will be described.
[0048]
First, the address decoder 4 decodes the address signal 16 received from the address bus 13 forming the bus line 12, and selects a register selection signal that selects the i-th register circuit 2 from one end of the plurality of register circuits 2. 7 is generated.
[0049]
The write enable signal generation circuit 5 arranged i-th from one end of each write enable signal generation circuit 5 receives from the control bus 14 a register selection signal 7 for selecting the register circuit 2 arranged i-th from one end. Based on the write control signal 8, a write enable signal 10 for enabling a write operation is output to the register circuit 2 arranged i-th.
[0050]
The selector 3 provided in the register unit 1 disposed at one end selects write data received from the data bus 15 forming the bus line 12. The selector 3 provided in the second register unit 1 selects the write data selected by the selector 3 provided in the register unit 1 provided at one end.
[0051]
In this way, the write data supplied from the data bus 15 to the register unit 1 disposed at one end bypasses the register unit 1 disposed at one end to the register unit 1 disposed at the (i−1) -th position.
[0052]
According to the write enable signal 10 output from the write enable signal generation circuit 5, the register circuit 2 arranged at the i-th position ranges from the register unit 1 disposed at one end to the register unit 1 disposed at the (i−1) th position Write write data that bypasses.
[0053]
Next, an operation of reading read data from the register circuit 2 provided in the i-th register unit 1 will be described.
[0054]
First, the address decoder 4 decodes the address signal 16 received from the address bus 13 forming the bus line 12, and selects a register selection signal that selects the i-th register circuit 2 from one end of the plurality of register circuits 2. 7 is generated.
[0055]
The read enable signal generating circuit 6 arranged i-th from one end of each read enable signal generating circuit 6 receives from the control bus 14 a register selection signal 7 for selecting the register circuit 2 arranged i-th from one end. On the basis of the read control signal 9, a read enable signal 11 for enabling a read operation is output to the selector 3 provided in the i-th register unit 1.
[0056]
The selector 3 provided in the i-th register unit 1 reads the read data read from the i-th register circuit 2 in response to the read enable signal 11 output from the read enable signal generation circuit 6. Select data.
[0057]
The selector 3 provided in the (i + 1) th register unit 1 selects the read data selected by the selector 3 provided in the i-th register unit 1.
[0058]
In this way, the read data read from the register circuit 2 disposed at the i-th position bypasses the register units 1 disposed at the (i + 1) -th position to the register units 1 disposed at the (n-1) -th position.
[0059]
The selector 3 provided in the register unit 1 arranged in the n-th register selects the read data selected by the selector 3 provided in the register unit 1 arranged in the (n-1) th, and outputs the read data to the data bus 15. I do.
[0060]
As described above, only the selector 3 provided in the i-th register unit 1 selected by the register selection signal 7 selects the read data read from the register circuit 2 and the selectors provided in the other register units 1 3 selects the output from the selector 3 arranged immediately before, and the read data read from the register circuit 2 arranged i-th is changed from the register unit 1 arranged at the (i + 1) -th to n-1 The data is bypassed to the register unit 1 arranged at the nth position, and is output to the data bus 15 from the register unit 1 arranged at the nth position.
[0061]
The feature of this bus control circuit is that the bus control circuit has a topology in which the data input / output signals of the registers are serially connected as mixed input / output signals while maintaining the logical configuration of the bus interface. According to this feature, as described with reference to FIG. 2, it is possible to reduce the total wiring length of the data signal wiring connected to the bus. This has the effect of suppressing wiring congestion.
[0062]
As described above, according to the first embodiment, the register circuit 2 that writes the write data supplied from the bus line 12 and the write data supplied from the bus line 12 and the read data read from the register circuit 2 A selector 3 for selecting one of them, a register circuit 2 for writing the write data selected by the selector 3, and a read data read from the register circuit 2 corresponding to one of the write data and the read data selected by the selector 3 And a selector 3 for selecting any one of the above. Therefore, since each register unit 1 constituted by the register circuit 2 and the selector 3 is serially connected to each other, the total wiring length of input / output data lines for inputting / outputting data to / from each register unit 1 is reduced. , The total wiring length in the conventional configuration in which the register units 1 are connected in parallel with each other is shorter. Therefore, consumption of wiring resources for arranging the input / output data lines is suppressed. As a result, it is possible to prevent an increase in chip size in the LSI configuring the bus line control circuit.
[0063]
(Embodiment 2)
FIG. 3 is a block diagram showing a configuration of the bus line control circuit 100A according to the second embodiment. The same components as those of the bus line control circuit 100 described above with reference to FIG. 1 are denoted by the same reference numerals. Therefore, a detailed description of these components will be omitted. The difference from the bus line control circuit 100 described above is that an address decoder 4A is provided in place of the address decoder 4, and a command decoder 18, a feedback selector 19, a switch element 21, a data hold circuit 22, and a detection element 24 are further provided. The point is.
[0064]
When data transfer in units of shift registers is designated by the mode selection signal 20, the address decoder 4A outputs a start address and a burst address corresponding to the first register circuit of the burst transfer represented by the address signal 16 input from the address bus 13. Based on the transfer word length (burst length), a register selection signal 7A for selecting a plurality of register circuits 2 corresponding to addresses from the start address to an address obtained by adding the burst length to the start address is enabled (HIGH). To
[0065]
When data transfer in register units is specified by the mode selection signal 20, the address decoder 4A selects one register circuit 2 corresponding to the address specified by the address signal 16, as in the first embodiment. Register enable signal 7A is enabled (HIGH).
[0066]
When data transfer in units of shift registers is specified by the mode selection signal 20, the command decoder 18 enables (writes) both the write control signal 8 and the read control signal 9 and outputs them. When data transfer in register units is specified by the mode selection signal 20, the command decoder 18 outputs the write control signal 8 and the read control signal 9 as they are.
[0067]
The feedback selector 19 responds to the mode selection signal 20 output from the command decoder 18 with the write data from the data bus 15 and the read data output from the selector 3 provided in the register unit 1 disposed at the other end. And outputs it to the register circuit 2 and the selector 3 provided in the register unit 1 disposed at one end.
[0068]
The operation of the bus line control circuit 100A thus configured will be described. First, among the n (n is an integer of 3 or more) register units 1 arranged along the direction parallel to the bus line 12, the register 2 provided in the register unit 1 arranged third from one end is used. , K-th (k is an integer greater than 3 and less than n) transfer operation of write data to the register circuit 2 provided in the register unit 1 in shift register units.
[0069]
First, data transfer in units of shift registers is specified by the mode selection signal 20, and an address signal 16 representing the address of the register 2 provided in the third register unit 1 and the burst length k is input to the address decoder 4A. Then, the address decoder 4A enables the register selection signals 7A corresponding to the registers 2 arranged at the third position to the registers 2 arranged at the (k-1) th position.
[0070]
The command decoder 18 enables and outputs both the write control signal 8 and the read control signal 9 (LOW) because the data transfer in units of shift registers is specified by the mode selection signal 20. The write data input from 15 is selected.
[0071]
The selector 3 provided in the register unit 1 disposed at one end selects the write data received from the feedback selector 19. The selector 3 provided in the second register unit 1 selects the write data selected by the selector 3 provided in the register unit 1 provided at one end.
[0072]
In this way, the write data supplied from the feedback selector 19 to the register unit 1 arranged at one end bypasses the register unit 1 arranged at one end to the register unit 1 arranged second.
[0073]
The register circuit 2 arranged in the third register unit 1 is arranged in the second position from the first register unit 1 in accordance with the write enable signal 10 output from the corresponding write enable signal generation circuit 5. Write the write data that bypasses the register unit 1 arranged in the.
[0074]
The selector 3 arranged in the third arranged register unit 1 reads the read data read from the corresponding register circuit 2 according to the read enable signal 11 output from the corresponding read enable signal generation circuit 6. select.
[0075]
The register circuit 2 arranged in the register unit 1 arranged fourth is selected by the selector 3 arranged third according to the write enable signal 10 output from the corresponding write enable signal generation circuit 5. Write the read data.
[0076]
The selector 3 arranged in the fourth register unit 1 converts the read data read from the corresponding register circuit 2 according to the read enable signal 11 output from the corresponding read enable signal generation circuit 6. select.
[0077]
In this way, the write data that bypasses the register unit 1 arranged first to the register unit 1 arranged second is written to the register circuit 2 arranged k-th.
[0078]
The write data written in the k-th register circuit 2 is output to the data bus 15 by bypassing from the (k + 1) -th register unit 1 to the n-th register unit 1.
[0079]
As described above, the write data from the data bus 15 is provided in the third register unit 1 bypassing the first register unit 1 to the second register unit 1. Are sequentially written from the registered register circuit 2 to the register circuit 2 provided in the k-th register unit 1. For this reason, the register circuits arranged from the third to the k-th register circuits operate as shift registers connected to the data bus 15.
[0080]
Therefore, data from the write data to be written to the register circuit 2 arranged at the kth position to the write data to be written to the register circuit 2 arranged at the third position are serially input in this order from the data bus 15 to perform data transfer. Can be realized.
[0081]
Next, the operation of transferring read data from the register 2 provided in the third register unit 1 to the register circuit 2 provided in the k-th register unit 1 in shift register units will be described. .
[0082]
First, as in the case of writing, data transfer in shift register units is designated by the mode selection signal 20, and the address signal 16 representing the address of the register 2 provided in the third register unit 1 and the burst length k. Is input to the address decoder 4A, the address decoder 4A enables the register selection signals 7A corresponding to the register 2 arranged at the third position to the register 2 arranged at the (k-1) th position.
[0083]
Since the data transfer in units of shift registers is specified by the mode selection signal 20, the command decoder 18 enables both the write control signal 8 and the read control signal 9 (LOW) and outputs them. The feedback selector 19 selects the read data output from the selector 3 provided in the n-th register unit 1, and feeds back the read data to the first register unit 1.
[0084]
Then, from the register circuit 2 provided in the register unit 1 arranged third to the register circuit 2 provided in the register unit 1 arranged k-th, it operates as a shift register connected to the data bus 15. . Therefore, data from the register circuit 2 arranged at the k-th position to data at the register circuit 2 disposed at the third position are output to the data bus 15 in this order.
[0085]
At this time, in order to prevent the value of the register circuit from being rewritten by shifting the shift register, data is fed back by the feedback selector 19, and the shift circuit outputs the shift output simultaneously with the shift output and operates as the shift register. 2 to retain the original data.
[0086]
Data transfer in units of a shift register, which is a feature of the present invention, can easily realize higher-speed data transfer as compared with a conventional bus control circuit. In register-based access, the number of logic stages of the decoding circuit (from the address signal 16 to the write control signal 8 and the read control signal 9) from input of an address to selection of a register is large, resulting in a large delay, resulting in high speed. However, in shift register access, address processing is performed only at the start of transfer, so that after a shift register is configured, a data transfer path is provided only to the selector 3 provided between the register circuits 2. Logical stage. Further, since the configuration is synchronized with the shift clock, the timing design is facilitated, which is advantageous for speeding up. In particular, the effect at the time of continuous data transfer is great. In addition, since the address control is performed only at the start of the transfer, the control is relatively easy, and the power consumption is reduced because the operation amount of the address decoding is small.
[0087]
The detection element 24 determines whether data transfer is being performed in shift register units based on the write control signal 8 or the read control signal 9. When the detection element 24 determines that data transfer is not being performed in shift register units, each switch element 21 is turned on. Then, the reference circuit 17 refers to the register value of each register circuit 2. Each data hold circuit 22 holds a register value of the corresponding register circuit 2.
[0088]
When the detection element 24 determines that data transfer is being performed in shift register units, each switch element 21 is turned off. As a result, each register circuit 2 is electrically disconnected from the reference circuit 17. Each data hold circuit 22 holds a register value of each register circuit 2 before each register circuit 2 is electrically disconnected from the reference circuit 17.
[0089]
In this way, during data transfer in shift register units, the reference circuit 17 is completely disconnected from each register circuit 2 so that an invalid register value is not propagated to the reference circuit 17.
[0090]
In the second embodiment, when data transfer is performed in units of cyst registers, the safety of the bus system is ensured by preventing the reference circuit 17 that refers to the value of the register from performing an unexpected malfunction during the shift operation. Performance and reliability can be maintained.
[0091]
When performing data transfer in shift register units, the value of the register circuit 2 changes during the shift operation, and the value of the register circuit 2 at that time is invalid. Therefore, the value of the register circuit 2 at the time of data transfer in shift register units is prohibited from being used, and the reference circuit 17 referring to the value of the register circuit 2 must be designed so as not to cause a malfunction at that time. Must.
[0092]
However, control registers are frequently used in many cases to increase the flexibility of the circuit, which is complicated. Therefore, there is a high possibility that an unexpected malfunction may occur in such a data invalid period. Therefore, the register value or a control signal supplied to the other circuit is controlled so as not to affect the operation of another circuit which is referencing the register value during data transfer. One of the measures is to provide a mechanism in which the register value is not propagated during the period.
[0093]
In the second embodiment, during data transfer in shift register units, a mechanism for holding the value of the register circuit 2 before data transfer is provided so that the invalid register value does not propagate to the referenced circuit. .
[0094]
Note that the clock supplied to the reference circuit 17 may be stopped during data transfer on a resist register basis so that the reference circuit 17 does not capture invalid data.
[0095]
(Embodiment 3)
FIG. 4A is a diagram for explaining information input in the circuit description data automatic generation method according to the third embodiment, and FIG. 4B is a circuit description data automatic generation method according to the third embodiment. FIG. 3 is a diagram for explaining a bus line control circuit based on circuit description data generated in FIG.
[0096]
In the third embodiment, circuit data for manufacturing the bus line control circuits according to the first and second embodiments is automatically generated based on desired specifications.
[0097]
Input data used for automatically generating circuit data for manufacturing the bus line control circuit includes a bus interface specification 25, a register map 26, and a register unit module 27.
[0098]
The bus interface specification 25 is used to generate a circuit based on the specification of a bus architecture used in a system actually designed and the specification of a functional block including a bus control circuit, without depending on a specific bus interface. Used. In the third embodiment, based on the circuit shown in FIG. 1 described in the first embodiment, the bit width of the address signal, the bit width of the data signal, the control signal, the write control condition, and the read control condition are defined. I have. Specifically, the bit width of the address signal is 4 bits, the bit width of the data signal is 16 bits, the control signals are nwe and nre, the write control conditions are nwe = 0 and nre = 1, the read control conditions are nwe = 1 and nre = 0, and other conditions define contents such as no operation.
[0099]
The register map 26 defines and defines each register name and an address value corresponding to the register based on the specification. Also, the order for serially connecting the registers is defined.
[0100]
The register unit module 27 is a circuit data library including the register circuit 2 and the selector 3, and is a part that constitutes one unit configuration of the register unit 1 of the present invention. The configuration of the register unit module 27 includes a port to which a register input data line is input, a port to which an input / output mixed signal is output, an input port to which a write enable signal and a read enable signal are input, and a register which supplies a register value to the reference circuit 17. An output port is provided, and in the selector 3, the register input line and the register output data line are coupled to output an input / output mixed signal.
[0101]
Circuit data for manufacturing the bus line control circuit is generated by software. The bus interface specification 25 and the register map 26 define a fixed format based on a certain grammar, and the unit register module 27 is prepared in advance by circuit data (for example, a hardware description language), and A procedure for generating circuit data (for example, a hardware description language) of the bus line control circuit is programmed and implemented in software.
[0102]
As a generation procedure, circuit data of the address decoder 4 is generated according to the bus interface specification 25, and the address decoder 4, a plurality of register unit modules 27, and external ports of the bus line control circuit module are connected according to the register map 26. It becomes.
[0103]
As shown in FIG. 4B, a data input signal is input to a register unit reg0, ten register units are serially connected in the order of reg0 to reg9, and a data output signal is output from the register unit reg9. The register unit module is configured such that ten register unit modules 27 are connected in the connection order defined by the register map 26, and are connected to the address decoder 4 by desired write enable signals and read enable signals. The external port and the internal connection are generated with accurate bit precision using the bit width defined by the input information, and as a result, circuit data (for example, a hardware description language) that can be implemented as an LSI is generated.
[0104]
(Embodiment 4)
FIG. 5A is a block diagram illustrating a configuration of a DMA circuit 28 according to the fourth embodiment, and FIG. 5B is a waveform diagram illustrating an operation of the DMA circuit 28. The same components as those of the bus line control circuit 100A described above with reference to FIG. 3 are denoted by the same reference numerals. Therefore, a detailed description of these components will be omitted.
[0105]
A bus line control circuit 100A, a CPU 32, a RAM 31, and a DMA circuit 28 are connected to the bus line 12. The DMA circuit 28 includes an address signal supply circuit 29. A selector 33 is provided between the CPU 32 and the DMA circuit 28 and the address bus 13. The selector 33 selects the DMA circuit 28 during the DMA transfer, and selects the CPU 32 when the DMA transfer is not performed. The address signal supply circuit 29 supplies the address signal 16 and the control signal to the address decoder 4A (FIG. 3) provided in the bus line control circuit 100A via the selector 33 and the address bus 13.
[0106]
The DMA circuit 28 is provided with a write data supply circuit 30. The write data supply circuit 30 reads the write data from the RAM 31 connected to the data bus 15 constituting the bus line 12 and writes the read data via the data bus 15 to the first register unit 1 in the bus line control device 100A. Supply data.
[0107]
The operation of the DMA circuit 28 thus configured will be described. First, when the DMA circuit 28 is activated, the selector 33 is switched to the DMA circuit 28 side, and the DMA circuit 28 can use the bus line 12. Next, the address signal supply circuit 29 provided in the DMA circuit 28 outputs the address signal 16 and the control signal to the bus line control circuit 100A, and sets the bus line control circuit 100A to the shift register unit write mode. .
[0108]
Then, at the stage of time T1, the start address and the burst length are taken into the bus line control circuit 100A to form a shift register. Thereafter, from time T2, the write data supply circuit 30 provided in the DMA circuit 28 continues to read data from the RAM 31.
[0109]
The data read from the RAM 31 is taken into the write data supply circuit 30 provided in the DMA circuit 28, and the write data supply circuit 30 switches from the data output bus to the data input bus within the write data supply circuit 30 and outputs the data from the bus line control circuit 100A. The write data is supplied to the register unit 1 arranged first.
[0110]
Then, by performing the shift operation for the burst length, writing to the shift register can be performed, and data transfer by high-speed DMA utilizing the high speed of the shift register becomes possible.
[0111]
(Embodiment 5)
FIG. 6A is a block diagram showing the configuration of the download circuit 34 according to the fifth embodiment, and FIG. 6B is a waveform diagram for explaining the operation of the download circuit 34. The same components as those of the bus line control circuit 100A described above with reference to FIG. 3 are denoted by the same reference numerals. Therefore, a detailed description of these components will be omitted.
[0112]
A bus line control circuit 100A, a CPU 32, a ROM 38, and a download circuit 34 are connected to the bus line 12. The download circuit 34 includes an address signal download circuit 35. The address signal download circuit 35 directly downloads the address signal 16 and the control signal to the address decoder 4A (FIG. 3) provided in the bus line control circuit 100A.
[0113]
The download circuit 34 is provided with a write data download circuit 36. The write data download circuit 36 reads the write data from the ROM 38 and directly downloads the write data to the register unit 1 arranged first in the bus line control device 100A.
[0114]
The determination circuit 37 is provided in the download circuit 34. The determination circuit 37 compares the write data 40 downloaded by the write data download circuit 36 to the register unit 1 arranged first and the write data 41 output from the register unit 1 arranged n-th. It is determined whether or not the write data 40 has been normally downloaded to the register unit 1.
[0115]
A selector 39 is provided between the download circuit 34 and the bus line 12 and the bus line control circuit 100A. The selector 39 selects one of the write data download circuit 36 provided in the download circuit 34 and the data bus 15.
[0116]
The operation of the download circuit 34 thus configured will be described. First, when the download circuit 34 is activated, the selector 39 is switched to the download circuit 34 side, and the bus line control circuit 100A is disconnected from the data bus 15 and connected to the download circuit 34.
[0117]
Next, an address signal download circuit 35 provided in the download circuit 34 outputs an address signal and a control signal to the bus line control circuit 100A, and sets a write mode in units of shift registers.
[0118]
At the time T1, the start address and the burst length are taken into the bus line control circuit 100A to form the shift register, and at the same time, the write data download circuit 36 provided in the download circuit 34 starts reading from the ROM 38.
[0119]
The data read out from the ROM 38 is taken into the write data download circuit 36, and the write data download circuit 36 switches from the data output bus to the data input bus within the write data download circuit 36, and the first register of the bus line control circuit 100A. The data read from the ROM 38 is supplied to the unit 1 as write data 40. The data transfer to the shift register is completed by performing the shift operation for the burst length by the above configuration.
[0120]
The determination circuit 37 compares the write data 40 downloaded to the register unit 1 arranged first by the write data download circuit 36 with the write data 41 output from the register unit 1 arranged n-th. When the write data 40 and the write data 41 do not match, the determination circuit 37 transmits an error flag 42 to the download circuit 34.
[0121]
As described above, by providing a mechanism for returning the comparison result by the determination circuit 37 to the download circuit 34, it is possible to confirm that the download has been correctly performed. Can be realized. The procedure will be described below.
[0122]
After performing the same download operation twice and setting the register in the first download operation, the download circuit 34 monitors the error flag 42 detected by the determination circuit 37 while executing the second download. At the time of the second download, the data set at the first time is output as a shift output. Therefore, if the download is executed correctly, the write data 40 input to the register unit 1 arranged at the first time is arranged at the end. It should match the write data 41 output from the registered register unit 1. Therefore, when the error flag 42 becomes HIGH, it is determined that the download has not been correctly performed, and the download circuit 34 executes the download again.
[0123]
As described above, in order to quickly set the register circuit provided in the bus line control circuit at the time of power-on or reset, the data transfer function of the shift register unit is used to set the register circuit provided in the bus line control circuit. It has a download function of directly executing data transfer between the register circuit and the ROM 38 in which the set value of the register circuit is written in advance without control from the CPU 32. The download circuit 34 is provided on an LSI, and at the time of downloading, the download circuit 34 disconnects the bus line control circuit 100A from the bus line 12 so that the download circuit 34 and the bus line control circuit 100A are directly connected. The download circuit 34 instructs the register circuit of the bus line control circuit 100A of the present invention to transfer data in shift register units. The download circuit 34 also disconnects the ROM 38 from the bus line 12, and the download circuit 34 directly accesses the ROM 38.
[0124]
(Embodiment 6)
FIG. 7A is a block diagram schematically illustrating a configuration of a bus line control circuit 100B according to the sixth embodiment, and FIG. 7B is a waveform diagram illustrating an operation of the bus line control circuit 100B. FIG. The same components as those of the bus line control circuit 100A described above with reference to FIG. 3 are denoted by the same reference numerals. Therefore, a detailed description of these components will be omitted.
[0125]
The bus line control circuit 100B includes a determination circuit 43. The determination circuit 43 compares the write data supplied to the first arranged register unit 1 with the write data output from the last arranged register unit 1 so that the write data is arranged first. It is determined whether the data is normally supplied to the register unit 1.
[0126]
A data monitor circuit 44 is provided in the bus line control circuit 100B. The data monitor circuit 44 outputs a positive acknowledgment (ACK signal) to the bus line according to the result of the determination by the determination circuit 43.
[0127]
The operation of the bus line control circuit 100B thus configured will be described.
[0128]
First, the same data transfer is performed twice, the first data transfer writes data to the register circuit provided in the register unit 1, and then the second data transfer is performed, and while the determination result of the determination circuit 43 is The monitor circuit 44 monitors.
[0129]
At the time of the second data transfer, the write data written to the register circuit by the first data transfer is output as a shift output. Therefore, if the data transfer is correctly performed, the data is transferred to the first register unit 1 disposed. The supplied write data should match the write data output from the last arranged register unit 1.
[0130]
Therefore, if the comparison result by the determination circuit 43 does not match at the time of the second data transfer, the data monitor circuit 44 can determine that the data transfer has been normally performed, and transmits an ACK signal to the CPU to transmit the data to the CPU. Notifies that the transfer was completed successfully.
[0131]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a bus line control circuit capable of preventing an increase in chip size.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a bus line control circuit according to a first embodiment.
FIG. 2 is a schematic diagram showing an arrangement of register units provided in the bus line control circuit according to the first embodiment;
FIG. 3 is a block diagram illustrating a configuration of a bus line control circuit according to a second embodiment;
FIG. 4A is a diagram for explaining information input in a circuit description data automatic generation method according to a third embodiment;
FIG. 9B is a diagram for explaining a bus line control circuit based on circuit description data generated by the circuit description data automatic generation method according to the third embodiment.
FIG. 5A is a block diagram illustrating a configuration of a DMA circuit according to a fourth embodiment;
(B) is a waveform diagram for explaining the operation of the DMA circuit according to the fourth embodiment.
FIG. 6A is a block diagram illustrating a configuration of a download circuit according to a fifth embodiment;
(B) is a waveform diagram for explaining the operation of the download circuit according to the fifth embodiment.
FIG. 7A is a block diagram schematically illustrating a configuration of a bus line control circuit according to a sixth embodiment;
(B) is a waveform diagram for explaining an operation of the bus line control circuit according to the sixth embodiment.
FIG. 8 is a block diagram showing a configuration of a conventional bus line control circuit.
FIG. 9 is a schematic diagram showing an arrangement of register units provided in a conventional bus line control circuit.
[Explanation of symbols]
1 Register unit
2 Register circuit
3 selector
4 Address decoder
5 Write enable signal generation circuit
6 Read enable signal generation circuit
7 Register selection signal
8 Write control signal
9 Read control signal
10 Write enable signal
11 Read enable signal
12 bus lines
13 Address bus
14 Control bus
15 Data bus
16 address signal
17 Reference circuit
18 Command decoder
19 Feedback selector
20 Mode selection signal
21 Switch element
22 Data hold circuit
23 Register value
24 Detector
25 Bus interface specifications
26 Register Map
27 Register Unit Module
28 DMA circuit
29 Address signal supply circuit
30 Write data supply circuit
31 RAM
32 CPU
33 Selector
34 Download Circuit
35 Address signal download circuit
36 Write data download circuit
37 Judgment circuit
38 ROM
39 Selector

Claims (19)

A first register circuit for writing write data supplied from a bus line in response to a write enable signal for enabling a write operation;
A first selector for selecting either the write data supplied from the bus line or the first read data read from the first register circuit in accordance with a read enable signal for enabling a read operation; When,
A second register circuit that writes the write data selected by the first selector according to the write enable signal;
A second selector for selecting one of the write data and the first read data selected by the first selector and the second read data read from the second register circuit in accordance with the read enable signal; A bus line control circuit, comprising: two selectors. 2. The device according to claim 1, further comprising: an address decoder configured to generate a register selection signal for selecting one of the first register circuit and the second register circuit based on an address signal supplied from the bus line. Bus line control circuit. 3. The bus line control circuit according to claim 2, wherein the bus line has an address bus provided to supply the address signal to the address decoder. A write enable signal generation circuit that generates the write enable signal based on a write control signal supplied from the bus line and the address selection signal generated by the address decoder;
3. The bus according to claim 2, further comprising: a read enable signal generation circuit that generates the read enable signal based on a read control signal supplied from the bus line and the address selection signal generated by the address decoder. Line control circuit. 5. The bus line includes a control bus provided to supply the write control signal and the read control signal to the write enable signal generation circuit and the read enable signal generation circuit, respectively. The described bus line control circuit. A third register circuit that writes the write data selected by the second selector according to the write enable signal;
In accordance with the read enable signal, select one of the first read data and the second read data selected by the second selector and the third read data read from the third register circuit. The bus line control circuit according to claim 1, further comprising a third selector that performs the operation. The bus line control circuit according to claim 6, wherein the third selector outputs any one of the selected first read data, the second read data, and the third read data to the bus line. The said bus line has a data bus provided for receiving any one of the first read data, the second read data, and the third read data output from the third selector. 7. The bus line control circuit according to 7. The bus line control circuit according to claim 1, wherein the bus line has a data bus provided to supply the write data to the first register and the first selector. A first register circuit that writes write data serially supplied from a bus line according to a write enable signal for enabling a write operation;
A second selector for selecting one of the write data serially supplied from the bus line and the first read data read from the first register circuit according to a read enable signal for enabling a read operation; One selector,
A second register circuit that writes one of the write data selected by the first selector and the first read data in response to the write enable signal;
A second selector for selecting one of the write data and the first read data selected by the first selector and the second read data read from the second register circuit in accordance with the read enable signal; Two selectors,
A third register circuit that writes one of the write data and the second read data selected by the second selector according to the write enable signal;
In accordance with the read enable signal, select one of the first read data and the second read data selected by the second selector and the third read data read from the third register circuit. A third selector,
An address decoder that selects a plurality of registers to form a shift register among the first register to the third register based on an address signal supplied from the bus line;
A plurality of selectors respectively corresponding to the plurality of register circuits selected by the address decoder select each read data read from each register circuit,
The plurality of register circuits selected by the address decoder operate as a shift register according to the write enable signal so that the plurality of write data serially supplied from the bus line are respectively written. And bus line control circuit. When the first register circuit is not selected by the address decoder, the first selector selects the write data serially supplied from the bus line,
11. The bus line control circuit according to claim 10, wherein when the third register circuit is not selected by the address decoder, the third selector selects each read data selected by the second selector. The third selector selects the write data selected by the second selector,
It is determined whether the write data has been normally supplied to the first register circuit by comparing the write data supplied to the first register circuit with the write data output from the third selector. Determining means;
11. The bus line control circuit according to claim 10, further comprising: a write data monitoring unit that outputs a positive acknowledgment (ACK signal) to the bus line in accordance with a result of the determination by the determining unit. A first register circuit for writing write data supplied from a bus line in response to a write enable signal for enabling a write operation;
A first selector for selecting either the write data supplied from the bus line or the first read data read from the first register circuit in accordance with a read enable signal for enabling a read operation; When,
A second register circuit that writes one of the write data selected by the first selector and the first read data in response to the write enable signal;
A second selector for selecting one of the write data and the first read data selected by the first selector and the second read data read from the second register circuit in accordance with the read enable signal; Two selectors,
A third register circuit that writes one of the write data and the second read data selected by the second selector according to the write enable signal;
In accordance with the read enable signal, select one of the first read data and the second read data selected by the second selector and the third read data read from the third register circuit. A third selector,
An address decoder that selects one of a plurality of registers to form a shift register and a single register to read and write data among the first register to the third register in response to a mode selection signal; A bus line control circuit. The first selector selects one of the write data serially supplied from the bus line and one of the first to third read data selected by the third selector in response to the mode selection signal. 14. The bus line control circuit according to claim 13, further comprising a circuit and a feedback selector provided to said first selector. A reference circuit that refers to a value of a register provided in each of the first to third register circuits;
And a switch element that operates to electrically disconnect the first to third register circuits from the reference circuit in accordance with a write control signal and a read control signal supplied from the bus line. Item 14. The bus line control circuit according to item 13. A first register circuit for writing write data supplied from a bus line in response to a write enable signal for enabling a write operation, and a first register circuit for writing write data supplied from a bus line in response to a read enable signal for enabling a read operation A first register unit configured by a first selector that selects one of the supplied write data and first read data read from the first register circuit; and A second register circuit for writing the write data selected by the first selector; and either one of the write data and the first read data selected by the first selector and the second register circuit in response to the read enable signal. Second reading read from the register circuit And a second register unit constituted by a second selector for selecting one of the first and second register circuits based on an address signal supplied from the bus line. Circuit description data automatic generation method for automatically generating circuit description data for implementing a bus line control circuit having an address decoder that generates a register selection signal for selecting
Generating circuit description data for forming the address decoder based on a bus interface specification of the bus line;
On the basis of a register map that defines a connection relationship between the first register unit and the second register unit, a register unit module that defines a configuration of each register unit, and circuit description data for forming the address decoder. Automatically generating circuit description data defining a connection relationship between the first register circuit and the first selector and the second register circuit and the second selector. Method. A direct memory access (DMA) circuit connected to the bus line control circuit according to claim 10 via the bus line,
Address signal supply means for supplying the address signal to the address decoder provided in the bus line control circuit via the bus line;
Write data supply means for reading the write data from a memory connected to the bus line and supplying the write data to the first register circuit provided in the bus line control device via the bus line; A DMA circuit, characterized in that: Address signal download means for directly downloading the address signal to the address decoder provided in the bus line control circuit according to claim 10,
A download circuit, comprising: write data download means for reading the write data from a memory and directly downloading the write data to the first register circuit provided in the bus line control device. The third selector selects the write data selected by the second selector,
By comparing the write data downloaded to the first register circuit by the write data download unit with the write data output from the third selector, the write data is normally downloaded to the first register circuit. 20. The download circuit according to claim 18, further comprising a determination unit that determines whether or not the download has been performed.

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