JP4636005B2 - MEMORY CONTROLLER, FLASH MEMORY SYSTEM HAVING MEMORY CONTROLLER, AND FLASH MEMORY CONTROL METHOD - Google Patents

Description

  The present invention relates to a memory controller, a flash memory system including the memory controller, and a flash memory control method.

  In recent years, flash memory, which is a non-volatile storage medium, has been actively developed, and is widely used as a storage medium for information devices (host systems) such as digital cameras.

  As the data handled by such devices has increased in capacity, the storage capacity of flash memory has also increased. In order to smoothly manage the storage area of the flash memory having such a large capacity, a method of managing the storage area by dividing it into a plurality of zones has been used in recent years (see, for example, Patent Document 1).

  More specifically, the storage area of the conventional flash memory having a plurality of zones is partitioned and managed in the form shown in FIG. 3, for example.

  That is, a specific physical block address (PBA) is assigned to each physical block that is a unit of data erasing and includes a predetermined number of pages that are units of physical data reading and writing. Each physical block is classified into one of a plurality of physical zones, and a unique physical zone number (PZN) is assigned to each physical zone. In the example of FIG. 3, a total of 2048 physical blocks are assigned consecutive PBAs # 0 to # 2047, and a total of 512 physical blocks PBA # 0 to # 511 are assigned to the physical zone of PZN # 0. A total of 512 physical blocks of PBA # 512 to # 1023 belong to the physical zone of PZN # 1, a total of 512 physical blocks of PBA # 1024 to # 1535 belong to the physical zone of PZN # 2, and PBA # A total of 512 physical blocks 1536 to # 2047 belong to the physical zone of PZN # 3.

  On the other hand, the address space on the host system side is managed by an LBA (Logical Block Address) which is a serial number assigned to an area divided in units of sectors (512 bytes). Further, a group of a plurality of sectors is called a logical block, and a group of a plurality of logical blocks is called a logical zone. The serial number assigned to the logical block is called a logical block number (LBN), and the serial number assigned to the logical zone is called a logical zone number (LZN). Further, the serial number in each logical zone of the logical block included in each logical zone is called a logical zone block number (LZIBN).

  Therefore, when the number of logical blocks included in each logical zone is n, the quotient when LBN is divided by n corresponds to LZN, and the remainder corresponds to LZIBN.

  In addition, one physical zone is allocated to each logical zone, and data corresponding to each logical block included in the logical zone is written to a physical block included in the physical zone allocated to the logical zone. Further, information (hereinafter referred to as logical address information) for identifying a logical block corresponding to the data, for example, LZIBN or LBN is written in the redundant area of the physical block in which the data is written.

  Note that the correspondence between the physical block and the logical block changes every time data is written or erased. Therefore, an address conversion table is created in order to manage the correspondence between the two at each time point, and the address conversion table is updated each time the correspondence changes. When creating this address conversion table, the redundant areas of the physical blocks in the physical zone specified based on the correspondence relationship between the logical zones and the physical zones are sequentially referenced, and the logical address information written in the redundant areas is used. Based on this, an address conversion table is created.

  Here, the logical address information written in the redundant area can be an LZIBN or LBN information, and an address conversion table can be created. Generally, LZIBN with a small amount of data is redundant as logical address information. Written to the area.

  Conventionally, each logical zone has been assigned a range of logical addresses with consecutive LBAs. In the example of FIG. 3, LBA # 0 to # 15999 sectors are in the LZN # 0 logical zone, LBA # 16000 to # 31999 sectors are in the LZN # 1 logical zone, and LBA # 32000 is in the LZN # 2 logical zone. ... To # 47999, and LBA # 48000 to # 63999 are assigned to the logical zone of LZN # 3, respectively. In this example, one page of the flash memory corresponds to one sector, and each physical block is composed of 32 pages.

  An area of 16000 sectors assigned to each logical zone is managed as a logical block in units of 32 sectors in which LBAs are continuous in the logical zone. Accordingly, in other words, an area of 32 sectors with continuous LBA is used as a logical block, and 500 logical blocks with continuous LBN (LZIBN # 0 to # 499) are allocated to each logical zone. For example, the 32-sector area of LBA # 0-31 is the logical block of LBN # 0, the 32-sector area of LBA # 32-63 is the logical block of LBN # 1, and the 32-sector area of LBA # 15968-15999 Are managed as logical blocks of LBN # 499. Here, the number of sectors included in the logical block is appropriately set so that the capacities of the logical block and the physical block match. When configuring a virtual block in which a plurality of physical blocks are virtually combined, the logical block and the virtual block have the same capacity. Since each page of physical blocks stores data in LBA order, it is based on the correspondence between the logical blocks included in each logical zone and the physical blocks included in the physical zone corresponding to the logical zone. The access destination in the flash memory can be specified.

JP 2005-18490 A

  However, when a sector having consecutive LBAs is assigned to each logical zone, if data writing or rewriting concentrates on a sector in which the LBA is in a specific range (for example, a sector in which a file allocation table is stored), the LBA becomes There is a problem that writing concentrates on physical blocks included in the physical zone corresponding to the assigned logical zone, and only the deterioration (bad block formation) of the physical block included in the physical zone is extremely accelerated. In addition, the physical block in the flash memory includes a congenital defective block that is defective from the time of shipment. Furthermore, even if a physical block is a non-defective product at the time of shipment, there is a physical block (acquired defective block) that deteriorates after use and becomes a defective block. Therefore, the storage capacity allocated to each logical zone needs to be set appropriately in consideration of the number of good physical blocks included in the physical zone, the number of acquired defective blocks, and the like.

  The present invention has been made in view of the above circumstances, and it is possible to avoid the concentration of data writing in a specific area in the flash memory and to appropriately adjust the storage capacity allocated to each logical zone. And a flash memory system including the memory controller, and a flash memory control method.

  In order to achieve the above object, a memory controller of the present invention is a memory controller that controls access to a flash memory in response to an instruction from a host system, and includes a plurality of physical blocks that are erase units in the flash memory. Zone management means for managing a correspondence relationship between the collected physical zones and a logical zone in which a plurality of sectors, which are access units in the host system, are collected, and a memory for setting a range of logical addresses that allow access to the host system Corresponding to area setting means, logical address distribution means for sequentially allocating a range of logical addresses set by the storage area setting means to a plurality of logical zones in units of a predetermined number of sectors in which logical addresses are continuous. The logical zone between the logical zone and the physical zone in relation Characterized in that it comprises an address management means for managing a correspondence relationship between the logical address and the physical address in the physical zones in over emissions.

  Preferably, the storage area setting means sets the logical address range based on the number of defective blocks in the physical zone that contains the most defective blocks.

  It is preferable that the number of the plurality of logical zones and the predetermined sector number unit are both values given as powers of 2.

  In order to achieve the above object, a flash memory system of the present invention includes the memory controller and a flash memory.

  In order to achieve the above object, a flash memory control method according to the present invention includes a physical zone in which a plurality of physical blocks, which are erase units in a flash memory, are collected in a logical zone in which a plurality of sectors, which are access units in a host system, are collected. And a storage area setting step for setting a range of logical addresses that allow access to the host system, and the storage area setting. A logical address distribution step of sequentially allocating a range of logical addresses set in the step in units of a predetermined number of sectors in which logical addresses are continuous with respect to a plurality of the logical zones; and logical addresses allocated to the logical zones, Physical zone assigned to the logical zone Characterized in that it comprises an address conversion step of converting the physical address of the inner.

  In the storage area setting step, it is preferable that the range of the logical address is set based on the number of defective blocks in the physical zone that contains the most defective blocks.

  According to the present invention, in a flash memory system in which a physical zone configured by a plurality of physical blocks is allocated to a logical zone configured by a region of a plurality of sectors, and the flash memory is accessed according to the allocation, the host system The logical address range that allows access is set, and the set logical address range (area) is sequentially allocated to a plurality of logical zones in units of a predetermined number of sectors in which logical addresses are continuous. The storage capacity allocated to each logical zone can be adjusted as appropriate. In addition, by assigning logical address ranges (areas) to each logical zone in this way, access to a specific range of logical addresses can be distributed to accesses to physical blocks in a plurality of physical zones.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention. As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a controller 3 that controls the flash memory 2.

  The flash memory system 1 is connected to the host system 4 via the external bus 13. The host system 4 includes a CPU (Central Processing Unit) for controlling the entire operation of the host system 4, a companion chip for transferring information to and from the flash memory system 1, and the like. The host system 4 may be various information processing apparatuses such as a personal computer and a digital still camera that process various types of information such as characters, sounds, and image information.

  The flash memory 2 is a non-volatile memory and includes a register and a memory cell array. The flash memory 2 writes or reads data by copying data between a register and a memory cell.

  The memory cell array includes a plurality of memory cell groups and word lines. Each memory cell group includes a plurality of memory cells connected in series. The word line is for selecting a specific memory cell in the memory cell group. Data is copied between the selected memory cell and the register via the word line, that is, data is copied from the register to the selected memory cell, or data is copied from the selected memory cell to the register. .

  A memory cell constituting the memory cell array is constituted by a MOS transistor having two gates. Here, one gate is called a control gate, and the other gate is called a floating gate. Data is written or erased by injecting charges (electrons) into the floating gate or discharging charges (electrons) from the floating gate.

  Since the floating gate is surrounded by an insulator, the injected electrons are held for a long period of time. Note that, when electrons are injected into the floating gate, a high voltage at which the control gate is on the high potential side is applied between the control gate and the floating gate. Further, when electrons are discharged from the floating gate, a high voltage at which the control gate becomes a low potential side is applied between the control gate and the floating gate.

  Here, a state where electrons are injected into the floating gate is a write state, which corresponds to a logical value “0”. The state in which electrons are discharged from the floating gate is an erased state, which corresponds to a logical value “1”.

  Such an address space of the flash memory 2 is shown in FIG. The address space of the flash memory 2 is composed of “pages” and “blocks (physical blocks)”.

  A page is a processing unit in a data read operation and a data write operation performed in the flash memory 2. The physical block is a processing unit in the data erasing operation performed in the flash memory 2, and is composed of a plurality of pages.

  Although the configuration of the block and page differs depending on the specifications of the flash memory, a small block flash memory as shown in FIG. 2A and a large block flash memory as shown in FIG. Has been used. In the small block configuration, as shown in FIG. 2A, one block is composed of 32 pages (P0 to P31), and each page is composed of a 512-byte user area 25 and a 16-byte redundant area 26. Yes. In the large block configuration, as shown in FIG. 2B, one block is composed of 64 pages (P0 to P63), and each page is composed of a 2048-byte user area 25 and a 64-byte redundant area 26. Has been.

  The user area 25 is an area for storing user data supplied from the host system 4.

  The redundant area 26 is an area for recording additional data such as an error collection code, logical address information, and a block status (flag).

  The error collection code is data for detecting and correcting an error included in the data stored in the user area 25.

  The logical address information is information for specifying a logical block corresponding to the data when valid data is stored in the user area 25 of at least one page included in each physical block of the flash memory 2. It is.

  For a physical block in which valid data is not stored in the user area 25, logical address information is not stored in the redundant area 26 of the block.

  Therefore, by determining whether or not logical address information is stored in the redundant area 26, it is possible to determine whether or not valid data is stored in the physical block including the redundant area 26. . That is, when no logical address information is stored in the redundant area 26, no valid data is stored in the physical block.

  As described above, one physical block includes a plurality of pages. Data cannot be overwritten on these pages. For this reason, even when only the data stored in one page is rewritten, the data stored in all pages in the physical block including the page is changed to the physical block in which the stored data is erased ( Hereinafter referred to as an erased block.) Must be written again.

  That is, in normal data rewriting, data stored in all pages of the physical block including the page to be rewritten (both data to be rewritten and data that cannot be rewritten) is written to another erased physical block. At this time, the rewritten data is written for the data to be rewritten, and the previously stored data is rewritten as it is for the data that is not rewritten.

  In the data rewriting as described above, the correspondence relationship between the logical block address and the physical block address changes before and after the rewriting. That is, the correspondence relationship between the logical block address and the physical block address changes every time data stored in the flash memory 2 is rewritten.

  Therefore, it is necessary to manage the correspondence between the logical block and the physical block, and this correspondence is usually managed by the address conversion table. This address conversion table is created based on logical address information (LZIBN or LBN) stored in the redundant area 26 of the first page of each physical block.

  The block status (flag) is a flag indicating whether the block is good or bad. A block in which data cannot be normally written is determined as a defective block, and a block status (flag) indicating a defective block is written in the redundant area 26.

  Such a flash memory 2 receives data, address information, internal commands, and the like from the controller 3 and performs various processes such as a data read process, a write process, a block erase process, and a transfer process.

  As shown in FIG. 1, the controller 3 includes a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, an ECC (error collection code) block 11, ROM (Read Only Memory) 12. The controller 3 constituted by these functional blocks is integrated on one semiconductor chip. Each functional block will be described below.

  The microprocessor 6 controls the overall operation of the controller 3 in accordance with a program stored in the ROM 12. For example, the microprocessor 6 reads a command set (sequence command) defining various processes from the ROM 12, supplies the command set to the flash memory interface block 10, and causes the flash memory interface block 10 to execute processes.

  The host interface block 7 exchanges data, address information, status information, external commands and the like with the host system 4 via the external bus 13. Data or the like supplied from the host system 4 to the flash memory system 1 is taken into the flash memory system 1 (for example, the buffer 9) using the host interface block 7 as an entrance. Data supplied from the flash memory system 1 to the host system 4 is supplied to the host system 4 through the host interface block 7 as an exit.

  A work area 8 shown in FIG. 1 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and includes a plurality of SRAM (Static Random Access Memory) cells. The work area 8 stores, for example, an address conversion table for converting a logical address and a physical address, an empty block search table for searching for an empty block, and the like.

  The buffer 9 temporarily stores data read from the flash memory 2 and data to be written to the flash memory 2. That is, data read from the flash memory 2 is held in the buffer 9 until the host system 4 can receive the data, and data to be written to the flash memory 2 is stored until the flash memory 2 becomes writable. It is held in the buffer 9.

  The flash memory interface block 10 exchanges data, address information, status information, internal commands, and the like with the flash memory 2 via the internal bus 14.

  The ECC block 11 generates an error correction code added to data to be written to the flash memory 2 and detects and corrects an error included in the read data based on the error correction code added to the read data.

  The ROM 12 is a non-volatile storage element that stores a program that defines a processing procedure performed by the microprocessor 6. Specifically, the ROM 12 stores a program that defines a processing procedure such as creation of an address conversion table, for example.

  Next, the configuration of the logical zone in the flash memory system according to the present invention will be described. In the flash memory system 1 according to the present invention, a range (area) of logical addresses that allows access from the host system side is set, and the set range (area) of logical addresses is assigned to each logical zone. First, the allocation of the range (area) of logical addresses will be described.

  In the present embodiment, as shown in FIG. 4B, the logical address range (area) by LBA is divided into LZN # 0 to # 3 in units of 4 sectors where logical addresses are continuous (LBA is continuous). The four logical zones are allocated sequentially. By assigning logical address ranges (areas) to each logical zone in this way, access to a specific range of LBAs is distributed to access to physical blocks in a plurality of physical zones. For example, when access is concentrated in a range of 16 sectors in which LBAs are continuous, the access is distributed to access to physical blocks in four physical zones allocated to each logical zone of LZN # 0 to # 3. .

If the number of logical zones to be distributed and the number of sectors in the distribution unit are powers of 2, the logical zone to be distributed can be determined from specific bits of the LBA. That is, the number is 2 ^p number of logical zones assignment destination, if the number of sectors sorting unit is 2 ^q sectors, a logical zone assignment destination from bits counted from the lower side of the LBA from q + 1 bit to p + q-th bit Can be determined.

As shown in FIG. 4B, when the number of logical zones to be distributed is 4 (2 ² ) and the number of sectors in the distribution unit is 4 (2 ² ), as shown in FIG. In addition, it is possible to determine the LZN of the logical zone as the distribution destination based on the 2-bit values (0 to 3) up to the third and fourth bits counted from the lower side of the LBA. Hereinafter, a bit for determining LZN is referred to as an LZN determination bit. In FIG. 4A, the LBA is represented by 16 bits in order to explain the distribution of the range of LBA # 0 to # 63999.

In the example shown in FIG. 4A, when LBA # 0 to # 3, the LZN discrimination bit (the fourth and third bits counted from the lower side of the LBA) is “00” in binary notation, and LBA # The LZN discrimination bit is “01” in binary notation when 4 to # 7, the LZN discrimination bit is “10” in binary notation when LBA # 8 to # 11, and the LZN discrimination when LBA # 12 to # 15. The bit is “11” in binary notation. That is, the value of the LZN discrimination bit (the fourth and third bits counted from the lower side of the LBA) corresponds to the distribution destination LZN. In addition, the areas of the logical addresses distributed to each logical zone are collected for each predetermined number of sectors, and the combined areas of the predetermined number of sectors are handled as logical blocks. Here, the minus the LZN discriminating bit from LBA LBA lower 'and the number of sectors areas included in each logical block when a 2 ^r sectors, LZIBN of logic blocks included in each logical zone LBA' Corresponds to upper bits excluding r bits. That is, when each logical block is composed of 32 (2 ⁵ ) sector areas, the upper 9 bits excluding the lower 5 bits of LBA ′ correspond to the LZIBN of the logical block included in each logical zone.

  On the other hand, when an area of 16000 sectors with continuous LBA is allocated to logical zones of LZN # 0 to # 3 as in the prior art, the upper 11 bits excluding the lower 5 bits of LBA are assigned to the LBN of each logical block. Correspond. The quotient obtained by dividing this LBN by the number of logical blocks included in the logical zone corresponds to LZN, and the remainder corresponds to LZIBN.

  Also, as shown in FIG. 4B, the logical address range (area) by LBA is divided into four logical units LZN # 0 to # 3 in units of four sectors where logical addresses are continuous (LBA is continuous). When sequentially assigned to zones, each logical block is composed of four consecutive 32-sector areas. For example, as shown in FIG. 5, the logical blocks of LZIBN # 0 in the logical zone of LZN # 0 are LBA = # 0 to # 3, # 16 to # 19, # 32 to # 35, # 48 to # 51, It consists of 32 sector areas # 64 to # 67, # 80 to # 83, # 96 to # 99, and # 112 to # 115. This logical block is associated with one of the physical blocks included in the physical zone of PZN # 0 of the flash memory 2.

  Similarly, the logical blocks of LZIBN # 0 in the logical zone of LZN # 1 are LBA = # 4 to # 7, # 20 to # 23, # 36 to # 39, # 52 to # 55, # 68 to # 71, It is composed of 32 sector areas # 84 to # 87, # 100 to # 103, and # 116 to # 119. This logical block is associated with one of the physical blocks included in the physical zone of PZN # 1 of the flash memory 2.

  In the above-described embodiment, the range (area) of logical addresses that allow access from the host system side is allocated in units of 4 sectors in which LBAs are continuous. If this allocation unit is set appropriately, the LBA can be specified. Even when access is concentrated on a certain area (for example, an area in which FAT (file allocation table) is written), access to the specific area can be distributed to a plurality of logical zones. By performing such distribution, access to a specific area of the LBA is distributed to access to physical blocks in a plurality of physical zones. Note that the number of sectors in the allocation unit can be arbitrarily set as long as the number of sectors is less than the total number of sectors included in the logical zone.

Here, when the number of logical zones to be distributed is 4 (2 ² ) and the number of sectors in the distribution unit is 8 (2 ³ ), the number of logical zones to be distributed is 32 (2 ⁵ ). A case where the number of sector units is 256 (2 ⁸ ) sectors will be described.

FIG. 6B shows a case where 4 (2 ² ) logical zones are allocated in units of 8 (2 ³ ) sectors. In this case, as shown in FIG. 6A, the 4th to 5th bits counted from the lower side of the LBA are LZN determination bits. That, p = 2, since q = 3 and the a distribution of ^{2 q} sectors for ^{2 p} number of logical zones case, counted from the lower side of the LBA 4 (q + 1) from the bit 5 (p + q) to bit The logical zone of the distribution destination can be determined from the bit.

FIG. 7 (b) shows a case where 256 (2 ⁸ ) sectors are allocated to 32 (2 ⁵ ) logical zones. In this case, as shown in FIG. 7A, the 9th to 13th bits counted from the lower side of the LBA are LZN determination bits. In other words, since the distribution is made in units of 2 ^q sectors for 2 ^p logical zones when p = 5 and q = 8, from the 9 (q + 1) th bit to the 13 (p + q) th bit counted from the lower side of the LBA The logical zone of the distribution destination can be determined from the bits. Since each logical block is composed of an area of 32 sectors, the distribution in units of 256 (2 ⁸ ) sectors corresponds to the case where the logical blocks are allocated to each logical zone in units of 8 blocks.

  The LZIBN of the logical block included in each logical zone can be obtained by the same method as in FIG. 4A. That is, LBA ′ obtained by removing the LZN discrimination bit from LBA is obtained, and the upper bits excluding the lower 5 bits of LBA ′ correspond to the LZIBN of the logical block included in each logical zone.

  In the above description, the number of logical zones and the number of one-unit sectors allocated to the logical zones are both powers of 2. However, even if they are not powers of 2, writing concentrates in a specific area of the flash memory. You can avoid that. However, when the number of logical zones and the unit to be distributed to the logical zones are not a power of 2, LZN and LZIBN cannot be determined by specific bits of LBA.

  Next, setting of a logical address range (area) that allows access from the host system side will be described. In this embodiment, a physical zone is allocated to each logical zone, and data corresponding to the logical block included in each logical zone is written to the physical block in the physical zone allocated to the logical zone including the logical block. Yes. In rewriting processing of data stored in a physical block in such a physical zone, one or more physical blocks for rewriting processing are usually required. Therefore, the number of logical blocks included in each logical zone needs to be one or more less than the number of non-defective physical blocks included in the physical zone assigned to the logical zone.

  In addition, the physical block in the flash memory includes a congenital defective block that is defective from the time of shipment. Furthermore, even if a physical block is a non-defective product at the time of shipment, there is a physical block (acquired defective block) that deteriorates after use and becomes a defective block. Therefore, the number of logical blocks included in each logical zone must be determined in consideration of the number of good physical blocks included in the physical zone, the number of acquired defective blocks, and the like.

  For example, if the number of spare blocks in consideration of the number of acquired defective blocks is determined according to the application, the number of logical blocks to be assigned to each logical zone can be determined according to the number of spare blocks. it can. In other words, when setting the range (area) of logical addresses that are allowed to be accessed from the host system, the logical zone is assigned a number obtained by subtracting the number of spare blocks from the number of good physical blocks contained in the physical zone. The number of blocks may be used.

  The above-described logical address range (area) is equally distributed to each logical zone. That is, the areas of logical addresses assigned to each logical zone (the number of logical blocks assigned to each logical zone) are equal. Therefore, the logical address area (number of logical blocks assigned to each logical zone) assigned to each logical zone is included in the physical zone when setting the range (area) of logical addresses that are allowed to be accessed from the host system. It must be determined based on the physical zone with the least number of good physical blocks.

  For example, when the number of spare blocks is set to 8 and the number of logical blocks allocated to each logical zone is determined, the number of non-defective physical blocks included in the physical zone of PZN # 0 is 510, and the physical block of PZN # 1 The number of non-defective physical blocks included in the zone is 508, the number of non-defective physical blocks included in the physical zone of PZN # 2 is 511, and the number of non-defective physical blocks included in the physical zone of PZN # 3 is 509. If it is, the number of logical blocks allocated to each logical zone is set to 500 (= 508-8) based on the number of non-defective physical blocks included in the physical zone of PZN # 1. The area of the logical address assigned to each logical zone is an area of 16000 (= 500 × 32) sectors.

  Here, the number of non-defective physical blocks included in each physical zone is obtained by counting the number of defective blocks included in each physical zone and subtracting the number of defective blocks from the total number of physical blocks in the physical zone. it can. When counting the number of defective blocks, the physical data in which the block status (flag) indicating the defective block is written is sequentially written with reference to the block status (flag) written in the redundant area 26 of the flash memory 2. Count the number of blocks.

  Regarding the number of spare blocks, a spare block number table that defines the relationship between the number of non-defective physical blocks included in the physical zone and the number of spare blocks is set in advance. The number of blocks may be determined. Alternatively, the number of spare blocks may be determined by the ratio to the number of non-defective physical blocks included in the physical zone. For example, when the spare block ratio is 2%, the number of non-defective physical blocks included in the physical zone having the smallest number of non-defective physical blocks is multiplied by 0.98, and the decimal part is rounded down. The number of logical blocks allocated to each logical zone can be obtained. When the spare block ratio is 3%, each logical unit is calculated by multiplying the number of non-defective physical blocks in the physical zone with the smallest number of non-defective physical blocks by 0.97 and rounding down the numbers after the decimal point. The number of logical blocks allocated to the zone can be obtained.

  Next, the relationship between the range (area) of the logical address that allows access from the host system side and the area of the logical address assigned to each logical zone will be described. The range (area) of logical addresses that allow access from the host system side can be obtained by multiplying the area of logical addresses assigned to each logical zone by the number of logical zones. That is, when an area of 16000 (= 500 × 32) sectors is assigned to each of four logical zones, an area of 64000 (= 16000 × 4) sectors becomes an area that can be accessed on the host system side. If the head of this area is LBA # 0, the range (area) of logical addresses that allow access from the host system side is the area of LBN # 0 to # 63999. Therefore, when the access target area requested from the host system is outside the area of LBN # 0 to # 63999, the access processing is not performed and an error message is notified to the host system.

  When the range (area) of the logical address that allows access from the host system side is set as described above, the setting information is written in the system area in the flash memory, and the access target area from the host system side Is determined to be within the allowable range based on the setting information written in the system area. The setting information written in the system area may be information that can specify the range (area) of the logical address that allows access from the host system side. For example, the LBA at the end of the range (area) of the logical address that allows access from the host system side, or the capacity (for example, the number of sectors) of the range (area) of the logical address that allows access from the host system side There may be.

  In the above description, physical blocks having consecutive PBAs are sequentially assigned to each physical zone. However, the number of non-defective physical blocks included in each physical zone (the number of defective blocks included in each physical zone) is evenly distributed. The physical zone may be configured as follows. In this way, it can be avoided that the range (area) of logical addresses that allow access from the host system side is narrowed due to the concentration of bad blocks in a specific physical zone. As a method for equalizing the number of good physical blocks included in each physical zone (the number of defective blocks included in each physical zone), a one-to-one method as disclosed in JP-A-2005-209140 is used. A method of determining the PBA of a physical block included in each physical zone based on a table that defines the correspondence relationship, or a PBA of a physical block included in each physical zone based on a function that generates a one-to-one mapping And a method of determining the PBA of a physical block included in each physical zone based on a function that generates a map circulation such as a tent map.

  Although the present embodiment has been described with respect to a small block flash memory, the present invention can be similarly applied to a large block flash memory.

  Moreover, all the embodiment described above shows the present invention exemplarily, and does not limit the present invention, and the present invention can be implemented in other various modifications and changes. Therefore, the scope of the present invention is defined only by the claims and their equivalents.

1 is a block diagram schematically showing a flash memory system in an embodiment of the present invention. FIG. It is explanatory drawing which shows the relationship between the block and page of the flash memory in embodiment of this invention. It is a figure which shows schematically the structure of the address space of the conventional flash memory. (A) is a figure which shows an example of the data structure of LBA, (b) is a figure which shows the transition of the zone to which the page of a writing destination belongs when data is written in the order of LBA shown to (a). is there. It is a figure which shows the structural example of a logical block, and a corresponding physical block. (A) is a figure which shows another example of the data structure of LBA, (b) shows the transition of the zone to which the page of the writing destination belongs when data is written in the order of LBA shown in (a). FIG. (A) is a figure which shows another example of the data structure of LBA, (b) shows the transition of the zone to which the page of the writing destination belongs when data is written in the order of LBA shown in (a). FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Flash memory system 2 Flash memory 3 Controller 4 Host system 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 12 ROM
13 External bus 14 Internal bus 25 User area 26 Redundant area

Claims (4)

A memory controller that controls access to a flash memory in response to a command from a host system,
Zone management means for managing a correspondence relationship between a physical zone that collects a plurality of physical blocks that are erase units in the flash memory and a logical zone that collects a plurality of sectors that are access units in the host system;
Storage area setting means for setting a range of logical addresses allowing access to the host system;
Logical address distribution means for sequentially allocating a range of logical addresses set by the storage area setting means to a plurality of logical zones in units of a predetermined number of sectors in which logical addresses are continuous;
Address management means for managing the correspondence between the logical address in the logical zone and the physical address in the physical zone between the logical zone and the physical zone in a correspondence relationship;
Equipped with a,
The storage region setting means, a memory controller, characterized in that you set the range of the logical address based on a defective block number of the physical zones that contain the largest number of bad blocks. 2. The memory controller according to claim 1, wherein the number of the plurality of logical zones and the unit of the predetermined number of sectors are values given as powers of two. Flash memory system comprising: a memory controller and a flash memory according to any one of claim 1 or 2. A flash memory that allocates a physical zone that collects a plurality of physical blocks that are erase units in a flash memory to a logical zone that collects a plurality of sectors that are access units in the host system, and controls access to the flash memory according to the allocation. A control method,
A storage area setting step for setting a range of logical addresses allowing access to the host system;
A logical address distribution step of sequentially allocating a range of logical addresses set in the storage area setting step in units of a predetermined number of sectors in which logical addresses continue to the plurality of logical zones;
Said logical address assigned to the logical zone, viewed contains an address conversion step of converting into a physical address in the physical zones that are assigned to the logical zone,
The flash memory control method, wherein, in the storage area setting step, the logical address range is set based on the number of defective blocks in the physical zone that contains the most defective blocks .

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