JP4636046B2 - MEMORY CONTROLLER, FLASH MEMORY SYSTEM HAVING MEMORY CONTROLLER, AND FLASH MEMORY CONTROL METHOD - Google Patents

Description

  The present invention relates to a memory controller, a flash memory system including the memory controller, and a flash memory control method.

  Conventionally, when accessing a plurality of flash memory chips configured by physical blocks that are data erasure units that include a predetermined number of pages that are physical read / write units of data, a plurality of flash memory chips in different flash memory chips are accessed. A method of accessing by forming a virtual block obtained by virtually combining a plurality of physical blocks is known (see, for example, Patent Document 1). In the access that forms this virtual block, the physical blocks in different flash memory chips are accessed in parallel, so that the access speed is increased.

  Further, in order to smoothly manage the storage area in the flash memory chip having a large capacity, a method of managing the storage area in the flash memory chip by dividing it into a plurality of physical zones is used (for example, Patent Document 2). reference). Each physical zone is composed of a plurality of physical blocks. Each physical zone is assigned a unique physical zone number (PZN), and each physical block is assigned a unique physical block address (PBA).

  On the other hand, the address space on the host system side managed by the LBA (Logical Block Address) which is a serial number assigned to the sector (512 bytes) unit area is also divided and managed in a plurality of logical zones. The LBA is continuous in the area of a plurality of sectors included in each logical zone. Furthermore, each logical zone is managed by being divided into a plurality of logical blocks. Each logical zone is assigned a logical zone number (LZN), and each logical block is assigned a logical block number (LBN).

In this management method, a logical zone is assigned to a physical zone in a one-to-one correspondence relationship, and a physical block and a logical zone included in the physical zone are included between the corresponding physical zone and the logical zone. Correspondence with logical blocks is managed.
International Publication No. WO2002 / 046929 Pamphlet 2005-18490 gazette

  However, if data writing or rewriting concentrates in an area with a specific LBA range (for example, an area in which a file allocation table is stored), the data is written into a physical block included in the physical zone corresponding to the logical zone to which the area belongs. Concentrate. As the number of times of erasure increases, there is a high possibility that a flash memory becomes a defective block. As described above, there is a problem that a defective block is likely to occur when writing concentrates on a specific physical block.

  In view of such circumstances, the present invention increases the access speed to the flash memory using a virtual block, and avoids the concentration of access to some storage areas in the flash memory, and a control method for the memory controller I will provide a.

In order to achieve the above object, a memory controller according to the present invention controls access to a plurality of flash memories in which stored data is erased in units of physical blocks, based on logical addresses in units of sectors given from a host system. a memory controller, wherein ^{(the n} 1 or more integer) 2 n logical addresses continue by form a plurality of logical blocks including the area of the sector, the area where the logical addresses are assigned logical block A logical block forming means for dividing each area and a means for forming 2 ^m (m is an integer of 1 or more) logical zones including a plurality of the logical blocks. The logical zone is formed so that the area where the logical address continues across the block is not included. A logical zone forming means, by dividing the storage area of each of the said flash memory into a plurality of physical zone, a physical zone forming means for forming several double the physical zone including a plurality of physical blocks, Group forming means for forming a plurality of physical zone groups composed of a plurality of the physical zones each included in the different flash memory , and a logical zone for allocating one logical zone to each of the physical zone groups and assignment means, a virtual block forming means for forming a virtual block each of the physical zones from one by one selected plurality of physical blocks virtually bonds contained in the physical zone group, before Symbol logical zone belongs logical blocks, the physical zone group corresponding to the logical zone Wherein a logical block allocation means for allocating a virtual block, the logical block forming means, the upper bits formed from the upper side of bits than the bit of the n-th bit counted from the lower despite the logical address displayed in bits A logical block is formed based on the logical zone, and the logical zone forming means forms the logical zone based on the lower m bits of the upper bits .

  In addition, if the area where access is concentrated is sufficiently larger than the area included in the logical block that is the distribution unit, even if the access is concentrated in a specific area, the access is limited to the access to the physical block included in each physical zone. Distributed. Furthermore, since the capacity of the area included in the logical block is equal to the capacity of the user area included in the virtual block, the logical address of the area allocated to each virtual block is a continuous address.

  Further, since the virtual block forming means forms the virtual block, it becomes possible to access different flash memories in parallel, and the access speed is increased.

A flash memory system according to the present invention includes a plurality of flash memories in which stored data is erased in units of physical blocks, and a memory controller that controls access to these flash memories .

The flash memory control method of the present invention is a flash memory control method for controlling access to a plurality of flash memories in which stored data is erased in units of physical blocks, based on logical addresses in units of sectors given from a host system. And forming a plurality of logical blocks including areas of 2 ⁿ (n is an integer of 1 or more) sectors where the logical addresses are continuous, thereby assigning the area to which the logical address is assigned to each logical block. A logical block forming step for dividing the logical block, and a step of forming 2 ^m (m is an integer of 1 or more) logical zones including a plurality of the logical blocks , wherein each logical zone includes the logical block. The theory that the logical zone is formed so as not to include the area where the logical addresses are contiguously straddled. A management zone forming step, by dividing a storage area of each of the said flash memory into a plurality of physical zone, a physical zone forming step of forming several double the physical zone including a plurality of physical blocks, respectively Forming a plurality of physical zone groups composed of the plurality of physical zones included in the flash memories having different numbers, and assigning one logical zone to each of the physical zone groups a step, a virtual block forming step of forming a virtual blocks virtually couples the selected plurality of physical blocks one by one from each of the physical zones included in the physical zone group, belonging to the prior SL logical zone the physical zone where the logical block corresponding to the logical zone And a logical block allocating step of allocating the virtual blocks belonging to the emission group, in the logical block formation step consists of the upper bits than bits of n-th bit counted from the lower side although the logical address and bits displayed A logical block is formed based on upper bits, and in the logical zone forming step, the logical zone is formed based on lower m bits of the upper bits .

  Since the capacity of the area included in the logical block is equal to the capacity of the user area included in the virtual block, the logical address of the area allocated to each virtual block is a continuous address. In addition, if the area where access is concentrated is sufficiently larger than the area included in the logical block that is the distribution unit, even if the access is concentrated in a specific area, the access is limited to the access to the physical block included in each physical zone. Distributed. Further, since the virtual block is formed, different flash memories can be accessed in parallel, and the access speed is increased.

  According to the memory controller, the flash memory system including the memory controller, and the flash memory control method according to the present invention, the capacity of the area included in the logical block is set to be equal to the capacity of the user area included in the virtual block. In the logical block unit set as described above, an area where LBAs are continuous is distributed to each logical zone. In this way, since the areas of multiple sectors with consecutive logical addresses are distributed in units of logical blocks, if the area where access is concentrated is sufficiently larger than the area included in the logical block that is the distribution unit, the access is specified. Even if concentrated in the area, the access is distributed to accesses to physical blocks included in each physical zone. In addition, since the capacity of the area included in the logical block, which is a distribution unit, is made equal to the capacity of the user area included in the virtual block, an area where LBA continues is assigned to each virtual block, and address management is complicated. do not become. Furthermore, since the virtual block is formed, different flash memories can be accessed in parallel, and the access speed is increased.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention. As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 including two flash memory chips 2-0 and 2-1, and a memory controller 3 that controls the flash memory 2.

  The flash memory system 1 is connected to the host system 4 via the external bus 13. The host system 4 is composed of a CPU (Central Processing Unit) for controlling the entire operation of the host system 4, a companion chip for transferring information to and from the flash memory system 1, and the like. The host system 4 may be various information processing apparatuses such as a personal computer and a digital still camera that process various types of information such as characters, sounds, and image information.

  As shown in FIG. 1, the memory controller 3 includes a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, an ECC (Error Correcting Code) block 11, and a ROM. (Read Only Memory) 12. The memory controller 3 is connected to the flash memory chips 2-0 and 2-1, respectively, via internal buses 14-0 and 14-1. The memory controller 3 constituted by these functional blocks is integrated on one semiconductor chip. Hereinafter, each functional block will be described.

  The host interface block 7 exchanges data, address information, status information, external commands, etc. with the host system 4. The external command is a command for the host system 4 to instruct the flash memory system 1 to execute processing. Data or the like supplied from the host system 4 to the flash memory system 1 is taken into the flash memory system 1 (for example, the buffer 9) using the host interface block 7 as an entrance. Data supplied from the flash memory system 1 to the host system 4 is supplied to the host system 4 through the host interface block 7 as an exit.

  The work area 8 is a work area for temporarily holding data necessary for controlling the flash memory chips 2-0 and 2-1, and is composed of a plurality of SRAM (Static Random Access Memory) cells. The work area 8 stores, for example, an address conversion table showing a relationship between a logical block and a physical block (virtual block) described later, an empty block search table for searching for an empty block, and the like.

  The buffer 9 holds the data read from the flash memory chips 2-0 and 2-1, until the host system 4 can receive the data. Further, data to be written to the flash memory chips 2-0 and 2-1 is held until the flash memory chips 2-0 and 2-1 become writable.

  The flash memory interface block 10 exchanges data, address information, status information, internal commands and the like with the flash memory chips 2-0 and 2-1, via the internal buses 14-0 and 14-1. . Here, the internal command is a command for the memory controller 3 to instruct the flash memory chips 2-0 and 2-1 to execute processing, and the flash memory chips 2-0 and 2-1 Operates according to the internal command given by

  The ECC block 11 generates an error correction code for data to be written to the flash memory chips 2-0 and 2-1, and detects an error included in the read data based on the error correction code added to the read data. ·correct.

  The ROM 12 is a non-volatile storage element that stores a program that defines the procedure of processing performed by the microprocessor 6. For example, a program that defines a processing procedure such as creation of an address conversion table is stored.

  The microprocessor 6 controls the overall operation of the memory controller 3 in accordance with a program stored in the ROM 12. For example, the microprocessor 6 reads a command set defining various processes from the ROM 12 and causes the flash memory interface block 10 to execute various processes.

  The flash memory chips 2-0 and 2-1 are NAND flash memories. The NAND flash memory is a non-volatile memory and includes a register and a memory cell array in which a plurality of memory cells are two-dimensionally arranged. The memory cell array includes a plurality of memory cell groups and word lines. Here, the memory cell group is a group in which a plurality of memory cells are connected in series. Each word line is for selecting a specific memory cell in the memory cell group. Data is written or read between the selected memory cell and the register via the word line, that is, data is written from the register to the selected memory cell or data is read from the selected memory cell to the register. Done. That is, the data input to the flash memory chips 2-0 and 2-1 is written into the memory cell via the register, and the data read from the memory cell is transferred via the register to the flash memory chip 2-0, 2-1. 2-1.

  In the NAND flash memory, a data read operation and a data write operation are performed in units of pages, and a data erase operation is performed in units of blocks (physical blocks). A physical block is composed of a plurality of pages. The configuration of the physical block of the flash memory has changed as the capacity of the flash memory has increased. In the embodiment of the present invention, one page is composed of a user area of 4 sectors (2048 bytes) and a redundant area of 64 bytes, and one physical block is composed of 64 pages. Is used. Although not used in the embodiment of the present invention, one page is composed of a user area of one sector (512 bytes) and a redundant area of 16 bytes, and one physical block is composed of 32 pages. There are also known flash memories.

  The user area is an area for storing data given from the host system 4. The redundant area is an area for storing additional data such as an error correcting code (ECC), logical address information, and a block status (flag).

  The logical address information is information for specifying a logical block corresponding to a physical block in which valid data is stored in the user area. For a physical block in which valid data is not stored in the user area, logical address information is not stored in the redundant area of the block. Therefore, by determining whether or not logical address information is stored in a redundant area, it is possible to determine whether or not valid data is stored in a physical block including the redundant area. That is, when logical address information is not stored in the redundant area, it is determined that valid data is not stored in the physical block.

  The correspondence relationship between the logical block and the physical block is usually managed by an address conversion table. This address conversion table is created based on logical address information stored in the redundant area of each physical block.

  The block status (flag) is a flag indicating whether the block is good or bad. A block in which data cannot be normally written is determined as a defective block, and a block status (flag) indicating a defective block is written in the redundant area. Note that a block status (flag) indicating a defective block is written in the defective block with an initial defect before shipment.

  The address space on the host system 4 side is managed by an LBA (Logical Block Address) which is a serial number assigned to an area divided in units of sectors (512 bytes). As shown in FIG. 2, in the present embodiment, a case will be described in which an area of 4096000 sectors consisting of LBA # 0 to # 40995999 is accessed from the host system 4 side. Here, an area of 512 sectors in which the LBA is continuous is managed as a logical block, and a logical block number (LBN) is assigned to this logical block. For example, the 512 sector area of LBA # 0 to # 511 belongs to the logical block of LBN # 0, and the 512 sector area of LBA # 512 to # 1023 belongs to the logical block of LBN # 2. In this manner, 8000 logical blocks LBN # 0 to # 7999 are configured in the area of 4096000 sectors of LBA # 0 to # 40995999.

  The capacity (number of sectors) of the area belonging to each logical block is set as appropriate so as to match the capacity (number of sectors) of the user area included in one virtual block described later.

  In this embodiment, 1000 logical blocks are allocated to 8 logical zones (LZN # 0 to # 7). Here, the number of logical zones to be distributed and the number of sectors in the area included in the logical block as the distribution unit are both set to numerical values given as powers of two. The number of sectors in the area included in the logical block is set so as to match the capacity (number of sectors) of the user area included in one virtual block, so the user area included in one virtual block The virtual block is configured so that the number of sectors becomes a value given as a power of 2. That is, when the number of sectors in the user area included in one physical block is a numerical value given by a power of 2, the number of physical blocks constituting the virtual block is a numerical value given by a power of 2. By setting in this way, the allocation destination of the sector unit area included in the logical block can be determined based on the value of a part of bits when the LBA is displayed in bits (binary display).

  FIG. 3 shows an LBA of bit display (binary number display), and LBA # 0 to # 40995999 are displayed in 22 bits. The upper 13 bits of the 22-bit LBA (13 bits from the 10th bit to the 22nd bit counted from the lower side of the LBA) indicate the LBN attached to each logical block, and the lower 9 bits (counted from the lower side of the LBA) 9 bits from the 1st bit to the 9th bit) indicates a logical sector number (LSN) which is a serial number assigned to a sector unit area included in each logical block. The lower 3 bits of LBN (3 bits from the 10th bit to the 12th bit counted from the lower side of the LBA) indicate LZNs attached to 8 logical zones. In other words, the allocation destination of the sector unit area included in the logical block can be determined based on the value of the lower 3 bits of LBN (3 bits from the 10th bit to the 12th bit counted from the lower side of the LBA). it can.

The bit corresponding to LZN of the logical zone of the distribution destination is determined based on the number of logical zones of the distribution destination and the number of sectors in the area included in the logical block that is the distribution unit. For example, if the number of logical zones to be distributed is 2 ^{m and} the number of sectors in the area included in the logical block is 2 ⁿ sectors, m bits from the (n + 1) th bit to the (m + n) th bit counted from the lower side of the LBA Based on the value, the logical zone of the distribution destination is determined. Further, the LBN attached to each logical block is indicated by the upper bits of the LBA excluding the lower n bits of the LBA. The LZIBN that is the serial number of the logical block in the logical zone is indicated by the upper bits of the LBN excluding the lower m bits of the LBN (the upper bits of the LBA excluding the lower n + m bits of the LBA). In the example shown in FIG. 3, the upper bits of the LBN excluding the lower 3 bits of the LBN (the upper bits of the LBA excluding the lower 12 bits of the LBA) indicate LZIBN.

As shown in FIG. 4, each of the flash memory chips 2-0 and 2-1 has 8192 physical blocks. Hereinafter, when representing the physical zone number and physical block address in the flash memory chip 2-0, the subscript 0 is used as in PZN ₀ and PBA ₀ , and the physical zone number and physical in the flash memory chip 2-1 are used. When expressing a block address, the subscript 1 is used, such as PZN ₁ and PBA ₁ . The physical blocks in the flash memory chips 2-0 and 2-1, are assigned PBA ₀ # 0 to # 8191, PBA ₁ # 0 to # 8191, respectively. Each flash memory chip 2-0, 2-1 is divided into eight physical zones. That is, each physical zone includes 1024 physical blocks each having a continuous PBA. For example, in the flash memory chip 2-0, the physical blocks # 0 to # 1023 are included in the physical zone PZN ₀ # 0, and the physical blocks PBA ₀ # 1024 to # 2047 are the physical zone PZN ₀ # 1. include. Similarly, in the flash memory chip 2-1, the physical blocks # 0 to # 1023 are included in the physical zone of PZN ₁ # 0, and the physical blocks of PBA ₁ # 1024 to # 2047 are the physical blocks of PZN ₁ # 1. Included in the zone. A serial number assigned to a physical block in each physical zone is referred to as a physical zone block number (PZIBN). When the block number in the physical zone in the flash memory chip 2-0 is represented, the subscript 0 is used as in PZIBN ₀ , and the block number in the physical zone in the flash memory chip 2-1 is represented. Subscript 1 is used as in PZIBN ₁ .

In the physical zone in the flash memory chip 2-0 and the physical zone in the flash memory chip 2-1, physical zones in which PZN ₀ and PZN ₁ coincide with each other are associated with each other. For example, the physical zone of PZN ₀ # 0 in the flash memory chip 2-0 is associated with the physical zone of PZN ₁ # 0 in the flash memory chip 2-1, and PZN ₀ # 1 in the flash memory chip 2-0 is associated. Are associated with the physical zone of PZN ₁ # 1 in the flash memory chip 2-1.

A logical zone in which PZN (PZN ₀ and PZN ₁ ) and LZN of the physical zone coincide with each other is assigned to the physical zone associated with each other. For example, the logical zone of LZN # 0 is allocated to the physical zone of PZN ₀ # 0 in the flash memory chip 2-0 and the physical zone of PZN ₁ # 0 in the flash memory chip 2-1, and the flash memory for _PZN 1 # 1 physical zone of _PZN 0 # 1 in the physical zone and the flash memory chip 2-1 in the chip 2-0 are assigned logical zone LZN # 1.

The memory controller 3 selects one physical block from each of the two associated physical zones, and virtually combines the two selected physical blocks to form a virtual block. To this virtual block, a logical block belonging to a logical zone having a correspondence relationship with a physical zone including the physical block constituting the virtual block is assigned. FIG. 5 shows a logical block in the logical zone of LZN # 0, a physical block in the physical zone of PZN ₀ # 0 in the flash memory chip 2-0, and a physical block of PZN ₁ # 0 in the flash memory chip 2-1. It is the figure which showed the correspondence with the virtual block which combined the physical block in a zone virtually. The hatched physical block represents a physical block constituting the virtual block. For example, the logical block of LBN # 0 includes the physical block of PZIBN ₀ # 14 in the physical zone of PZN ₀ # 0 in the flash memory chip 2-0 and the physical zone of PZN ₁ # 0 in the flash memory chip 2-1. Assigned to a virtual block composed of physical blocks of PZIBN ₁ # 16. The logical block of LBN # 8 is allocated to a virtual block composed of a physical block of PZIBN ₀ # 2 and a physical block of PZIBN ₁ # 3.

The correspondence relationship between the logical block and the virtual block (physical block) is determined based on the logical address information written in the redundant area of each physical block constituting the logical block. For example, # 1 is written as logical address information in the redundant area of the physical block of PZIBN ₀ # 2 and the physical block of PZIBN ₁ # 3 allocated to the logical block of LBN # 8, that is, the logical block of LZIBN # 1. It is.

  When accessing a virtual block composed of physical blocks in the flash memory chips 2-0 and 2-1, the logical block and logical zone to which the access target area belongs are specified. Subsequently, two physical zones assigned to the logical zone are specified. Further, two physical blocks constituting a virtual block corresponding to the logical block to which the area to be accessed belongs are specified.

  Next, a description will be given of the correspondence between the 512 sector area where the LBAs belonging to each logical block are continuous and the storage areas in the two physical blocks constituting each virtual block. The 4-sector user area included in each page in the physical block is referred to as a first sector area, a second sector area, a third sector area, and a fourth sector area in order from the top.

FIG. 6 shows a storage area in a virtual block composed of a physical block of PBA ₀ # 14 of the flash memory chip 2-0 and a physical block of PBA ₁ # 16 of the flash memory chip 2-1, and the virtual block. The correspondence relationship with the 512 sector area of LSN # 0 to # 511 belonging to the assigned logical block of LBN # 0 is shown. An area having an even number of LSNs belonging to the logical block of LBN # 0 is assigned to the physical block of PBA ₀ # 14 of the flash memory chip 2-0, and the physical block of PBA ₁ # 16 of the flash memory chip 2-1 , An area having an odd LSN belonging to the logical block of LBN # 0 is allocated. In each page of page numbers (PN) # 0 to # 63 included in each physical block, the first sector area and the second sector are included in each page in the order of page numbers (in order from the smallest page number). In the order of the area, the third sector area, and the fourth sector area, areas of 256 sectors belonging to the logical block are assigned in order from the lowest LSN.

  FIG. 7 is a diagram in which the LSN attached to the 512 sector area belonging to the logical block of LBN # 0 shown in FIG. 6 is replaced with an LBA. Since the LBA of the 512-sector area belonging to the logical block is continuous, the 512-sector area where the LBA is continuous is allocated to the virtual block. The correspondence relationship between the 512 sector area of LSN # 0 to # 511 belonging to another logical block (logical block other than LBN # 0) and the storage area in the virtual block to which the logical block is assigned is also shown in FIG. This is the same as the correspondence shown in FIG. Further, in the case of other logical blocks, the correspondence between LSN and LBA is different from that in the case of the logical block of LBN # 0, but in any logical block, the LBA is continuous in the virtual block. An area of 512 sectors is allocated.

  In the flash memory, when data is rewritten, the contents of the physical block storing the data to be rewritten are transferred to another physical block for rewriting. For this reason, the number of physical blocks included in the physical zone is configured to be greater than the number of logical blocks included in the logical zone. In addition, the physical blocks in the flash memory include innate defective blocks that are defective from the time of shipment. Furthermore, even if a physical block is a non-defective product at the time of shipment, there is a physical block (acquired defective block) that deteriorates after use and becomes a defective block. Accordingly, the number of logical blocks included in each logical zone is determined in consideration of the number of good physical blocks included in the physical zone, the number of acquired defective blocks, and the like. In the present embodiment, a storage area corresponding to 1024 virtual blocks is allocated to a logical zone including 1000 logical blocks. That is, the number of physical blocks included in each physical zone is 1024.

  When writing new data to the flash memory system 1 described above, the memory controller 3 first writes the data based on the 3-bit value from the 10th bit to the 12th bit counted from the lower side of the write destination LBA. Identify the logical zone to which the previous region belongs. Next, the memory controller 3 has not written data one by one from the physical zone in the flash memory chip 2-0 and the physical zone in the flash memory chip 2-1 that have a corresponding relationship with the specified logical zone. A physical block is searched, two detected physical blocks are virtually combined to form a virtual block, and data is stored in the virtual block. In the redundant area of the first page of the two physical blocks constituting this virtual block, the LZIBN of the logical block to which the write destination area belongs (the upper bits of the LBA excluding the lower 12 bits of the LBA) is written. .

In the above-described search for empty blocks, an empty block search table describing PBA ₀ and PBA ₁ of physical blocks (excluding bad blocks) in which logical address information (LZIBN) is not stored is referred to by referring to the redundant area. It may be created in advance and a physical block constituting a virtual block may be selected using this empty block search table.

  In the embodiment of the present invention described above, an area where LBAs continue in logical block units is allocated to each logical zone. For this reason, if the area where the access is concentrated is sufficiently larger than the area included in the logical block that is the distribution unit, even if the access is concentrated in a specific area, the access is an access to the physical block included in each physical zone. To be distributed. For this reason, the probability that a defective block will occur can be reduced.

  Further, since the virtual block is configured using two physical blocks selected from each of the flash memory chips 2-0 and 2-1, it is possible to access the physical blocks in different flash memory chips in parallel. It becomes possible to increase the access speed.

  In the flash memory system 1, the memory controller 3 can determine a logical zone to which a logical block is allocated by referring to a specific bit of the LBA.

Furthermore, since the capacity (number of sectors) of the area belonging to the logical block, which is a distribution unit, is equal to the capacity (number of sectors) of the user area included in the virtual block, the LBA is continuous for each virtual block. Areas are allocated and address management is not complicated.
Next, as a comparative example, as shown in FIGS. 8 to 10, when the allocation unit is ½ of the capacity (number of sectors) of the user area included in the virtual block (the allocation unit is 256 sectors). ).

  An area of 256 sectors, which is an allocation unit, is defined as a logical group for convenience of explanation, and a group number (GN) is assigned to this logical group. That is, the 256 sector area of LBA # 0 to # 255 belongs to the logical group of GN # 0, the 256 sector area of LBA # 256 to # 511 belongs to the logical group of GN # 1, and LBA # 512 to # 767. The 256 sector area belongs to the logical group of GN # 3, and the logical group is formed similarly in the following, and is assigned a group number. These logical groups are sequentially allocated to the eight logical zones LZN # 0 to # 7. For example, the logical group of GN # 0 is allocated to the logical zone of LZN # 0, the logical group of GN # 1 is allocated to the logical zone of LZN # 1, and the logical group of GN # 2 is allocated to the logical zone of LZN # 2. Allocated.

  In the logical group allocated to each logical zone, two logical groups constitute one logical block and one logical block is allocated to one virtual block. For example, the logical groups of GN # 0, # 8, # 16, and # 24 allocated to the logical zone of LZN # 0 have one logical group consisting of two logical groups of GN # 0 and # 8. A block (logical block of LZIBN # 0) is configured, and one logical block (logical block of LZIBN # 1) is configured by a combination of logical groups of GN # 16 and # 24.

  This logical group unit distribution will be described with reference to an LBA of bit display (binary display).

  As shown in FIG. 9, the upper 14 bits of the 22-bit LBA indicate the GN assigned to the logical group that is the unit of allocation. The lower 3 bits of this GN, that is, the 10th bit counted from the lower side of the LBA 3 bits from the 12th bit to the 12th bit indicate the LZN of the logical zone of the distribution destination. Further, the upper 10 bits of GN, that is, 10 bits from the 13th bit to the 22nd bit counted from the lower side of the LBA indicate the LZIBN assigned to each logical block.

  Therefore, two logical groups in which the lower 3 bits of GN indicating LZN of the distribution destination logical zone and the upper 10 bits of GN indicating LZIBN are the same, that is, only the fourth bit counting from the lower side of GN is different. A logical group becomes one logical block. For example, a logical group of GN # 0 in which all bits indicating GN are “0” and a logical group of GN # 8 in which only the fourth bit is “1” from the lower 14 bits indicating GN are LZN #. The logical block of LZIBN # 0 in the logical zone of 0 is configured. Further, 9 bits obtained by concatenating the 12th bit counted from the lower side of the LBA and the lower 8 bits of the LBA indicate the LSN attached to the sector unit area included in the logical block.

  Even when one logical block is constituted by two logical groups allocated to each logical zone, and this one logical block is assigned to one virtual block, LSN # 0 to #SN belonging to this logical block The correspondence relationship between the 512 sector area 511 and the storage area in the virtual block to which this logical block is assigned is the same as that shown in FIG. However, in the two logical groups constituting one logical block, the LBA of the area belonging to one logical group and the LBA of the area belonging to the other logical group are continuous. Therefore, when LSN is replaced with LBA, The LBA in the area corresponding to LSN # 0 to # 255 and the LBA in the area corresponding to LSN # 256 to # 511 are not continuous.

For example, FIG. 9 shows that the logical block of LZIBN # 0 in the logical zone of LZN # 0 is replaced with the physical block of PZIBN ₀ # 14 in the physical zone of PZN ₀ # 0 in the flash memory chip 2-0 and the flash memory chip. In this example, the virtual block is assigned to a physical block of PZIBN ₁ # 16 in the physical zone of PZN ₁ # 0 in 2-1. The areas of LSN # 0 to # 255 belonging to this logical block correspond to LBA # 0 to # 255, and the areas of LSN # 256 to # 511 correspond to LBA # 2048 to # 2303. Thus, the LBA of the area corresponding to LSN # 0 to # 255 and the LBA of the area corresponding to LSN # 256 to # 511 are not continuous.

  It should be noted that the flash memory system of the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the present invention.

  For example, the number of flash memories is not limited to two, and may be a power of two. Also, the number of sectors in the logical block and the number of logical zones are not limited to eight as long as the number is the power of two. In any case, if the capacity (number of sectors) of the area belonging to the logical block and the capacity (number of sectors) of the user area of the virtual block are made the same, the area of the sector unit is allocated to each logical zone in logical block units. Good.

1 is a block diagram showing a schematic configuration of a flash memory system according to an embodiment of the present invention. It is a figure explaining the process which distributes a logical block to a logical zone. It is the figure which showed LBA which carried out bit display (binary number display). It is a figure explaining allocation of the logical zone with respect to the related physical zone. It is a figure which shows the structure of a virtual block. It is the figure which showed the correspondence of the memory area in a virtual block, and the area | region which belongs to a logical block using LSN. It is the figure which showed the correspondence of the storage area in a virtual block, and the area | region which belongs to a logical block using LBA. It is a figure explaining the distribution process in a comparative example. It is the figure which showed LBA which carried out the bit display (binary number display) in the comparative example. It is the figure which showed the correspondence of the storage area in the virtual block in a comparative example, and the area | region which belongs to a logical block using LBA.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Flash memory system 2 Flash memory 2-1 and 2-0 Flash memory chip 3 Memory controller

Claims (3)

A memory controller that controls access to a plurality of flash memories in which stored data is erased in units of physical blocks based on logical addresses in units of sectors given from a host system,
By forming a plurality of logical blocks including areas of 2 ⁿ sectors (n is an integer equal to or greater than 1) where the logical addresses are continuous, the area to which the logical addresses are assigned is divided into areas for each logical block. Logical block forming means;
A means for forming 2 ^m (m is an integer of 1 or more) logical zones including a plurality of logical blocks , and each logical zone has a region where the logical addresses are continuous across the logical blocks. Logical zone forming means for forming the logical zone so as not to be included ;
By dividing the storage area of each of the said flash memory into a plurality of physical zone, a physical zone forming means for forming several double the physical zone including a plurality of physical blocks,
Group forming means for forming a plurality of physical zone groups each consisting of a plurality of the physical zones included in the flash memory different from each other;
Logical zone assigning means for assigning one logical zone to each physical zone group ;
A virtual block forming means for forming a virtual block that combines a plurality of physical blocks which are selected one by one from each of the physical zones included in the physical zone group virtually,
A logical block belonging to the prior SL logical zones, and a logical block allocation means for allocating the virtual blocks belonging to the physical zone group corresponding to the logical zone,
The logical block forming means forms a logical block based on higher-order bits composed of bits higher than the n-th bit counted from the lower-order side of the logical address expressed in bits,
The memory controller, wherein the logical zone forming unit forms the logical zone based on lower m bits of the upper bits . A flash memory system comprising: a plurality of flash memories in which stored data is erased in units of physical blocks; and a memory controller according to claim 1 for controlling access to the flash memories. A flash memory control method for controlling access to a plurality of flash memories in which stored data is erased in physical block units, based on logical addresses in sector units given from a host system,
By forming a plurality of logical blocks including areas of 2 ⁿ sectors (n is an integer equal to or greater than 1) where the logical addresses are continuous, the area to which the logical addresses are assigned is divided into areas for each logical block. A logic block forming step;
Forming 2 ^m (m is an integer of 1 or more) logical zones including a plurality of logical blocks , each logical zone having a region where the logical addresses are continuous across the logical blocks; Forming a logical zone so as not to be included; and
By dividing the storage area of each of the said flash memory into a plurality of physical zone, a physical zone forming step of forming several double the physical zone including a plurality of physical blocks,
A group forming step of forming a plurality of physical zone groups each consisting of a plurality of the physical zones included in the flash memory different from each other ;
A logical zone assignment step for assigning one logical zone to each of the physical zone groups ;
A virtual block forming step of forming a virtual block that combines a plurality of physical blocks which are selected one by one from each of the physical zones included in the physical zone group virtually,
A logical block belonging to the prior SL logical zones, and a logical block allocation step of allocating the virtual blocks belonging to the physical zone group corresponding to the logical zone,
In the logical block forming step, a logical block is formed based on higher-order bits composed of bits higher than the n-th bit counted from the lower-order side of the logical address in bits.
In the logical zone forming step, the logical zone is formed based on lower m bits of the upper bits .

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