JP4634973B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and is particularly suitable for a nonvolatile semiconductor memory device such as a NAND cell, NOR cell, DINOR cell, and AND cell type EEPROM.

  As a kind of semiconductor memory device, an EEPROM that can be electrically rewritten is known. In particular, a NAND cell type EEPROM in which a plurality of memory cells are connected in series to form a NAND cell block has been attracting attention as being capable of high integration.

  One memory cell in the NAND cell type EEPROM has a FET-MOS structure in which a floating gate (charge storage layer) and a control gate are stacked on a semiconductor substrate via an insulating film. A plurality of memory cells are connected in series so that adjacent memory cells share a source / drain to form a NAND cell, which is connected as a unit to a bit line. Such NAND cells are arranged in a matrix to form a memory cell array. The memory cell array is usually integrated in a p-type semiconductor substrate or a p-type well region.

  The drains on one end side of the NAND cells arranged in the column direction of the memory cell array are commonly connected to the bit line via the selection gate transistors, respectively, and the source on the other end is also connected to the common source line via the selection gate transistor. Yes. The control gate electrode of the memory cell and the gate electrode of the selection gate transistor are continuously extended along the row direction of the memory cell array, and are used as a control gate line (word line) and a selection gate line.

  The operation of such a NAND cell type EEPROM is as follows. First, the data write operation is performed in order from the memory cell farthest from the bit line contact. A high voltage Vpp (about 20V) is applied to the control gate of the selected memory cell, and an intermediate potential Vmc (= about 10V) is applied to the control gate and the selection gate of the memory cell on the bit line contact side. Then, 0V or an intermediate potential Vmb (= about 8V) is applied to the bit line according to the data. When 0V is applied to the bit line, the potential is transmitted to the drain of the selected memory cell, and electrons are injected from the drain to the floating gate. As a result, the threshold voltage of the selected memory cell is shifted in the positive direction. This state is set to “1”. On the other hand, when the intermediate potential Vmb is applied to the bit line, electron injection does not occur, so the threshold voltage does not change and remains negative. This state is “0”.

  Data erasure is performed simultaneously on all the memory cells in the selected NAND cell block. That is, all the control gates in the selected NAND cell block are set to 0 V, the bit line, the source line, the p-type well region (or p-type semiconductor substrate), the control gates in the non-selected NAND cell block and all the select gates. A high voltage of about 20V is applied. As a result, electrons in the floating gate are emitted to the p-type well region (or p-type semiconductor substrate) in all the memory cells in the selected NAND cell block, and the threshold voltage is shifted in the negative direction.

  On the other hand, in the data read operation, the control gate of the selected memory cell is set to 0 V, and the control gates and select gates of the other memory cells are set to the power supply voltage Vcc to detect whether a current flows in the selected memory cell. Is done.

  Next, a memory cell array, block arrangement, NAND cell configuration, etc. in such a NAND cell type EEPROM will be described in detail.

FIG. 32 shows a block arrangement in the memory cell array in the above-described conventional NAND cell type EEPROM. In FIG. 32, all the blocks 1-0 to 1-N in the memory cell array 1 are composed of NAND cells having the same configuration (referred to as NAND-A cells). Selection gate lines SG ₁ and SG ₂ and control gate lines CG (1) to CG (8) are connected to each block 1-0 to 1 -N, respectively, and these selection gate lines SG ₁ , SG ₁ , line of the block and the NAND cell according to the supplied row address SG ₂ and the control gate line CG (1) ~CG (8) is selected.

FIG. 33 shows a detailed configuration example of a part of the memory cell array 1 shown in FIG. 32, and is an equivalent circuit diagram of the memory cell array in which NAND cells are arranged in a matrix. Each block 1-0 to 1-N in the memory cell array 1 shown in FIG. 32 corresponds to a broken line area 1-L (L = 0 to N) in FIG. Here, a NAND cell group sharing the same word line and selection gate line is called a block, and a region 1-L surrounded by a broken line in FIG. 33 is defined as one block. The drain of the select gate transistors _{S 1} of the NAND cell bit lines _{BL 1, BL 2, ...,} are connected to the BL _m, the source of the select gate transistor _{S 2} is connected to the common source line CS. Memory cells M ₁ , M ₂ ,..., M ₈ are connected in series between the source of the select gate transistor S ₁ and the drain of S ₂ . Operations such as reading and writing are usually performed by selecting _{one of} a plurality of blocks (referred to as a selection block) by the selection gate transistors S ₁ and S ₂ .

FIGS. 34 and 35 respectively show one NAND cell in the circuit shown in FIG. 33 in detail. FIGS. 34A and 34B are a pattern plan view and an equivalent circuit diagram of the NAND cell portion, and FIGS. 35A and 35B are AA ′ lines of the pattern shown in FIG. 34A, respectively. FIG. 6 is a cross-sectional configuration diagram along the line BB ′. In a p-type silicon substrate (or p-type well region) 11 surrounded by the element isolation oxide film 12, a memory cell array composed of a plurality of NAND cells is formed. In this example, eight memory cells M ₁ , M ₂ ,..., M ₈ are connected in series to one NAND cell.

Each of the memory cells M ₁ , M ₂ ,..., M ₈ has a floating gate 14 (14 ₁ , 14 ₂ ,..., 14 ₈ ) formed on the substrate 11 via a gate insulating film 13, and is insulated thereon. Control gates 16 (16 ₁ , 16 ₂ ,..., 16 ₈ ) are formed through the film 15. The n-type diffusion layers 19 (19 ₁ , 19 ₂ ,..., 19 ₉ ) which are the sources and drains of these memory cells are connected so as to be shared by adjacent ones, whereby the memory cells M ₁ , M ₂ , ..., M ₈ are connected in series.

Select gates 14 ₉ , 16 ₉ and 14 ₁₀ , 16 ₁₀ formed in the same process as the floating gate and control gate of the memory cell are provided on the drain side and the source side of the NAND cell, respectively. The selection gates 14 ₉ and 16 ₉ and 14 ₁₀ and 16 ₁₀ are electrically connected in regions not shown, and function as gate electrodes of the selection gate transistors S ₁ and S ₂ . The substrate 11 thus formed with an element is covered with a CVD oxide film (interlayer insulating film) 17, and a bit line 18 is disposed on the CVD oxide film 17. The bit line 18 is in contact with the drain-side diffusion layer 19 ₀ at one end of the NAND cell. The control gates 14 of NAND cells arranged in the row direction are commonly arranged as control gate lines CG (1), CG (2),... CG (8). These control gate lines function as word lines. The selection gates 14 ₉ , 16 ₉ and 14 ₁₀ , 16 ₁₀ are also arranged as selection gate lines SG ₁ and SG ₂ continuously in the row direction, respectively. Also, a source line wiring layer 22 is disposed between the bit line 18 and the control gate line / selection gate dedicated wiring layer, and is formed on the source side diffusion layer 19 ₁₀ (end opposite to the bit line contact) of the NAND cell. Contacted.

  Thus, conventionally, memory cells having the same dimensions and the same configuration have been formed in each block in the memory cell array.

By the way, in the memory cell array as shown in FIG. 32, since the blocks are regularly arranged, the control gate lines CG (1) to CG (8) and the selection gate lines SG ₁ and SG ₂ are arranged as a whole memory cell array. Therefore, the processing accuracy of the word lines and the like is relatively high in the blocks located in the memory cell array 1 (corresponding to the blocks 1-1 to 1- (N-1) in FIG. 32). Become. However, in particular near the outer periphery of the memory cell array 1 in the block located in the memory cell array edge (block 1-0 in FIG. 32, corresponds to block 1-N) (select gate line SG ₂ vicinity of Figure 33), the wiring pattern Therefore, the etching conditions are not uniform, and the processing accuracy is lowered.

Usually, the block at the end of the memory cell array is a non-use block in consideration of a decrease in processing accuracy. However, in this case as well, there is no sufficient countermeasure, and the selection gate in the blocks 1-0 and 1-N in FIG. disconnection of the line SG _2, or short circuit or the like occurs between the source line contact portion due to the increase of the line width of the select gate line SG _2, which has been a problem. In general, the selection gate lines SG ₁ and SG ₂ are wirings whose levels are set according to the selection / non-selection of a block. When a block is not selected, the bit line, the source line, and the NAND cell are set in a non-selected state. This eliminates the influence of non-selected blocks during operations such as writing and reading. However, when disconnection occurs, it is difficult to realize the above-described non-conduction state. In this case, leakage current from the bit line is generated, load capacity of the bit line and the source line is increased, and between the bit line and the source line. A problem such as a short circuit occurs, leading to a decrease in operation margin and malfunction. Further, even when the select gate line SG ₂ is short-circuited with the source line contact portion, the source line voltage and the select gate line SG ₂ voltage fluctuates, which leads to poor.

  The problem of the reduction in processing accuracy due to the disruption of the periodicity of the wiring pattern described above can be applied not only to the entire memory cell array but also to one NAND cell when higher accuracy is desired. Next, a decrease in processing accuracy when attention is paid to one NAND cell will be described in detail with reference to FIGS. FIGS. 36A and 36B are a pattern plan view and an equivalent circuit diagram of one NAND cell portion of the memory cell array, and FIGS. 37A and 37B are respectively A-A in FIG. It is a section lineblock diagram along a 'line and a BB' line. 36 (a), (b) and FIGS. 37 (a), (b), the same components as those in FIGS. 34 (a), (b), 35 (a), (b) are denoted by the same reference numerals. Detailed description thereof will be omitted.

Here, the line widths of the selection gate lines SG ₁ and SG ₂ in FIGS. 36A and 36B and FIGS. 37A and 37B are set to Wsg1 and Wsg2, and the control gate lines CG (1) and CG (2). ,..., CG (8) have line widths Wcg1, Wcg2,..., Wcg8, spaces between control gate lines Scg12, Scg23,..., Scg78, respectively, and spaces between control gate lines and select gate lines Ssg1, Represented by Ssg2. The NAND cells shown in FIGS. 36A, 36B, 37A, and 37B are the NAND cells shown in FIGS. 34A, 34B, 35A, and 35B. The difference is that the wiring layer 22 for the source line is not provided.

In such a NAND cell, conventionally, the aim of processing all the control gate line widths in the NAND cell is the same. That is, in FIGS. 36A and 37A, Wcg1 = Wcg2 =,..., = Wcg8. The spaces between the control gate lines are all the same, that is, Scg12 = Scg23 =,. On the other hand, the selection gate line width is larger than the control gate line width for the purpose of improving the cutoff characteristics of the selection gate transistors S ₁ and S ₂ (reducing leakage current when SG ₁ = SG ₂ = 0V). It was set to be a little thicker.

Further, while the select gate lines SG ₁ and SG ₂ is a wiring layer 14 is continuous (wiring layer 14 is connected in between the adjacent select gate transistor of the selection gate line direction), the control gate lines In CG, the wiring layer 14 is divided between the memory cells (see the hatched portion in FIG. 36A). For this reason, the spaces Ssg1 and Ssg2 may be made larger than Scg12 to Scg78 in order to reduce damage to the wiring layer 14 of the selection gate line part during processing of the wiring layer 14 of the control gate line part.

  As described above, in the conventional NAND cell, the line width and the space are periodically arranged (same dimension) between the control gate lines CG (1) to CG (8), but other than the control gate line arrangement part. In this region (corresponding to the region above the control gate line CG (1) in FIG. 36A and the region below the control gate line CG (8)), the periodicity of the wiring arrangement is broken. Therefore, compared to the control gate lines GG (2) to CG (7) in which the periodicity with the adjacent wiring is maintained, the control gate lines CG (1) and CG (8) at both ends of the CG line array portion. However, there was a problem that the machining was unstable, that is, the machining accuracy was lowered. When the processing accuracy is lowered, the line width of the control gate line adjacent to the selection gate line, that is, the channel length of the corresponding memory cell varies due to processing variations.

The biggest problem when the processing accuracy is lowered is when the line widths of the control gate lines CG (1) and CG (8) at both ends described above are narrower than intended. This will be described with reference to FIG. When the control gate line CG (1) has the target line width, as shown in FIG. 38 (a), since the cut-off characteristic of the memory cell is good, “1” data (negative charge is applied to the floating gate). When the gate voltage is 0V, no current (leakage current IL) flows in the memory cell having the state in which is injected). On the other hand, if the control gate lines CG (1) becomes thinner than aim first is because the channel length of the memory cell M ₁ is shortened, the leakage of a state to be cut-off characteristics is decreased (original off of the memory cell current order (FIG. 38 (b) refer) is increased) to state this regardless written to the data in the memory cell, i.e. regardless of the amount of charge in the floating gate 14 _1, a current flows IL always the memory cell M ₁ Thus, “0” data is always read out. Accordingly, there is a problem that normal data writing / reading cannot be performed. Similar to the case of the control gate line CG (1), the same problem occurs when the line width of the control gate line CG (8) becomes narrower than the target. In order to eliminate this problem, if all the control gate line widths are uniformly increased, a new problem arises that the memory cell size increases.

  Incidentally, in the NAND cell as described above, conventionally, a wiring structure as shown in FIGS. 39A and 39B is used to connect the control gate line and the selection gate line from the memory cell array to the row decoder. Was used. Usually, when making contact for connecting between different wiring layers, the wiring layer to be contacted is charged in an etching process such as RIE, and the absolute value of the potential of the wiring may increase. At this time, the wiring that is not connected to the pn junction does not have a current path that causes a voltage drop, and thus a high potential is maintained. At this time, the control gate line corresponding to the control gate of the memory cell is particularly problematic.

In general, in a memory cell such as a NAND-type EEPROM, the control gate line is not conventionally connected to a pn junction, and a high potential is applied during the manufacturing process. Further, when data is written or erased, a high potential difference of about 20 V is applied between the control gate line and the p-type well region. Furthermore, it is required that the tunnel current can be used to inject and emit electrons to the floating gate 100,000 times or more. As described above, the insulating film (the wiring film 16 _i (i = 1 to 8) and the wiring layer 14 _i (i = 1 to 8) between the control gate line and the p-type well region, and the wiring) A very high electric field is applied to the layer 14 _i (corresponding to an oxide film between the p-type well region) and _i (i = 1 to 8). In addition, since data is determined by the charge in the floating gate, the charge retention characteristics of the floating gate are extremely important, and leakage of charge from the floating gate due to leakage current is not allowed. Therefore, the reliability of the insulating film between the control gate line and the p-type well region is extremely important.

However, conventionally, when the control gate line and the selection gate line are connected from the memory cell array to the transistor QN in the row decoder, wiring is performed using two types of wiring layers 22 and 18 positioned above the control gate line. It was. For this reason, there were two steps (corresponding to (a) and (b) in FIG. 39A) for making contact with the wiring layer _16i as the control gate line during the manufacturing process. In this case, not only the control gate line is charged during the contact processing (A), but also the wiring layer 16 _i and the wiring layer 22 are already connected by the contact (A). The control gate line will be charged. For this reason, there is a problem in that the time during which a high voltage is applied to the control gate line is lengthened, the stress applied to the control gate line is increased, and the film quality of the oxide film is deteriorated. As a result, the reliability of data held in the memory cell is lowered, and the risk of data destruction is increased.

On the other hand, in the case of the selection gate line, in addition to the applied voltage being about 10 V at the maximum, the floating gate (wiring layer 14 _j (j = 9, 10) is continuously arranged, Since voltage is directly applied inside and outside the memory cell array), even if some stress is applied, there is no significant problem in terms of reliability.

  As described above, in the conventional semiconductor memory device such as the NAND cell type EEPROM, there is a problem that the processing accuracy of the block at the end of the memory cell array is lowered, and the operation margin is lowered and the operation failure occurs.

  Further, in a conventional semiconductor memory device such as a NAND cell type EEPROM, the processing accuracy of the control gate line adjacent to the selection gate line is lower than that of other control gate lines, and the line width becomes narrower than the target. However, there is a problem that normal data writing / reading cannot be performed. Further, if the control gate line width is uniformly increased to eliminate this problem, there is a problem that the memory cell size increases.

  Further, in a conventional semiconductor memory device such as a NAND cell type EEPROM, since the stress applied to the control gate line during the manufacturing process is large, the reliability of the insulating film around the floating gate of the memory cell is lowered, and data destruction is caused. There was a problem that the risk of getting higher.

  The present invention has been made in view of the above circumstances, and the object of the present invention is to prevent defects due to a decrease in processing accuracy of the end region of the memory cell array without increasing the chip size. Another object of the present invention is to provide a semiconductor memory device capable of realizing a chip with high operation reliability and high yield.

  Another object of the present invention is to prevent the generation of word lines with extremely narrow line widths caused by a decrease in processing accuracy due to the disruption of the periodicity of the wiring around the word lines. An object of the present invention is to provide a semiconductor memory device capable of realizing a chip with high data writing / reading reliability without causing a significant increase.

  Still another object of the present invention is to reduce the stress applied to the memory cells in the manufacturing process and to reduce the pattern area of the row decoder, and to realize an inexpensive chip with high operational reliability and yield. A semiconductor memory device is provided.

According to a first aspect of the present invention, there is provided a semiconductor memory device in which a memory cell array in which a plurality of memory cells connected to each other is arranged in an array and a gate of a selection transistor in the memory cell unit extends continuously. A selection gate line, a control gate line formed by continuously extending a gate of a memory cell in the memory cell unit, and the selection gate line and the control gate line of the memory cell array. And a plurality of the controls connected to one memory cell unit, and a row decoder for controlling the potential and a first wiring layer positioned above the wiring layer constituting the control gate line. From all the wiring layers used for connection from the memory cell array end of the first control gate line included in the gate line to the transistor in the row decoder The first wiring layer is located in an upper layer and connects the selection gate line from the memory cell array end to the transistor in the row decoder using the first wiring layer and is included in the plurality of control gate lines. The first wiring layer is positioned above all wiring layers used for connection from the memory cell array end of the second control gate line to the transistors in the row decoder, and the memory cell array end of the second control gate line A wiring connected to the first wiring layer is used for connection to the transistor in the row decoder .

According to a second aspect of the present invention, in the semiconductor memory device according to the first aspect, the first layer is located above the wiring layer that constitutes the control gate line, and is located below the first wiring layer. The second wiring layer can be directly connected to a wiring layer constituting a control gate line in the memory cell array without any other wiring layer, and the memory of the first control gate line A wiring layer used for connection from the end of the cell array to the transistor in the row decoder is formed by the second wiring layer or a wiring layer located below the second wiring layer .

According to a third aspect of the present invention, in the semiconductor memory device according to the second aspect, of the wiring length of the wiring layer used for connection from the memory cell array end of the first control gate line to the transistor in the row decoder The wiring length of the second wiring layer is the longest .

According to a fourth aspect of the present invention, in the semiconductor memory device according to any one of the first to third aspects, of the wiring length used for connecting the memory cell array of the selection gate line to the transistor in the row decoder. The wiring length of the wiring by the first wiring layer is the longest .

Further, according to a fifth aspect of the present invention, there is provided a semiconductor memory device in which a memory cell array in which a plurality of memory cell units connected to each other is arranged in an array and a gate of a selection transistor in the memory cell unit is continuous. A selection gate line formed extending in a row, a control gate line formed by continuously extending gates of memory cells in the memory cell unit, the selection gate line and the control in the memory cell array A row decoder that selects a gate line and controls a potential, and a first wiring layer positioned above a wiring layer that constitutes the control gate line, and a plurality of connected to one memory cell unit All wirings used for connection from the memory cell array end of the first control gate line included in the control gate line to the transistors in the row decoder The first wiring layer is positioned above the layer, and the selection gate line is connected from the end of the memory cell array to the transistor in the row decoder using the first wiring layer, and the plurality of control gate lines A first wiring for connecting a second control gate line included in the memory cell array end to a transistor in the row decoder is connected to a pn junction other than a source / drain of the transistor in the row decoder ; The first wiring includes the wiring of the first wiring layer .

  According to a sixth aspect of the present invention, in the semiconductor memory device according to the fifth aspect, the selection gate line is connected by a second wiring that has no connection with a pn junction other than the source / drain of the transistor in the row decoder. The memory cell array is connected to the transistors in the row decoder.

According to a seventh aspect of the present invention, in the semiconductor memory device according to the sixth aspect , the uppermost wiring layer of the wiring layers constituting the first wiring is a wiring layer constituting the second wiring. Of these, the wiring layer is the same as the uppermost wiring layer.

The semiconductor memory device according to claim 6 , wherein the uppermost wiring layer of the wiring layers constituting the first wiring is the wiring layer constituting the second wiring. Of these, the wiring layer is located below the uppermost wiring layer.

  Furthermore, as described in claim 9, in the semiconductor memory device according to any one of claims 5 to 8, the first wiring is connected to both the p-type diffusion layer and the n-type diffusion layer. It is characterized by being.

According to a tenth aspect of the present invention, in the semiconductor memory device according to any one of the fifth to ninth aspects, the first wiring layer is a wiring layer that forms a control gate line in the memory cell array. characterized in that it is a wiring layer positioned on the upper layer than can be connected directly to wiring layers without using a wiring layer.

The semiconductor memory device according to any one of claims 6 to 10, wherein the second wiring includes another wiring in a wiring layer constituting a control gate line in the memory cell array. It includes a wiring layer positioned above a wiring layer that can be directly connected without a layer interposed therebetween.

  According to a twelfth aspect of the present invention, in the semiconductor memory device according to any one of the first to tenth aspects, the memory cell unit is a NAND type EEPROM.

  According to the configuration of the first aspect, since the number of contacts with the control gate line can be reduced to one, the stress on the control gate line during the manufacturing process can be reduced, and the reliability of the insulating film around the floating gate can be improved. Can be improved. As a result, a chip having an operation with high reliability can be realized without increasing the chip size.

According to a second aspect of the present invention , the second wiring layer is provided above the wiring layer constituting the control gate line and below the first wiring layer, and the second wiring layer is a memory. The wiring layer constituting the control gate line in the cell array can be directly connected without passing through another wiring layer, and the wiring layer used for connection from the memory cell array end of the first control gate line to the transistor in the row decoder is it can be formed by a wiring layer positioned below than the second wiring layer or the second wiring layer.

According to a third aspect of the present invention, the wiring length of the wiring by the second wiring layer is the longest among the wiring length of the wiring layer used for connection from the memory cell array end of the first control gate line to the transistor in the row decoder. Preferably, among the wiring lengths used for connection from the memory cell array of the selection gate line to the transistors in the row decoder, it is preferable that the wiring length of the wiring by the first wiring layer is the longest. .

  According to the configuration of the fifth aspect, the number of times of contact with the control gate line can be reduced to one, and the current due to the pn junction for preventing the control gate from being charged to a high voltage during the contact processing step. Since the path is formed, stress on the control gate line during the manufacturing process can be reduced, and the reliability of the insulating film around the floating gate can be improved. As a result, a chip having a highly reliable operation can be realized without increasing the chip size.

  According to the sixth aspect of the present invention, even when the selection gate line is connected from the memory cell array to the transistor in the row decoder by the second wiring having no connection with the pn junction other than the source / drain of the transistor in the row decoder. A current path for preventing the control gate from being charged to a high voltage can be formed by using the source / drain regions of the transistor.

  According to a seventh aspect of the present invention, the uppermost wiring layer of the wiring layers constituting the first wiring is formed of the same wiring layer as the uppermost wiring layer of the wiring layers constituting the second wiring. For example, both wiring layers can be formed in the same manufacturing process.

  The uppermost wiring layer of the wiring layers constituting the first wiring may be a wiring layer located below the uppermost wiring layer of the wiring layers constituting the second wiring. In this case, the first wiring and the second wiring can be formed to overlap each other, and the pattern area can be reduced.

  As shown in claim 9, if the first wiring is connected to both the p-type diffusion layer and the n-type diffusion layer, when the wiring is about to be charged during contact processing between the wirings during the manufacturing process, the charging is not performed. Since a current path for discharging charges is formed for both the positive case and the negative case, the stress applied to the memory cell due to charging during the etching process can be greatly reduced. In addition, if the forward current of the pn junction is used, the amount of current is larger than that of the reverse current, and higher applied stress relaxation effect can be obtained.

As shown in claim 10, the first wiring layer is a wiring layer positioned on the upper layer than can be connected directly to wiring layers without using another wiring layer in the wiring layer constituting the control gate lines in the memory cell array Can be formed.

  According to another aspect of the present invention, the second wiring includes a wiring layer located above the wiring layer that can be directly connected to the wiring layer constituting the control gate line in the memory cell array without passing through another wiring layer. Can be configured.

  As the memory cell unit, for example, a NAND type EEPROM is suitable.

According to the present invention, it is possible to prevent a defect due to a decrease in processing accuracy of the memory cell array end region. Therefore, it is possible to obtain a semiconductor memory device capable of realizing a chip with higher operational reliability and higher yield than the conventional one without increasing the chip size.

  In addition, it is possible to prevent the occurrence of a word line having an extremely narrow line width caused by a reduction in processing accuracy due to the disruption of the periodicity of the wiring around the word line. Therefore, it is possible to obtain a semiconductor memory device capable of realizing a chip with higher data writing / reading reliability than the conventional one without causing a significant increase in chip size.

  Furthermore, the stress applied to the memory cell in the manufacturing process can be reduced, and the pattern area of the row decoder can be reduced. Therefore, it is possible to obtain a semiconductor memory device capable of realizing an inexpensive chip having higher operation reliability and yield than conventional ones.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
FIG. 1 is a diagram for explaining a semiconductor memory device according to the first embodiment of the present invention, and shows a block arrangement of a memory cell array in a NAND cell type EEPROM. In FIG. 1, NAND cells (NAND-B cells) constituting blocks 2-0 and 2-N at both ends of the memory cell array 2 and other blocks 2-1 to 2- (N-1) in the memory cell array 2 are illustrated. Have different configurations. Selection gate lines SG ₁ and SG ₂ and control gate lines CG (1) to CG (8) are connected to the blocks 2-0 to 2-N, respectively, and these selection gate lines SG ₁ , SG ₂ and A block and a row of NAND cells are selected according to the row address supplied to the control gate lines CG (1) to CG (8).

FIG. 2 is an equivalent circuit diagram of the memory cell array 2 in which NAND cells are arranged in a matrix. Here, a NAND cell group sharing the same word line or selection gate line is called a block, and a region 2-L (L = 0 to N) surrounded by a broken line in FIG. 2 is defined as one block. . This block corresponds to each block 2-0 to 2-N in FIG. Operations such as reading and writing are usually performed by selecting one of a plurality of blocks (referred to as a selected block). The drain of the select gate transistors _{S 1} of the NAND cell bit lines _{BL 1, BL 2, ...,} are connected to the BL _m, the source of the select gate transistor _{S 2} is connected to the common source line CS. Memory cells M ₁ , M ₂ ,..., M ₈ are connected in series between the source of the select gate transistor S ₁ and the drain of S ₂ .

3 and 4 are respectively for explaining NAND-A cells constituting the central blocks 2-1 to 2- (N-1) in the memory cell array 2 shown in FIG. FIGS. 4A and 4B are a pattern plan view and an equivalent circuit diagram of one NAND cell portion in FIG. 2, and FIGS. 4A and 4B are AA ′ lines in FIG. FIG. 6 is a cross-sectional configuration diagram along the line BB ′. A memory cell array composed of a plurality of NAND cells is formed on a p-type silicon substrate (or p-type well region) 11 surrounded by the element isolation oxide film 12. In this example, eight memory cells M ₁ , M ₂ ,..., M ₈ are connected in series to one NAND cell.

Each of the memory cells M ₁ , M ₂ ,..., M ₈ has a floating gate 14 (14 ₁ , 14 ₂ ,..., 14 ₈ ) formed on the substrate 11 via a gate insulating film 13. A control gate 16 (16 ₁ , 16 ₂ ,..., 16 ₈ ) is formed thereon via an insulating film 15. These memory cells _{M 1,} M 2, ..., the source of _{M 8,} n-type diffusion layer ₁₉ is a drain (19 _1, 19 2, ..., 19 ₉₎ is connected in a manner to each other sharing one adjacent, Thereby, the memory cells M ₁ , M ₂ ,..., M ₈ are connected in series.

Select gates 14 ₉ , 16 ₉ and 14 ₁₀ , 16 ₁₀ formed in the same process as the floating gate and control gate of the memory cell are provided on the drain side and the source side of the NAND cell, respectively. The selection gates 14 ₉ and 16 ₉ and 14 ₁₀ and 16 ₁₀ are electrically connected in regions not shown, and function as gate electrodes of the selection gate transistors S ₁ and S ₂ . The substrate 11 on which the elements are formed as described above is covered with a CVD oxide film (interlayer insulating film) 17, and a bit line 18 (BL) is disposed on the CVD oxide film 17. The bit line 18 is in contact with the drain-side diffusion layer 19 ₀ at one end of the NAND cell. The control gates 14 of NAND cells arranged in the row direction are commonly arranged as control gate lines CG (1), CG (2),... CG (8). These control gate lines become word lines. The selection gates 14 ₉ , 16 ₉ and 14 ₁₀ , 16 ₁₀ are also continuously extended in the row direction, and are used as selection gate lines SG ₁ , SG ₂ . Also, a source line wiring layer 22 is disposed between the bit line 18 and the control gate line / selection gate line wiring layer, and a source side diffusion layer 19 ₁₀ (end opposite to the bit line contact) of the NAND cell. ).

FIG. 5 and FIG. 6 are for explaining NAND-B cells constituting the blocks 2-0 and 2-N at the end of the memory cell array shown in FIG. 1, and FIGS. FIG. 6 is a pattern plan view and an equivalent circuit diagram of one NAND cell portion in FIG. 2, and FIG. 6 is a cross-sectional configuration diagram taken along the line AA ′ in FIG. NAND cell differs from that of Figure 3 and Figure 4 part of FIG. 5 and FIG. 6 is a dimension of about selection gate line SG _2.

That is, FIG. 5, the NAND cell shown in FIG. 6, the line width of 3 of the selection gate lines SG _2, is characterized by thicker than NAND cell of FIG. 4, i.e. Wsg2 (Figure 3) <Wsg2 ( (Fig. 5)
Therefore, the length of the NAND cell in the long side direction (corresponding to the length of the AA ′ cross section in FIGS. 3 and 5), that is, the cell size is the NAND cell shown in FIGS. A little longer than 5, the line width of the select gate line SG ₂ in FIG. 6 machining accuracy has been set to the thickness of an extent that does not break when dropped. This avoids the problem of breakage of the select gate line SG ₂ in the arrangement block 2-0,2-N to the end of the memory cell array 2. The other blocks 2-1 to 2- (N-1) in the memory cell array 2 use the cells shown in FIGS. 3 and 4 having a smaller cell size than the cells shown in FIGS. Therefore, the difference between the present invention shown in FIG. 1 and the conventional cell array shown in FIG.
[NAND cell size in FIG. 3−NAND cell size in FIG. 5] × 2
It becomes. Usually, since the number of blocks is about several hundred to several thousand, the ratio of this difference to the entire cell size is extremely small and can be ignored. That is, according to the first embodiment, the reliability of the chip operation can be improved without increasing the chip size.

In the first embodiment,
Wsg2 (NAND-A cell) <Wsg2 (NAND-B cell)
And has been described manner to prevent disconnection of the select gate line SG ₂ block 2-0,2-N cell array end by, the present invention is not limited to the above first embodiment, Various modifications are possible. Also in the case of using the modifications described below, the chip operation reliability and yield can be improved without increasing the chip size for the same reason.

For example, if the space between the select gate line SG ₂ and the source line contacts and Ss1 (FIG. 3 (a), reference FIG. 4 (a)), in the case of FIG. 1,
Ss1 (NAND-A cell) <Ss1 (NAND-B cell)
With, in the case where the machining accuracy of the block of the cell array end thickened select gate line SG ₂ decreases also, since a wide space Ss1 between the select gate line SG ₂ and the source line contact, select gate line SG The risk of a short circuit between ₂ and the source line contact can be greatly reduced. This method is also very effective, and a highly reliable chip can be realized.

As shown in FIGS. 7 and 8, the NAND cell from which the source line contact is removed is used as the NAND-B cell (blocks 2-0 and 2-N) in FIG. 1, and the NAND-A cell (block 2). -1 to 2- (N-1)) may be a method using the NAND cell shown in FIGS. In this case, since during the cell array end blocked no source line contact, when the machining accuracy of the cell array end block thickened select gate line SG ₂ and drops, the select gate line SG ₂ and the source line The risk of shorting between contacts can be eliminated.

  7 and 8, the source line contact is deleted, but the source line wiring layer 22 remains. The presence or absence of the wiring layer 22 is not a problem, and the necessity / unnecessity of the wiring layer 22 is determined from the viewpoint of the processing accuracy of the wiring layer 22. That is, the present invention is effective regardless of the presence or absence of the wiring layer 22.

  In the first embodiment, the present invention has been described by taking the case where the memory cell array has a block arrangement as shown in FIG. 1 as an example. However, in other cases, for example, when the block arrangement is as shown in FIG. The present invention can also be applied to.

That is, while the select gate line SG ₂ as wiring 1 in the memory cell array edge Figure was provided, selection gate lines SG _1, FIG. 9 is provided. In this case, the Wsg1 the wiring width of the select gate lines SG _1,
Wsg1 (NAND-A cell) <Wsg1 (NAND-B cell)
By setting, it is possible to prevent breakage of the selection gate lines SG ₁ in a block of the memory cell array edge. Furthermore, when Sb1 space between the selection gate lines SG ₁ and the bit line contact, as in the case of the first embodiment, with respect to FIG. 9,
Sb1 (NAND-A cell) <Sb1 (NAND-B cell)
By setting, in a case where the machining accuracy of the cell array end block thickened select gate line SG ₁ decreases also, it can significantly reduce the short risk between the selection gate lines SG ₁ and the bit line it can.

Further, as shown in FIGS. 10 and 11, by eliminating the bit line contacts in the block of the cell array end, the selection gate lines SG ₁ processing precision block 2-0,2-N cell array end is lowered is when thickened, it can also be eliminated short risk between the selection gate lines SG ₁ and the bit line contact.

  The various modifications related to the first embodiment described above are very effective when a plurality of modifications are combined.

For example, for the block arrangement of FIG. 1, the NAND-A cell shown in FIGS. 3 and 4 and the NAND-B cell shown in FIGS. 5 and 6 and the cells shown in FIGS. 7 and 8 are combined. Wsg2 (NAND-A cell) <Wsg2 (NAND-B cell)
In addition, when the NAND-B cell from which the source line contact is deleted is used, operation reliability and yield can be greatly improved.

Similarly, for the block arrangement of FIG. 9, the cells of FIGS. 3 and 4 are used as NAND-A cells, and
Wsg1 (NAND-A cell) <Wsg1 (NAND-B cell)
In addition, when the NAND-B cell in which the bit line contact is deleted (see FIGS. 10A and 11) is used, the operation reliability and yield can be greatly improved.

Further, in the in the first embodiment, if the same wiring in the memory cell array ends at the upper and lower cell arrays ends, i.e. an upper and lower both the select gate line SG ₂ in the arrangement of FIG. 1, the embodiment of FIG. 9 in but a was the case up and down both the select gate lines SG _1, also the present invention in other cases is valid. For example, when the wirings at the upper and lower memory cell array ends are the select gate lines SG ₁ and SG ₂ (see FIG. 12), or conversely, the select gate lines SG ₂ and SG ₁ (see FIG. 13), respectively. The present invention is effective even when the upper and lower parts are different, and the present invention can be applied by combining the above-described modified examples. In this case, as blocks 2-0 and 2-N at the end of the memory cell array, one of the upper and lower ones is a NAND-B block, the other is a NAND-C block, and the other block is a NAND-A book. What is necessary is just to provide a kind of block.

  In the first embodiment, the present invention has been described by taking as an example the case where the number of control gate lines and word lines in the blocks 2-0 and 2-N at the end of the memory cell array is the same as in other blocks. However, the present invention is not limited to this configuration. The block at the end of the memory cell array is normally a non-used (data writing / reading) block, so it is not necessary to use the same number of wires as the used block, and the number of wires is sufficient so that the processing accuracy of adjacent blocks does not deteriorate. It only has to be arranged. In order to maintain the processing accuracy of the blocks 2-1 and 2- (N-1) adjacent to the block at the end of the cell array, among the used blocks 2-1 to 2- (N-1), in FIG. A cell array end block is provided, and it is sufficient that this block includes a minimum number of wires for maintaining processing accuracy. For example, when there are four control gate lines in the cell array end block and fewer than other blocks due to processing accuracy problems (see FIG. 14), or conversely, the number of control gate lines is twelve to further increase processing accuracy. It is possible to make various changes such as increasing the number (see FIG. 15).

  In the first embodiment, the case where the wiring of the selection gate line at the end of the memory cell array is thickened or the periphery of the contact at the end of the cell array is changed has been described as an example. The present invention is also effective when the control gate line adjacent to the selection gate line is thickened or the wiring in the block at the end of the cell array is thickened as a whole.

In a NAND cell, when a block is not selected, at least one of the selection transistors S ₁ and S ₂ must be in an off state, otherwise a failure occurs due to the connection between the bit line and the source line. . Some operating systems, during the non-selected block, to some method to the OFF state only select transistors S _1, there is also a method in which the off state only the selected transistor S _2. The particular problem in the prior art, when employing the method of the OFF state only select transistors S _1, or when an off state only the selected transistor S ₂ in FIG. 9 memory cell array end being a select gate line SG ₁ memory cell array edge when employing the method according to the selective gate line SG ₂ is the case of FIG. 1, or disconnected thinner by the selection gate line processing variations in the memory cell array edge in these cases, select transistors Due to the deterioration of the cut-off characteristics due to the shortening of the channel length, the bit line and the source line are short-circuited, resulting in a defect. When the present invention is applied to such a case, the line width of the selection gate line at the end of the memory cell array is set to be large, so that the selection transistor can be reliably turned off and a defect can be prevented.

  As described above, setting the line width of the selection gate line at the end of the memory cell array to be larger than the selection gate at the end of the memory cell array on the data pattern in the mask for processing the selection gate line compared to other selection gate lines. This can be realized by using a method of setting the line width to be thick. In addition, it goes without saying that the present invention is also effective when the line width of the selection gate line at the end of the memory cell array is set to be thick using other methods.

  Further, although the line width variation after processing is small as the line width of the selection gate line at the end of the memory cell array, the ratio of the line width after processing to the line width on the mask due to collapse of the periodicity of the wiring However, there are cases where it is always smaller than other select gate lines. That is, when all the select gate lines have the same width on the mask data pattern, the line width of the memory cell array end select gate line is always smaller than the width of the other select gate lines. In such a case, the line width of the selection gate line at the end of the cell array is set larger than the other selection gate line width on the mask data pattern so that all the selection gate line widths after processing are the same. Is also effective. In this case, since the widths of all the selection gate lines are the same, the channel lengths of the selection transistors in all the NAND cells are also the same, and defects due to a short of the bit line or the source line can be prevented.

Further, in the in the first embodiment has been described the case line width of the selection gate lines SG ₁ and SG ₂ in the NAND cell other than the block of the memory cell array edge are the same as an example, the present invention Is not limited to this. For example, even when the line width of the selection gate lines SG ₁ in the NAND cell other than the blocks of the cell array end and SG ₂ are different, the cell array end when the wiring of the cell array end of the select gate lines SG ₁ in the data pattern of the mask method of thickening than the wiring width of the selection gate lines SG ₁ the line width of the other selection gate lines SG ₁ is effective. Similarly, if the wiring of the memory cell array end of the select gate line SG ₂ is thicker than the wiring width of the cell array end of the select gate line SG other selection gate lines SG ₁ a wiring width of ₂ in the data pattern of the mask The method is effective, and the present invention can be applied.

  The block at the end of the memory cell array is usually installed for the purpose of improving the processing accuracy of other blocks, and it is possible to maintain the periodicity of the wiring other than the block at the end of the cell array in the memory cell array. In such a case, it is unavoidable that the processing accuracy of the selection gate line and the control gate line in the block at the end of the cell array is lowered. Therefore, the block at the end of the cell array is not used as a dummy block (usually as a data storage area). The block is arranged only for the purpose of improving the processing accuracy, and is not selectable and cannot be replaced with another block). In particular, in the first embodiment, the block (corresponding to FIG. 8 and FIG. 11) from which the source line contact and bit line contact at the end of the cell array are deleted cannot perform normal data storage / reading operations, and is therefore a dummy. It becomes a block. In the cell array end block, when the contact between the bit line and the source line is left and the number of control gate lines in the block is the same as other blocks, the block at the cell array end is replaced with a redundancy block, that is, a defective block. It can also be used as a block (a block that can be replaced with a defective block by cutting a fuse). As an example of using as a redundancy cell block, it is possible to first check the operation of the redundancy block at the end of the memory cell array after chip manufacture, and use it as a redundancy block if it is normal, and use it as a dummy block if there is an abnormality. . As a result, the number of redundancy blocks can be increased according to the processing state of the block at the end of the cell array, and a very large effect can be obtained. By using the present invention, the state after processing of the block at the end of the cell array can be greatly improved as compared with the prior art. Therefore, the present invention is very effective even when used as a redundancy block. As described above, the present invention can also be applied to the case where the block at the end of the cell array is used as a dummy block or a redundancy block.

[Second Embodiment]
Next, a semiconductor memory device according to a second embodiment of the present invention will be described. In the first embodiment, the processing accuracy of the block at the end of the memory cell array is a problem. In the second embodiment, the periodicity of the wiring around the word line in one NAND cell is lost. This prevents a reduction in machining accuracy due to the above.

FIGS. 16A and 16B are a pattern plan view and an equivalent circuit diagram of one NAND cell portion in the memory cell array. FIGS. 17A and 17B are respectively A- It is a section lineblock diagram along an A 'line and a BB' line. A memory cell array composed of a plurality of NAND cells is formed on a p-type silicon substrate (or p-type well region) 11 surrounded by the element isolation oxide film 12. In the second embodiment, as in the first embodiment described above, eight memory cells M ₁ , M ₂ ,..., M ₈ are connected in series to form a NAND cell.

Each of the memory cells M ₁ , M ₂ ,..., M ₈ has a floating gate 14 (14 ₁ , 14 ₂ ,..., 14 ₈ ) formed on the substrate 11 via a gate oxide film 13, and an insulating film thereon. A control gate 16 (16 ₁ , 16 ₂ ,..., 16 ₈ ) is formed through 15. These memory cells _{M 1,} M 2, ..., the source of _{M 8,} n-type diffusion layer ₁₉ is a drain (19 _1, 19 2, ..., 19 ₉₎ is connected in a manner to each other sharing one adjacent, Thereby, the memory cells M ₁ , M ₂ ,..., M ₈ are connected in series.

The drain side of the NAND cell, each of the source, the memory cells _{M 1,} M 2, ..., a floating gate 14, control gate 16 formed simultaneously with the selection gates ₁₄ 9, 16 ₉ and ₁₄ 10, _{16 10 M 8} Is provided. These selection gates 14 ₉ and 16 ₉ and 14 ₁₀ and 16 ₁₀ are electrically connected in regions not shown, and function as gate electrodes of the selection gate transistors S ₁ and S ₂ . The substrate 11 thus formed with the element is covered with a CVD oxide film (interlayer insulating film) 17, and a bit line 18 (BL) is disposed on the CVD oxide film 17. Bit line 18 is in contact with the drain-side diffusion layer 19 ₀ at one end of the NAND cell. The control gates 14 of NAND cells arranged in the row direction are commonly arranged as control gate lines CG (1), CG (2),... CG (8). These control gate lines serve as word lines. The selection gates 14 ₉ , 16 ₉ and 14 ₁₀ , 16 ₁₀ are also continuously extended in the row direction, and serve as selection gate lines SG ₁ , SG ₂ .

  The feature of the NAND cell type EEPROM according to the second embodiment is that, as shown in FIGS. 16A and 17A, compared with the control gate lines CG (2) to CG (7), That is, the control gate lines CG (1) and CG (8) have a large line width.

Normally, the selection gate lines SG ₁ and SG ₂ are set to have a larger line width than the control gate line in order to improve the cutoff characteristics of the selection gate transistors S ₁ and S ₂ (reduction of leakage current when turned off). It is. Further, in order to reduce the influence on the selection gate lines SG ₁ and SG ₂ at the time of processing the wiring layer 14 in the portions of the control gate lines CG (1) to CG (8), between the control gate line and the selection gate line The spaces Ssg1 and Ssg2 are set to have larger targets than the spaces Scg12 to Scg78 between the control gate lines. Therefore, periodic arrangement CG wiring (1), SG ₁ or between CG (8), since the collapse at between SG _2, as compared to CG (2) ~CG (7) , CG (1) , CG (8) processing accuracy is lowered, and processing variation is increased.

  However, as in the embodiments of FIGS. 16A and 17A, the target of the line width of the control gate lines CG (1) and CG (8) adjacent to the selection gate line is controlled by other control. When the control gate lines CG (1) and CG (8) are slightly narrowed due to a decrease in processing accuracy, the control is performed because the target of the original line width is large by setting the gate line larger than the gate line. The finished line widths of the gate lines CG (1) and CG (8) do not become extremely small compared to the control gate lines CG (2) to CG (7). In this case, it is possible to prevent an extreme reduction in the cut-off characteristics of the memory cell due to the extremely narrow channel length as shown in FIG. Thus, it is possible to realize a cut-off possible state.

  Further, in the second embodiment, among the control gate lines in the NAND cell, there are only two control gate lines adjacent to the selection gate line to increase the aim of the line width. Increasing the NAND cell size by increasing the width target is not so large.

  Therefore, by using the second embodiment, a chip with high data writing / reading reliability can be realized without causing a significant increase in chip size.

In the second embodiment, in the case where only the control gate line adjacent to the selection gate line among the control gate lines in the NAND cell is used, the aim of the line width is made larger than that of the other control gate lines. An embodiment has been shown. When the contents of this embodiment are expressed by a formula,
Wcg1> Wcg2-Wcg7
Wcg8> Wcg2-Wcg7
Wcg2 = Wcg3 = Wcg4 = Wcg5 = Wcg6 = Wcg7
It becomes. Further, in this case, with respect to the increase amount of Wcg1 and Wcg8 with respect to the target Wcg2 to Wcg7, when the periodicity is lost, the magnitude of the influence of each of the control gate lines CG (1) and CG (8) (processing) The optimum value may be taken in accordance with the degree of accuracy reduction. Therefore, in some cases, it is optimal to set Wcg1 = Wcg8 depending on the magnitude of the influence of each of the control gate lines CG (1) and CG (8). In other cases, Wcg1> Wcg8 or Wcg1 <Wcg8 is optimal. In some cases.

  In this case, since Wcg1 and Wcg8 are thicker than the other control gate lines, the periodicity breaks down strictly between Wcg1 and Wcg2 or between Wcg7 and Wcg8, but the difference between Wcg1, Wcg8 and Wcg2, Wcg7 is relatively small. For example, the amount of decrease in the processing accuracy of Wcg2 and Wcg7 due to the influence of the periodicity breaking between Wcg1 and Wcg2 or between Wcg7 and Wcg8 is reduced. In the second embodiment, a case is considered in which the word line width is adjusted within a range in which the amount of decrease in processing accuracy due to the disruption of periodicity due to the difference in control gate line width is small (a level that does not cause a problem). .

  In general, if S1, Wsg2, and Ssg2 are comparable to Su, Wsg1, and Ssg1 in FIGS. 16A and 38A, respectively, the degree of reduction in machining accuracy is controlled. Since the gate lines CG (1) and CG (8) have the same level, it is desirable that Wcg1 = Wcg8. On the other hand, when S1, Wsg2, and Ssg2 are relatively smaller than Su, Wsg1, and Ssg1, respectively, Wcg1> Wcg8 is optimal, and S1, Wsg2, and Ssg2 are respectively set to Su, Wsg1, and Ssg2. If is a relatively large value, Wcg1 <Wcg8 is likely to be optimal.

  In the second embodiment, the control gate lines CG (1) and CG (8) at the boundary where the periodicity is lost due to the loss of the periodicity of the wiring arrangement of the control gate line and the selection gate line in the NAND cell. The method of solving the problem that the machining accuracy of () decreases is described. Usually, among the control gate lines CG (1) to CG (8), the degree of deterioration of the processing accuracy of CG (1) and CG (8) is particularly large, so the second embodiment is effective.

However, the influence that this periodicity breaks affects other than the wiring at the boundary, and the influence is larger as the distance from the boundary is closer (the reduction in machining accuracy is larger). For example, in FIG. 36 (a), the control gate lines CG (1) and CG (8) are most greatly affected, followed by CG (2) and CG (7) that are greatly affected. CG (3), CG (6),... If a reduction in processing accuracy becomes a problem in CG (2), CG (7), etc. in addition to the control gate lines CG (1), CG (8), the aim of the line width is increased as described above. It is effective to apply the method to the control gate lines CG (2), CG (7) and the like. When applied to only four control gate lines CG (1), CG (8), CG (2), and CG (7),
Wcg1>Wcg2> Wcg3-Wcg6
Wcg8>Wcg7> Wcg3 to Wcg6
Wcg3 = Wcg4 = Wcg5 = Wcg6
The method of increasing the aim of the line width near the boundary where the periodicity is broken is particularly effective. In addition to the effect of periodicity collapse,
Wcg1>Wcg2>Wcg3> Wcg4, Wcg5
Wcg8>Wcg7>Wcg6> Wcg4, Wcg5
Wcg4 = Wcg5
The method is also effective.

Further, in the second embodiment, as the number of control gate lines to set the line width large, the same to the control gate line select gate line SG ₂ close and the control gate line select gate line SG ₁ close Although the case has been described as an example, the present invention is not limited to this. For example, if the degree of reduction in machining accuracy due to collapse of the periodicity greater in the selection gate lines SG ₁ side of the control gate lines,
Wcg1>Wcg2> Wcg3 = Wcg4 = Wcg5 = Wsg6 = Wsg7
Wcg8> Wcg3 = Wcg4 = Wcg5 = Wsg6 = Wsg7
And then, if the degree of reduction in machining accuracy due to collapse of the periodicity in the opposite greater in the select gate line SG ₂ side of the control gate lines,
Wcg1> Wcg2 = Wcg3 = Wcg4 = Wcg5 = Wsg6
Wcg8>Wsg7> Wcg2 = Wcg3 = Wcg4 = Wcg5 = Wsg6
In some cases, the method is most effective. Also, if the degree of reduction in machining accuracy due to collapse of periodicity is small at the control gate line select gate line SG ₂ near the
Wcg1> Wcg2 = Wcg3 = Wcg4 = Wcg5 = Wsg6 = Wsg7 = Wsg8
As such, only the method is extremely effective to apply the increase in line width with respect to the selection gate lines SG ₁ shift control gate line, as well as control the degree of reduction in machining accuracy due to collapse of the periodicity of the SG ₁ close the gates of If the line is small,
Wcg8> Wsg1 = Wcg2 = Wcg3 = Wcg4 = Wcg5 = Wsg6 = Wsg7
Method of applying a line width increases only selected gate line SG ₂ shift control gate line as is very effective.

  In the second embodiment described above, some of the control gate lines in the NAND cell are set to have a large line width. However, the minimum necessary only for a line in which a large setting is indispensable. Since the method of increasing the line width by the limited size is used, the increase amount of the NAND cell size can be reduced as compared with the conventional method of setting the control gate line width to be uniformly large. Further, by examining the processing accuracy and the NAND cell size, it is possible to examine which method in the second embodiment is most effective.

  As described above, in order to solve the problem caused by the deterioration of the processing accuracy caused by the periodicity of the wiring or the like, the second embodiment of the present invention that uses the method of selectively changing the target of the word line width is used. Although the embodiment has been described, the present invention is not limited to the second embodiment and can be variously modified. In the second embodiment, the present invention has been described by taking as an example the case where the periodicity between the selection gate line and the control gate line is broken. However, the periodicity of other parts is broken, for example, control It is also effective when the gate line layout is not periodic, or when periodicity cannot be realized due to the influence of wiring other than the selection gate line or control gate line, and the target of the gate line width is changed selectively. It is possible to apply this method.

  In the description of the second embodiment, the method of selectively enlarging the line width targets such as the control gate line and the selection gate line has been described. In an actual chip manufacturing process, the method of changing the size on the mask is the easiest, and this method is usually used. That is, the width of the control gate line adjacent to the selection gate line is made larger than the width of the other control gate lines on the data pattern in the processing mask for the control gate line and the selection gate line. Form can be realized. However, even when a method other than using a mask is used, the present invention can of course be applied as long as it is a method capable of realizing the second embodiment.

  Furthermore, the wiring set with a large line width in the second embodiment has a relatively low processing accuracy, and even when the degree of thinning of the line width due to processing variations is greatest, the memory cell is cut. The aim of the line width is set so that the off characteristic does not deteriorate. Accordingly, in many cases (when the line width has not become extremely narrow due to processing variations), the wiring having a large line width is larger in width than other control gate lines after processing.

  Further, in the second embodiment, the case where the processing accuracy of the control gate line located at the end of the control gate line group is lowered and the processing variation is increased has been described. The invention is applicable and effective. For example, when the wiring widths on the masks of all control gate lines are the same, the line width of the control gate line located at the end of the control gate line group is always higher than other control gate lines due to the disruption of the periodicity of the wiring. It can also be applied when processing thinly. In other words, although the processing variation is small, the ratio of the processed wiring width to the wiring width on the mask in the control gate line located at the end of the control gate line group is stably smaller than the other control gate lines. It can also be applied to cases. In this case, the wiring width on the mask of the control gate line located at the end of the control gate line group is set to the wiring width of other control gate lines so that the processed wiring width is the same in all the control gate lines. A slightly larger method is effective.

[Third Embodiment]
Next, a semiconductor memory device according to a third embodiment of the present invention will be described. In the first and second embodiments, the processing accuracy is prevented from being lowered due to the disruption of the periodicity of the wiring around the word line in the block at the end of the memory cell array or in one NAND cell. In this embodiment, the stress applied to the control gate line during the manufacturing process prevents the reliability of the insulating film around the floating gate of the memory cell from being lowered or the stored data from being destroyed. .

FIGS. 18A and 18B are a pattern plan view and an equivalent circuit diagram of one NAND cell portion in the memory cell array. FIGS. 19A and 19B are respectively A- It is a section lineblock diagram along an A 'line and a BB' line. A memory cell array composed of a plurality of NAND cells is formed on a p-type silicon substrate (or p-type well region) 11 surrounded by the element isolation oxide film 12. In the third embodiment, as in the first and second embodiments described above, eight memory cells M ₁ , M ₂ ,..., M ₈ are connected in series to form a NAND cell. Yes.

Each of the memory cells M ₁ , M ₂ ,..., M ₈ has a floating gate 14 (14 ₁ , 14 ₂ ,..., 14 ₈ ) formed on the substrate 11 via a gate oxide film 13, and an insulating film thereon. A control gate 16 (16 ₁ , 16 ₂ ,..., 16 ₈ ) is formed through 15. These memory cells _{M 1,} M 2, ..., the source of _{M 8,} n-type diffusion layer ₁₉ is a drain (19 _1, 19 2, ..., 19 ₉₎ is connected in a manner to each other sharing one adjacent, Thereby, the memory cells M ₁ , M ₂ ,..., M ₈ are connected in series.

Select gates 14 ₉ , 16 ₉ and 14 ₁₀ , 16 ₁₀ formed in the same process as the floating gate and control gate of the memory cell are provided on the drain side and the source side of the NAND cell, respectively. The selection gates 14 ₉ and 16 ₉ and 14 ₁₀ and 16 ₁₀ are electrically connected in regions not shown, and function as gate electrodes of the selection gate transistors S ₁ and S ₂ . The substrate 11 on which the element is formed in this manner is covered with a CVD oxide film (interlayer insulating film) 17, and a bit line 18 (BL) is disposed on the CVD oxide film 17. Bit line 18 is in contact with the drain-side diffusion layer 19 ₀ at one end of the NAND cell. The control gates 14 of NAND cells arranged in the row direction are commonly arranged as control gate lines CG (1), CG (2),... CG (8). These control gate lines serve as word lines. The selection gates 14 ₉ , 16 ₉ and 14 ₁₀ , 16 ₁₀ are also arranged as selection gate lines SG ₁ and SG ₂ continuously in the row direction, respectively. Also, a source line wiring layer 22 is disposed between the bit line 18 and the control gate line / selection gate line wiring layer, and a source side diffusion layer 19 ₁₀ (on the opposite side of the bit line contact) of the NAND cell. End).

  FIG. 20 shows a connection example between the memory cell array and the row decoder, and a configuration example of the row decoder. A NAND cell block decode signal for each block is supplied to a NAND gate 51, and a row decoder activation signal RDECD is supplied to an inverter 52. The output signal of the NAND gate 51 and the output signal of the inverter 52 are respectively supplied to a NOR gate 53, and the output signal of the NOR gate 53 is supplied to a voltage switching circuit 54. The voltage switching circuit 54 switches the levels of the nodes N1 and N2 in response to the output signal of the NOR gate 53, and includes an inverter 55 and a flip-flop 56. The output signal of the NOR gate 53 and the output signal of the inverter 55 are supplied to the flip-flop 56, and the output of the flip-flop 56 is inverted. The voltage VPPRW is supplied from the voltage switching circuit 54 to the row decoders 5a and 5b through the node N1. The row decoder 5a is supplied with signals SGD, SGDS, CGD2, CGD4, CGD6 and CGD8, and the row decoder 5b is supplied with signals CGD1, CGD3, CGD5, CGD7, SGS and a voltage VPPRW. The memory cell array 2 is supplied with decode signals from the row decoders 5a and 5b.

As can be seen from FIG. 20, the control gate lines CG (1) to CG (8) and the selection gate lines SG ₁ and SG ₂ in the memory cell array 2 are connected to one of the source and drain of the transistors in the row decoders 5a and 5b. It is connected.

  FIG. 21 shows a configuration example relating to the connection of the control gate line and the selection gate line from the memory cell array 2 to the row decoders 5a and 5b. FIG. 21A shows a configuration example of the control gate line, and FIG. 21B shows a configuration example of the selection gate line. The N-channel transistor QN at the right end in FIGS. 21A and 21B corresponds to the transistor in the row decoders 5a and 5b.

  In the example of FIG. 21A, when the control gate line is connected from the memory cell array 2 to the transistors QN in the row decoders 5a and 5b, as a wiring layer above the control gate line, one wiring layer 22 is provided. Only used. Therefore, according to such a configuration, since the control gate line can be contacted only once during the manufacturing process, the control gate line is charged during contact processing, and stress is applied to the insulating film around the floating gate. As a result, the number of times is one, and the stress can be greatly reduced as compared with the conventional two times. As a result, the deterioration of the quality of the insulating film around the floating gate during contact processing can be significantly improved as compared with the conventional case, and the high data retention characteristics of the memory cell can be realized. Therefore, it is possible to realize a highly reliable chip in which the risk of data destruction is greatly reduced as compared with the prior art.

  On the other hand, in the example of FIG. 21 (b), the selection gate line is connected to the transistor QN in the row decoders 5a and 5b from the memory cell array, and the two wiring layers 22 as the wiring layer above the control gate line. 18 are used. This is because the selection gate line constitutes the gate electrode of the selection transistor in the NAND cell, and the operation or role that requires extremely high demands on the film quality of the insulating layer around the gate electrode (data retention in the memory cell) This is because there is no major problem even if a slight stress is applied to the selection gate line.

  In addition, the normal selection gate line has a role of controlling selection / non-selection of the block, and it is desirable that the selection gate line can be charged and discharged at high speed in order to realize a highly reliable operation. For example, in order to reduce the leakage current flowing through the NAND cell of the non-selected block during the read operation from the bit line, it is necessary to turn off the selection transistor of the non-selected block at a high speed. Speeding up is important. In order to realize this high speed, it is desirable that the value of the wiring resistance of the selection gate line in the row decoders 5a and 5b from the memory cell array 2 is low. Usually, when the different wiring layers are compared, the upper layer wiring has a lower resistivity. Therefore, it is desirable to use the upper layer wiring as much as possible as the selection gate line. Therefore, the example of FIG. Then, the upper wiring layer 18 was used for connection. On the other hand, with respect to the control gate line, since it is usually more important to improve the data retention characteristics of the memory cell than to increase the charge / discharge speed, the connection is made without using the wiring layer 18 in FIG. Is going.

  Further, regarding the pattern creation of the row decoders 5a and 5b, as shown in FIG. 21, by using different wiring layers for the control gate line and the selection gate line as wiring from the cell array 2 to the row decoders 5a and 5b, Benefits. That is, the pattern of the row decoders 5a and 5b is equal to the width of one block of the NAND cell (corresponding to the length in the long side direction of FIG. 18A), and all the transistors of the row decoders 5a and 5b shown in FIG. Must be placed. That is, when creating a pattern, it is necessary to pass a large number of wirings (the total number of control gate lines and selection gate lines) in the width of one block. As shown in FIGS. 39A and 39B, when the wiring layers of the control gate line and the selection gate line have the same structure, the wiring of the control gate line and the selection gate line cannot be arranged so as to overlap. The width required to pass through increases, the pattern area of the row decoders 5a and 5b increases, the wiring design rule must be strict (the wiring pitch must be reduced), and the like. Occur. On the other hand, as shown in FIGS. 21A and 21B, main wiring layers used for wiring (corresponding to the wiring layer 22 used as a control gate line and the wiring layer 18 used as a selection gate line in FIG. 21). However, when the control gate line and the selection gate line are different, the control gate line and the selection gate line can be arranged so as to overlap each other. Therefore, the row decoders 5a and 5b having a small pattern area can be formed without strict design rules. .

  The main wiring layer or the main wiring layer described above and below is the wiring length of the wiring layers used for connecting the transistors from the memory cell array end to the row decoder in the selection gate line and the control gate line. Corresponds to the wiring layer constituting the longest wiring (drawn longest in the drawing of the third embodiment), the wiring layer 22 in the control gate line shown in FIG. 21 and the wiring in the selection gate line Corresponds to layer 18. In addition, when there are a plurality of transistors in the row decoder connected to one selection gate line or one control gate line, the transistor that connects the wiring from the end of the memory cell array first (usually most on the memory cell array side) (Corresponding to the arranged transistors) and only the wiring between the end of the memory cell array is considered, and the wiring layer constituting the wiring having the longest wiring length within this range is called the wiring layer of the main wiring. .

  In the third embodiment, in the wiring layer from the memory cell array 2 to the row decoders 5a and 5b, the wiring layer that is higher than the wiring layer used for the control gate line is used for the control gate line. The method for realizing the high-speed charge / discharge operation, the reduction of the stress applied to the memory cell during contact processing, and the reduction of the pattern area of the row decoders 5a and 5b has been described. The present invention is applied to the third embodiment. It is not limited and can be variously modified.

For example, instead of the configuration shown in FIG. 21A as the control gate line in the third embodiment, the wiring structure shown in FIG. 22A or FIG. 22B is used, and as the selection gate line, Similar effects can be obtained by using the wiring structure shown in FIG. In FIG. 22A, the control gate line is once connected to the wiring layer 22 and then connected again to the wiring layer 16 formed in the same process as the control gate line. In FIG. 22B, the control gate line is once connected to the wiring layer 22 and then connected to the wiring layer 23 between the wiring layer 22 and the wiring layer 16. The configuration using the wiring layer 23 is suitable for wiring that cannot be directly connected to the wiring layer 16, such as polysilicon wiring. In this case, the wiring layer that can be connected to the wiring layer 16 or the wiring layer 23 is used. Thus, the wiring layers are connected to each other with 22 interposed. Even when the wiring structure as shown in FIGS. 22A and 22B is used, as in the case of FIG. 21A, the control gate line 16 _i (i = 1 to 8) is used. In addition to the process of processing the contact to which stress is applied (contact between the wiring layer 22 and the control gate line 16 _i (i = 1 to 8)), the wiring layers 22 and 23 mainly used for the control gate line are selected. Since it is different from the wiring layer 18 (see FIG. 21B) mainly used for the gate line, the same effect as that obtained when the wiring structure shown in FIG. 21 is used can be obtained.

  FIGS. 23A, 23B, and 23C show another example of the wiring structure from the memory cell array 2 to the row decoders 5a and 5b. FIG. 23A shows the wiring structure of the control gate lines. , (B), (c) will be described below with reference to FIG. 21B used as the wiring of the selection gate line.

FIG. 23A shows a configuration in which the wiring layer 18 is mainly used as the control gate line, and the control gate line is connected to the pn junction using the wiring layer 16 _i (i = 1 to 8). The wiring layer 18 is connected to the wiring layer 16 _i through the wiring layer 22, and the wiring layer 16 _i is in contact with the n ⁺ -type diffusion layer 25. Since the control gate line takes a voltage range of about 0 V to 20 V during operation, if the p-type well region has a voltage of 0 V or less, the n ⁺ -type diffusion layer 25 and the p-type well region are sequentially connected during normal operation. There is no bias and does not affect the operation. Since the p-type well voltage at which the N-channel transistor QN of FIG. 23A is formed is also usually 0 V or less, the n ⁺ -type diffusion layer 25 and the source / drain region of the transistor QN are formed in the same p-type well region. In this case, since it is not necessary to provide two p-type well regions, the pattern area can be reduced. Thus, when the wiring layer 16 _i connected to the pn junction, when the contact process between the wiring layer 22 during the manufacturing process the wiring layer 16 _i and the wiring layer 18 and the wiring layer 16 _i when the contact process between the wiring layer 22 This pn junction serves as a current path for discharging the charge of the wiring layer 16 _i when it is going to be charged, so that the stress applied to the memory cell due to the charging of the wiring layer 16 _i can be reduced. Usually, the wiring layer 16 _i is formed using polysilicon. In this case, when the n ⁺ -type diffusion layer 25 is directly contacted from the wiring layer 16 _i , aluminum (Al), tungsten (W), or the like is used. Since the contact resistance tends to be larger than the contact resistance using this wiring material, the method of directly connecting the polysilicon wiring to the n ⁺ type diffusion layer forming the source / drain of the transistor QN is not used much. do not do. However, as a current path for preventing the charging of the wiring during the manufacturing process as described above, even if the contact resistance is somewhat high, it is sufficient to function as a path through which a certain amount of current flows, and the pn junction and the wiring layer Compared with the case where there is no connection with 16 _i , a significant reduction in applied stress can be realized.

FIG. 23B shows a case where connection to the pn junction is performed by the wiring layer 22. In this case, as in the case of FIG. 21A, stress due to the charging of the wiring layer 16 _i is applied during contact processing for connecting the wiring layer 22 and the wiring layer 16 _i . However, at the time of contact processing for connecting the wiring layer 18 and the wiring layer 22, since the connection between the wiring layer 22 and the pn junction has already been completed, a discharge current path is formed, and the wiring layers 22 and 16 are connected. The applied stress due to charging can be greatly reduced.

Accordingly, as can be seen from FIG. 23A and FIG. 23B, even when the wiring layer 18 is used as the main wiring of the control gate line, as in FIG. It is obvious that the application of stress due to the charging of the wiring layer 16 _i during contact processing can be significantly reduced by providing the connection portion with the junction.

FIG. 23C shows a configuration in which a connection to the pn junction of the wiring layer 16 _i is added to the wiring structure shown in FIG. 21A. In this case, contact processing to the wiring layer 16 _i is performed. Since the number of times of stress application at that time is as small as one and the connection to the pn junction of the wiring layer 16 _i is already completed at the time of applying the stress, this one-time applied stress is further reduced. Therefore, the applied stress can be extremely suppressed.

Although not shown, the third embodiment can be modified in various ways, such as when the connection to the pn junction of the wiring layer 16 _i is added to the configuration of FIG. 22A or 22B. It is.

  Furthermore, in the third embodiment, the present invention has been described using the wiring structure in the case of using FIG. 21B as a configuration example of the selection gate line. In other cases, for example, the selection gate line The present invention is also effective when the line configuration examples shown in FIGS. 24A to 24D are used.

  First, consider the case where FIG. 22A is used as the wiring structure of the control gate line and FIG. 24A is used as the wiring structure of the selection gate line. When there are only two wiring layers 16 and 22 that can be used for connection between the memory cell array 2 and the row decoders 5a and 5b, a wiring layer having a lower resistivity (corresponding to the wiring 22). ) As the wiring for the selection gate line and the remaining wiring layer 16 as the wiring for the control gate line, which realizes high-speed charge / discharge of the control gate line and reduces the pattern area of the row decoders 5a and 5b. Connected.

  Further, in the case of using FIG. 23C and FIG. 24A, the difference in wiring configuration between the control gate line and the selection gate line is only the presence or absence of connection to the pn junction. Since the pn junction has disadvantages such as a slight increase in pattern area and an increase in the capacity of the connected wiring, it is desirable that the number of wirings connecting the pn junction is as small as possible. When the wiring structures of FIG. 23 (c) and FIG. 24 (a) are combined, the control gate line is connected to the pn junction and the selection gate line is not connected to the pn junction, so the number of pn junctions is minimized ( = Number of control gate lines). This modification is particularly effective when only the wiring layer 22 can be used as the connection wiring from the memory cell array 2 to the row decoders 5a and 5b.

  In the third embodiment, the case has been described in which the reduction in applied stress during contact processing in the selection gate line is not taken into consideration. However, it is more preferable to reduce the stress applied to the selection gate line. In this case, a method of connecting to the pn junction is also effective for the purpose of reducing the stress. For example, FIG. 24B is used as the wiring structure of the selection gate line, and FIGS. 21A, 22A, 22B, and 23C are used as the wiring structure of the control gate line. In this case, the pattern area of the row decoders 5a and 5b is reduced (because the main wiring of the control gate line and the selection gate line is different), the applied stress is reduced, and the charge / discharge operation of the selection gate line is accelerated (= resistivity is reduced). A low wiring layer (usually, a wiring layer located in a higher layer is used as the main wiring of the selection gate line) can be realized. Further, FIG. 24C is used as the wiring structure of the selection gate line, and FIGS. 21A, 22A, 22B, and 23C are used as the wiring structure of the control gate line. The same effect can be obtained also. Furthermore, the same effect can be obtained when FIG. 24D is used as the wiring structure of the selection gate line and FIGS. 22A and 22B are used as the wiring structure of the control gate line. .

In the third embodiment, the pn junction in which the selection gate line and the control gate line are respectively connected has an n ⁺ type diffusion layer-p type well configuration, and the wiring layer is connected to the n ⁺ type diffusion layer. As described above by way of example, the present invention is also effective in other cases, for example, in the case of bonding to a p ⁺ type diffusion layer having a p ⁺ type diffusion layer-n type well structure. In this case, the voltage of the n-type well region is connected during normal operation in order to avoid fluctuation of the voltage of the control gate line due to the forward bias of the pn junction of the p ⁺ -type diffusion layer-n-type well configuration. The voltage needs to be higher than the control gate line and the selection gate line.

In the n ⁺ -type diffusion layer-p-type well configuration, the current through the pn junction as the current path described above is the reverse current of the pn junction when the wiring layer is positively charged, and the wiring layer is negatively charged. In this case, it corresponds to the forward current of the pn junction. On the other hand, in the p ⁺ -type diffusion layer-n-type well configuration, when the charge of the wiring layer is positive, it corresponds to the forward current of the pn junction, and when the charge of the wiring layer is negative, it corresponds to the reverse current of the pn junction. . In general, in the same pn junction, the forward current is much larger than the reverse current. Therefore, the effect of alleviating applied stress during contact processing is that the forward direction of the pn junction has a larger amount of current through the current path. It is bigger to use current.

Therefore, when the charge during contact processing is positive, a pn junction having a p ⁺ -type diffusion layer-n-type well configuration is used, and when negative, a pn junction having an n ⁺ -type diffusion layer-p-type well configuration is used. The configuration has the highest effect of reducing applied stress. Furthermore, when both pn junctions of the p ⁺ type diffusion layer-n type well configuration and the n ⁺ type diffusion layer-p type well configuration are used for the wiring layer to be prevented from being charged, regardless of whether the charge is positive or negative. A current path by the forward current of the pn junction can be realized, and applied stress can be alleviated to the maximum.

FIG. 25 shows an example of a wiring structure in which pn junctions of both a p ⁺ type diffusion layer-n type well configuration and an n ⁺ type diffusion layer-p type well configuration are provided with respect to FIG. In general, when the wiring layer 16 _i is directly connected to the n ⁺ -type diffusion layer or the p ⁺ -type diffusion layer, the n ⁺ -type diffusion layer 25-1 is used when the wiring layer 16 _i is p-type polysilicon. When the wiring layer 16 _i is n-type polysilicon, the contact resistance with the p ⁺ -type diffusion layer 25-2 may become extremely large. In this case, (n ⁺ -type) such as Al or W It is desirable to connect the pn junction and the wiring layer 16 _i through a wiring layer (which has relatively low contact resistance for both the diffusion layer 25-1 and the p ⁺ -type diffusion layer 25-2). Is used. As another example, as shown in FIG. 25B, when the wiring layer 16 _i is n-type polysilicon, the n ⁺ -type diffusion layer 25-1 and the wiring layer 16 _i are directly connected, and the p ⁺ -type diffusion layer is formed. Various modifications such as connection with the wiring layer 22 can be made with the line 25-2.

FIG. 26 shows still another modification. In FIG. 26, when the control gate line is used in addition to being connected to the transistor QN in the row decoders 5a and 5b shown in FIG. This is a wiring structure connected to a certain wiring layer 18, and shows a method of reducing applied stress at the time of contact processing for connecting the wiring layer 18 and the wiring layer 22 at this time. In FIG. 26A, the wiring layer 22 is connected to the n ⁺ type diffusion layer as the source / drain of the transistor QN (connected to the pn junction of the n ⁺ type diffusion layer-p type well configuration). A p ⁺ -type diffusion layer 25-1 provided in the n-type well region is sufficient for a pn junction newly connected to the wiring layer 22. In FIG. 26B, similarly, since the wiring layer 22 is connected to the p ⁺ type diffusion layer of the transistor QN (connected to the pn junction of the p ⁺ type diffusion layer-n type well configuration), For the pn junction connected to the wiring layer 22, only the n ⁺ -type diffusion layer 25-2 provided in the p-type well region is sufficient.

FIG. 27 shows another modification. The wiring structure of FIG. 27 is a modification of FIG. FIG. 27A shows a structure in which a wiring layer 18 is added above the transistor QN in FIG. When evaluating a chip, a technique is usually used in which a word line potential is measured by placing a needle on a node having the same potential as the word line. In general, the higher the position of the wiring layer is, the easier it is to apply the needle. Therefore, the node of the wiring layer 18 in FIG. 27A is provided for the purpose of facilitating the contact with the needle. Yes. Further, regarding the damage at the time of opening the contact when using FIG. 27A, only the damage at the time of opening the contact for connecting the wiring layer 18 and the wiring layer 22 is different from that in FIG. In this case, since the wiring layer 22 is already connected to the pn junction of the transistor, the wiring layer 22 and the control gate line 14 _i (i = 1 to 8) are not charged and hardly damaged. For this reason, even when the wiring structure of FIG. 27A is used instead of FIG. 21A, a highly reliable chip can be realized as compared with the prior art.

FIG. 27B is a modification in the case where there is a wiring layer located further above the wiring layer 18, and the wiring layer 24 is added to the wiring structure shown in FIG. Yes. Since the wiring layer 24 is located in an upper layer than the wiring layer 18, the use of the wiring structure of FIG. 27 (b) makes needle contact easier than in FIG. 27 (a), and the wiring layer 22 and the wiring layer 24. Since the wiring layer 22 is already connected to the pn junction of the transistor QN at the time of contact opening between them, the wiring layer 22 and the control gate line 14 _i (i = 1 to 8) are not charged and are hardly damaged. . For this reason, even when the wiring structure of FIG. 27B is used, it is possible to realize a chip with significantly higher reliability than the conventional one.

  FIG. 27 (c) is a modified example in which the wiring layer 24 is added to FIG. 21 (b). As in the wiring structure of FIG. A highly reliable chip can be realized.

  As described above, the third embodiment of the present invention has been described using various modifications. However, the present invention is not limited to the third embodiment, and various modifications can be made. For example, FIG. 25 and FIG. 26 show examples of the wiring structure of the control gate line, but a similar wiring structure can be used for the selection gate line.

Further, in the third embodiment, the present invention is described by taking as an example the case where contact is made to the wiring layer 14 when the voltage of the selection gate line is connected to another wiring or the like at the end of the memory cell array. However, when the wiring layer 14 and the wiring layer 16 in the selection gate line portion are connected in the memory cell array or the like, the wiring 14 _j (j = 9, 10) and the wiring in the third embodiment are used. It is also possible to change the connected part to the connection with the wiring 16 _j (j = 9, 10), and the same effect as in the third embodiment can be obtained.

  In the third embodiment, the case where the wiring structures of the control gate line from the memory cell array 2 to the row decoders 5a and 5b are all the same has been described as an example. However, the plurality of modified examples are combined. The case is also effective. For example, the present invention is also effective in a wiring structure using the selection gate lines in FIG. 21B and three of the eight control gate lines in FIG. 23B and five in FIG. 21A. 21B is used as the selection gate line. Of the eight control gate lines, two are as shown in FIG. 21A, three are as shown in FIG. 22A, and three are as shown in FIG. The present invention is also effective when three or more types of modifications are combined. When considering the pattern of the row decoders 5a and 5b, if the wiring layers of the main wirings of the control gate line and the selection gate line in the row decoders 5a and 5b are separated from the memory cell array 2, a pattern can be created by overlapping each wiring. . For example, if it is divided into three wiring layers, the pattern area can be reduced because it can be drawn in three stages. In addition, in order to reduce the pattern area, it is very effective to use a combination of a plurality of the above modification examples for the convenience of pattern creation.

  In the third embodiment, the present invention has been described by taking the case where the uppermost layer of the wiring layer used for wiring is the wiring layer 18 as an example. In other cases, for example, the wiring layer 18 is positioned above the wiring layer 18. However, it is possible to change the wiring layer 18 by adding a wiring layer that can be directly connected to the wiring layer 18, and the present invention is also effective for such a wiring structure.

  In the first to third embodiments, the case where the number of memory cells connected in series in one NAND cell is eight has been described. However, the number of memory cells connected in series is not eight. For example, the present invention is applicable to 2, 4, 16, 32, 64, and the like. In the first to third embodiments, the present invention has been described by taking the NAND cell type EEPROM as an example. However, the present invention is not limited to the NAND type EEPROM. The third embodiment can also be applied to a NOR cell type EEPROM, a DINOR cell type EEPROM, an AND cell type EEPROM, a NOR cell type EEPROM with a select transistor, and the second embodiment is a DINOR cell type EEPROM. It can also be applied to an AND cell type EEPROM.

FIG. 28 shows an equivalent circuit diagram of a memory cell array in a NOR cell type EEPROM. The memory cell array, a word line _{WL j, WL j + 1,} WL j + 2, ... and the bit lines _{BL 0,} BL 1, ..., at each intersection of the BL _m, NOR cell _M j0 _{~M j + 2m} is provided, each NOR the control gate of the cell _M j0 _{~M j + 2m} word lines _WL j in each _{row, WL j + 1, WL j} + 2, ... , the drain bit line _{BL 0,} BL 1 in each column, ..., are connected to the BL _m, source Are commonly connected to the source line SL.

FIG. 29 shows an equivalent circuit diagram of the memory cell array in the DINOR cell type EEPROM. In the DINOR cell type memory cell array, a DINOR cell block is provided corresponding to each main bit line D ₀ , D ₁ ,..., D _n . Each DINOR cell selection gate transistors _{SQ 0, SQ 1, ...,} are composed of an SQ _n and the memory cell _M 00 _{~M 31n,} the select gate transistor _{SQ 0, SQ 1, ...,} drain of SQ _n each the main bit lines _{D 0, D 1, ...,} to _{D n,} the gate to select gate line ST, the source is local bit lines _{LB 0, LB 1, ...,} it is connected to the LB _n. The drains of the memory cells M _{00 to} M _31n are connected to the local bit lines LB ₀ , LB ₁ ,... LB _n for each column, and the control gates are connected to the control gate lines W _{0 to} W ₃₁ for each row. The sources are commonly connected to the source line SL.

FIG. 30 shows an equivalent circuit diagram of the memory cell array in the AND cell type EEPROM. In the AND cell type memory cell array, a block of AND cells is provided corresponding to each main bit line D ₀ , D ₁ ,..., D _n . Each AND cell first select gate transistor _{SQ 10, SQ 11, ...,} SQ 1n, the memory cell _M 00 _{~M 31n} and the second select gate transistor _{SQ 20, SQ 21, ...,} are composed of _{SQ 2n} The drains of the first selection gate transistors SQ ₁₀ , SQ ₁₁ ,..., SQ _1n are the main bit lines D ₀ , D ₁ ,..., D _n , and the gates are the source of the _first selection gate line ST ₁ . Are connected to local bit lines LB ₀ , LB ₁ ,..., LB _n , respectively. The drains of the memory cells M _{00 to} M _31n are connected to the local bit lines LB ₀ , LB ₁ ,..., LB _n for each column, and the control gates are connected to the control gate lines W _{0 to} W ₃₁ for each row. Are connected to local source lines LS ₀ , LS ₁ ,..., LS _n . The drains of the second selection gate transistors SQ ₂₀ , SQ ₂₁ ,..., SQ _2n are connected to the local source lines LS ₀ , LS ₁ ,... LS _n , respectively, and the gates are connected to the second selection gate line ST ₂ . The sources are commonly connected to the main source line MSL.

Further, FIG. 31 shows an equivalent circuit diagram of a memory cell array in a NOR cell type EEPROM with a select transistor. This memory cell array is configured by arranging memory cells MC composed of selection transistors SQ and memory cell transistors M in an array. The drain of each selection transistor SQ is connected to the bit lines BL ₀ , BL ₁ ,..., BL _n for each column, the gate is connected to the selection gate line ST for each row, and the source is connected to the drain of the corresponding memory cell transistor M. Connected. The control gate of the memory cell transistor M is connected to the word line WL for each row, and the source is commonly connected to the source line SL.

  For details of the DINOR cell type EEPROM, refer to “H. Onoda et al., IEDM Tech. Digest, 1992, pp. 599-602”, and for details of the AND cell type EEPROM, refer to “H. Kume et al. , IEDM Tech.Digest, 1992, pp. 991-993, respectively.

  In the DINOR cell, only one of the memory cell groups has a selection gate line, but the periodicity of the control gate line is lost even in a portion without the selection gate line (for example, control of the end of the control gate line group on the side without the selection gate). In order to solve the problem caused by the reduction in processing accuracy due to the gate line (corresponding to the word line W31 in FIG. 29), it is effective to selectively change the target of the word line width, Also in this case, the second embodiment of the present invention can be applied.

  In the first to third embodiments, the present invention has been described by taking a nonvolatile semiconductor memory device that can be electrically rewritten as an example. However, the present invention can also be used in other devices. The nonvolatile semiconductor memory device, or the first and second embodiments can be similarly applied to devices such as DRAM and SRAM.

  While the present invention has been described above using the first to third embodiments and various modifications thereof, the present invention can be variously modified without departing from the spirit of the present invention.

1 is a diagram showing a block arrangement in a memory cell array in a NAND cell type EEPROM for explaining a semiconductor memory device according to a first embodiment of the present invention; FIG. 2 is an equivalent circuit diagram of a memory cell array in which NAND cells are arranged in a matrix. FIG. 1 shows a configuration example of a block constituted by NAND-A cells shown in FIG. 1. FIG. 1A is a pattern plan view of one NAND cell portion of the memory cell array in FIG. 2, and FIG. circuit diagram. FIG. 2 shows a configuration example of a block configured by the NAND-A cell shown in FIG. 1, (a) FIG. 3 is a sectional configuration diagram taken along line AA ′ in FIG. 3 (a), and (b) FIG. The cross-sectional block diagram along the BB 'line. 1 shows a configuration example of a block configured by NAND-B cells shown in FIG. 1. FIG. 1A is a pattern plan view of one NAND cell portion of the memory cell array in FIG. 2, and FIG. circuit diagram. FIG. 6 is a cross-sectional configuration diagram taken along the line A-A ′ of FIG. 5A, illustrating a configuration example of a block configured by the NAND-B cell illustrated in FIG. 1. FIG. 2 shows another configuration example of a block constituted by NAND-B cells shown in FIG. 1, (a) FIG. 2 is a pattern plan view of one NAND cell portion of the memory cell array in FIG. 2, and (b) FIG. The equivalent circuit diagram. FIG. 8 is a cross-sectional configuration diagram taken along the line A-A ′ of FIG. 7A, showing another configuration example of a block configured by the NAND-B cell shown in FIG. 1. The figure which shows the other block arrangement | positioning in the memory cell array in NAND cell type EEPROM. FIG. 3 shows still another example of the configuration of the block that constitutes the NAND-B cell shown in FIG. 1. FIG. 5A is a pattern plan view of one NAND cell portion of the memory cell array in FIG. 2, and FIG. The equivalent circuit diagram. FIG. 11 is a cross-sectional configuration diagram taken along the line A-A ′ of FIG. 10A, showing still another configuration example of a block configuring the NAND-B cell shown in FIG. 1. The figure which shows other block arrangement | positioning in the memory cell array in NAND cell type EEPROM. The figure which shows another block arrangement | positioning in the memory cell array in NAND cell type EEPROM. The figure which shows another block arrangement | positioning in the memory cell array in NAND cell type EEPROM. The figure which shows other block arrangement | positioning in the memory cell array in NAND cell type EEPROM. 2A and 2B are diagrams for explaining a semiconductor memory device according to a second embodiment of the present invention, in which FIG. 1A is a pattern plan view of one NAND cell portion in a memory cell array, and FIG. 2B is an equivalent circuit diagram thereof. . FIG. 8 is a diagram for explaining a semiconductor memory device according to a second embodiment of the present invention, in which FIG. 16A is a cross-sectional configuration diagram along the line AA ′ in FIG. 16A, and FIG. The cross-sectional block diagram along the BB 'line. 4A and 4B are diagrams for explaining a semiconductor memory device according to a third embodiment of the present invention. FIG. 5A is a pattern plan view of one NAND cell portion in a memory cell array, and FIG. . FIG. 10 is a diagram for explaining a semiconductor memory device according to a third embodiment of the present invention, in which FIG. 18A is a cross-sectional configuration diagram along the line AA ′ in FIG. 18A, and FIG. The cross-sectional block diagram along the BB 'line. FIG. 9 is a circuit diagram illustrating a connection example between a memory cell array and a row decoder, and a configuration example of a row decoder, for explaining a semiconductor memory device according to a third embodiment of the present invention. FIG. 21 shows a configuration example relating to the connection of a control gate line and a selection gate line from the memory cell array to the row decoder in the circuit shown in FIG. 20, wherein (a) is a cross-sectional configuration diagram of the control gate line, and (b) FIG. Is a cross-sectional configuration diagram of a selection gate line. FIG. 21A shows another configuration example of the control gate line shown in FIG. 21A. FIG. 21A shows that the control gate line is once connected to another wiring layer and then connected again to the same wiring layer as the control gate line. (B) is a cross-sectional configuration diagram in the case where the control gate line is once connected to another wiring layer and then connected to the wiring layer between the wiring layer and the wiring layer of the control gate line. FIG. 4A shows another example of the wiring structure of the row decoder from the memory cell array of the control gate line. FIG. 5A shows the use of the uppermost wiring layer as the control gate line wiring and the control gate line wiring between the control gate and the pn junction. In the case of direct connection using layers, (b) shows the case where the wiring layer for connection to the pn junction is a wiring layer above the control gate line wiring layer, (c) shows the control gate in FIG. The cross-sectional block diagram at the time of adding the connection to the pn junction of a line. FIG. 4A is a diagram illustrating a configuration example of a selection gate line. FIG. 4A illustrates a wiring structure of a selection gate line in which the selection gate line is charged and discharged at high speed and the pattern area of a row decoder is reduced. ) The figure shows the wiring structure of the selection gate line that is connected to the pn junction for the purpose of stress reduction. FIGS. (C) and (d) show the reduction of the pattern area of the row decoder, the reduction of the stress, and the selection gate line. Wiring structure of select gate line to speed up charging / discharging operation. FIG. 11A is a diagram for explaining a configuration example of a selection gate line. FIG. 23A shows a p ⁺ -type diffusion layer-n-type well configuration and an n ⁺ -type diffusion layer-p type with respect to the wiring structure of FIG. Wiring structure provided with both pn junctions in a well configuration, (b) shows that when the wiring layer is n-type polysilicon, the n ⁺ -type diffusion layer is directly connected to this wiring layer and is separate from the p ⁺ -type diffusion layer. Wiring structure connected via the wiring layer. FIG. 2A and FIG. 2B are wiring structures for reducing stress by using diffusion layers as source / drain regions of transistors in a row decoder, respectively, for explaining different configuration examples of select gate lines. . FIG. 21 shows a modification of the wiring structure shown in FIG. 21. FIG. 21A shows a wiring structure in which a wiring layer for applying a potential measuring needle is added to the upper part of the transistor of FIG. A wiring structure in which a wiring layer for applying a potential measuring needle is further added to the wiring structure shown in FIG. 27A. FIG. 27C shows a potential measuring needle applied to the wiring structure shown in FIG. Wiring structure with an additional wiring layer. FIG. 3 is an equivalent circuit diagram of a memory cell array in a NOR cell type EEPROM. The equivalent circuit diagram of the memory cell array in a DINOR cell type EEPROM. The equivalent circuit diagram of the memory cell array in AND cell type EEPROM. The equivalent circuit diagram of the memory cell array in NOR cell type EEPROM with a selection transistor. FIG. 10 is a diagram illustrating a block arrangement in a memory cell array in a NAND cell type EEPROM for explaining a conventional semiconductor memory device. FIG. 33 shows an example of a detailed configuration of a part of the memory cell array shown in FIG. 32, and is an equivalent circuit diagram of the memory cell array in which NAND cells are arranged in a matrix. FIG. 33 shows one NAND cell extracted in detail in the circuit shown in FIG. 33, wherein FIG. 33A is a pattern plan view of the NAND cell portion, and FIG. 33B is an equivalent circuit diagram thereof. FIG. 33 shows one NAND cell extracted from the circuit shown in FIG. 33 in detail, and FIG. 33A is a cross-sectional configuration diagram taken along the line AA ′ of the pattern shown in FIG. The figure is a cross-sectional view taken along the line BB ′. 33 shows another detailed configuration example in which one NAND cell is extracted from the circuit shown in FIG. 33, (a) FIG. 33 is a pattern plan view of the NAND cell portion, and (b) is an equivalent circuit diagram thereof. 33 shows another detailed configuration example in which one NAND cell in the circuit shown in FIG. 33 is extracted, and FIG. 36 (a) is a cross-sectional configuration along the line AA ′ of the pattern shown in FIG. 36 (a). The figure and (b) figure are cross-sectional block diagrams along the BB 'line. This is for explaining a problem when the processing accuracy is lowered. (A) In the figure, when the control gate line is at the target line width, (b) In the figure, the control gate line is thinner than the target line. FIG. FIG. 2 is a diagram for explaining a wiring structure used to connect a control gate line and a selection gate line from the memory cell array to the row decoder, in which (a) shows the control gate line and (b) shows the selection gate line; The figure which shows a wiring structure.

Explanation of symbols

DESCRIPTION OF SYMBOLS 2 ... Memory cell array, 2-0-2-N ... Block, 5a, 5b ... Row decoder, 11 ... P-type silicon substrate (or p-type well region), 12 ... Element isolation oxide film, 13 ... Gate insulating film, 14 (14 ₁ , 14 ₂ ,..., 14 ₈ ) ... floating gate, 15 ... insulating film, 16 (16 ₁ , 16 ₂ , ..., 16 ₈ ) ... control gate (wiring layer), 17 ... CVD oxide film (interlayer insulation) _{film), 18, BL, BL 1} ~BL m ... bit lines (wiring _{layer), 19 (19 1, 19} 2, ..., 19 9) ... n -type diffusion layer, 22, 24 ... wiring layer, 25 ... ^{n +} -type diffusion _{layer, M 1, M 2, ...} , M 8 ... memory cells, _SG 1, _SG 2 _... select gate line, CG (1) ~CG (8 ) ... control gate line, QN ... N-channel transistor.

Claims (12)

A memory cell array in which a plurality of memory cells connected to each other are arranged in an array; and
A selection gate line formed by continuously extending a gate of the selection transistor in the memory cell unit;
A control gate line formed by continuously extending the gate of the memory cell in the memory cell unit;
A row decoder for selecting the selection gate line and the control gate line of the memory cell array and controlling a potential;
A first wiring layer located above the wiring layer constituting the control gate line,
From all the wiring layers used for connection from the memory cell array end of the first control gate line included in the plurality of control gate lines connected to one memory cell unit to the transistors in the row decoder, The wiring layer is located in an upper layer, and the first gate layer is used to connect the selection gate line from the memory cell array end to the transistor in the row decoder, and a second control included in the plurality of control gate lines. The first wiring layer is positioned above all wiring layers used for connection from the memory cell array end of the gate line to the transistors in the row decoder, and the row decoder extends from the memory cell array end of the second control gate line. the semiconductor memory device which is characterized by using a wire connected to the first wiring layer is connected to the transistor in. A second wiring layer located above the wiring layer constituting the control gate line and located below the first wiring layer;
The second wiring layer can be directly connected to a wiring layer constituting a control gate line in the memory cell array without any other wiring layer,
A wiring layer used for connection from the memory cell array end of the first control gate line to the transistor in the row decoder is formed by the second wiring layer or a wiring layer located below the second wiring layer. The semiconductor memory device according to claim 1. Of the wiring lengths of wiring layers used for connection from the memory cell array end of the first control gate line to the transistors in the row decoder, the wiring length of the wiring by the second wiring layer is the longest. The semiconductor memory device according to claim 2 . 4. The wiring length of the wiring by the first wiring layer is the longest among wiring lengths used for connecting the memory cell array of the selection gate line to a transistor in the row decoder. The semiconductor memory device according to one item. A memory cell array in which a plurality of memory cells connected to each other are arranged in an array; and
A selection gate line formed by continuously extending a gate of the selection transistor in the memory cell unit;
A control gate line formed by continuously extending the gate of the memory cell in the memory cell unit;
A row decoder for selecting the selection gate line and the control gate line of the memory cell array and controlling a potential ;
A first wiring layer located above the wiring layer constituting the control gate line ,
From all the wiring layers used for connection from the memory cell array end of the first control gate line included in the plurality of control gate lines connected to one memory cell unit to the transistors in the row decoder, A wiring layer is located in an upper layer, and the first gate layer is used to connect the selection gate line from a memory cell array end to a transistor in the row decoder, and a second layer included in the plurality of control gate lines. first wiring connecting the control gate lines to the transistors in the row decoder from the memory cell array end, the is connected to the pn junction other than the source and drain of the transistor in the row decoder, in said first wiring Includes a wiring of the first wiring layer .   The selection gate line is connected from the memory cell array to the transistor in the row decoder by a second wiring having no connection to a pn junction other than the source / drain of the transistor in the row decoder. The semiconductor memory device according to claim 5. Wherein the first uppermost wiring layer among the wiring layers constituting the wiring, the claims, characterized in that said a second same wiring layer as the uppermost wiring layer among the wiring layers constituting the wiring 6. The semiconductor memory device according to 6 . Of the wiring layers constituting the first wiring, the uppermost wiring layer is a wiring layer located below the uppermost wiring layer of the wiring layers constituting the second wiring. The semiconductor memory device according to claim 6 .   9. The semiconductor memory device according to claim 5, wherein the first wiring is connected to both the p-type diffusion layer and the n-type diffusion layer. The first wiring layer, wherein which is a wiring layer positioned on the upper layer than can be connected directly to wiring layers without using another wiring layer in the wiring layer constituting the control gate lines in the memory cell array Item 10. The semiconductor memory device according to any one of Items 5 to 9. The second wiring includes a wiring layer located above a wiring layer that can be directly connected to a wiring layer constituting a control gate line in the memory cell array without passing through another wiring layer. The semiconductor memory device according to any one of 6 to 10.   The semiconductor memory device according to claim 1, wherein the memory cell unit is a NAND type EEPROM.

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