JPH06204467A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PURPOSE:To prevent deterioration of a gate oxide film without connecting a protecting diode to a metal wiring connected to the gate electrode of a MOS semiconductor element. CONSTITUTION:A first first layer aluminum wiring 7 which is a metal wiring connected to the gate electrode 3 of a MOS semiconductor element and is not connected to a homogeneously diffused layer is set to have a prescribed wire length which does not permit charged particles which are generated by plasma process and incident on the first first layer aluminum wiring 7 to deteriorate the gate oxide film 2 of the MOS semiconductor element. The first first layer aluminum wiring 7 is permitted to pass through a second layer aluminum wiring 13, which is the topmost layer metal wiring connected to the diffused layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly to a measure for preventing deterioration of a gate oxide film due to charge-up during a plasma process in a manufacturing process of a MOS type semiconductor integrated circuit device.

[0002]

2. Description of the Related Art As semiconductor integrated circuits become higher in density and lower in power consumption and the gate oxide film of a MOS device becomes thinner, a gate caused by charge-up due to charged particles (ions / electrons) in a plasma process. Deterioration of the oxide film is becoming a problem. That is, during a plasma process such as a dry etching method or a plasma CVD method, charged particles generated by plasma enter the semiconductor substrate.
If there is a long metal wiring that is connected to the gate electrode and is not connected to the diffusion layer, the charged particles that are incident on the metal wiring are collected, and the gate oxide film of a minute area connected to the metal wiring is deteriorated. Of.

FIG. 5 schematically shows the deterioration of the gate oxide film. In the figure, 51 is a silicon substrate, 52 is a LOCOS oxide film formed on the surface of the silicon substrate 51,
53 is a gate oxide film formed between the LOCOS oxide films 52, 54 is a gate electrode formed on the gate oxide film 53, and 55 is a BPSG interlayer formed on the LOCOS oxide film 52 and the gate electrode 54. Membrane, 56 is BPSG
Aluminum wiring formed on the interlayer film 55 and the gate electrode 54, 57 is a plasma vapor phase generated by a plasma generator (not shown), and 58 is charged particles generated in the plasma vapor phase 57 and incident on the silicon substrate 51. As shown in the figure, after the charged particles 58 enter the aluminum wiring 57, they reach the gate electrode 54 and deteriorate the gate oxide film 53. A phenomenon in which the gate oxide film 53 is significantly deteriorated when the ratio of the area of the charged wiring (aluminum wiring 56) and the area of the gate (gate electrode 54) becomes large is called "antenna effect".

Regarding the deterioration of the gate oxide film, at present, the wiring formation (“Gate Oxide Charging and its Elimi
nation for Metal Antenna Capacitor and Transistor
in VLSI CMOS Double Layer Metal Technology "F.Shon
e et al.; 1989 Symposium onVLSI Technology pp73-7
4) and interlayer film formation ("Thin Oxide Charging Current Duri
ng Plasma Etching of Aluminum "H. Shin et al.; IEEE
Electron Devices Lett., Vol.12, No.8, p404, Aug.1991
However, the same applies to the formation of contact holes. When many contact holes are formed in the metal wiring that is connected to the gate electrode and not connected to the diffusion layer, charged particles generated in the plasma process such as dry etching or sputtering are collected in many contacts and It deteriorates the gate oxide film of a small area connected.

For the above problems, various measures are taken into consideration on both the process side and the circuit design side.
There is an approach to prevent charge-up from the process side, but as long as plasma is used, there is a limit as a measure for preventing deterioration of the gate oxide film.

On the other hand, from the circuit design side, as described in the report on the interlayer film formation, as shown in FIG. 6, means for adding / connecting the protection diode to the aluminum wiring 56 has been proposed. In the figure, 59 is an n ⁺ diffusion layer, 60 is a first aluminum wiring, and 61 is p-TEO.
An S interlayer film, 62 is a second aluminum wiring.

[0007]

However, when the protection diode is added to the aluminum wiring as described above, there is a problem that the circuit operation speed is deteriorated due to the capacitance of the protection diode.

In view of the above, an object of the present invention is to prevent the deterioration of the gate oxide film without connecting a protection diode to the metal wiring connected to the gate electrode of the MOS type semiconductor device.

[0009]

In order to achieve the above object, the invention of claim 1 provides a semiconductor integrated circuit device comprising a MOS
Type metal element connected to the gate electrode of the type semiconductor element but not connected to the diffusion layer, the charged particles generated in the plasma process and incident on the metal wiring are M
The wiring length is set so as not to deteriorate the gate oxide film of the OS type semiconductor device, and the metal wiring of the uppermost layer is used.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device according to the first aspect of the present invention, wherein metal wiring connected to a gate electrode of a MOS type semiconductor element but not connected to a diffusion layer is formed. The charged particles generated in the plasma process and incident on the metal wiring are formed into a predetermined wiring length that does not deteriorate the gate oxide film of the MOS type semiconductor device, and then the metal wiring is passed through the uppermost metal wiring. is there.

A third aspect of the present invention is directed to a method of manufacturing a semiconductor integrated circuit device in which a standard cell group including a plurality of standard cells each formed of a plurality of transistors is connected by an automatic placement and wiring method. After the metal wiring connected to the gate electrode which is each input portion of the standard cell is passed through the uppermost metal wiring in the standard cell, the metal wiring is connected by the automatic placement and wiring method.

[0012]

According to the structure of the first and second aspects of the invention, the metal wiring connected to the gate electrode of the MOS type semiconductor element is
The charged particles generated in the plasma process are set to a wiring length that does not deteriorate the gate oxide film and pass through the uppermost metal wiring connected to the diffusion layer, so that the plasma is ultimately the same circuit configuration. In the process, since the wiring length is short and the number of contact holes opened is small, the charged particles entering the metal wiring or the contact portion are collected and the gate oxide film of a minute area connected to the metal wiring is deteriorated. The "antenna effect" does not occur.

According to the third aspect of the invention, the metal wiring connected to the gate electrode which is each input portion of the plurality of standard cells has a short wiring length and is routed through the uppermost metal wiring in the standard cell. Therefore, in the plasma process, the wiring length is short and the number of contact holes to be opened is small in the plasma process.
"Antenna effect" does not occur.

[0014]

(First Embodiment) FIG. 1 is a cross-sectional view showing the steps of a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention, which is a semiconductor integrated circuit manufactured by the manufacturing method. The device has a two-layer aluminum wiring and is manufactured by the following method.

First, as shown in FIG. 1A, a gate oxide film 2 having a film thickness of 10 nm and a gate length 0.5 made of a polysilicon film are formed on a p-type silicon substrate 1 by a known method.
A MOS n-channel transistor composed of the gate electrode 3 having a thickness of μm and an n ⁺ diffusion layer is formed. Since this figure is a cross-sectional view of the gate electrode surface perpendicular to the source / drain direction,
The diffusion layer is not shown. Further, in the figure, 4 is a LOCOS oxide film for element isolation.

Next, as shown in FIG. 1 (b), the LOCO
After depositing a BPSG film 5 as a first interlayer insulating film on the S oxide film 4 and the gate electrode 3, a contact hole 6 is opened above the gate electrode 3 in the BPSG film 5.
Then, after forming the first first-layer aluminum wiring 7 and the second second-layer aluminum wiring 8 on the BPSG film 5, the first and second first-layer aluminum wirings 7 and 8 are formed on the first and second first-layer aluminum wirings 7 and 8. A silicon oxide film 9 as a second interlayer insulating film is deposited by the plasma CVD method.

The first first connected to the gate electrode 3
The length of the layer aluminum wiring 7 is 10 μm, which will be described later.
The length of the second first layer aluminum wiring 8 connected to another block by the layer aluminum wiring group 14 is 10 m.
The distance between the first first-layer aluminum wiring 7 and the second first-layer aluminum wiring 8 is 5 μm. The length of the first first layer aluminum wiring 7 connected to the gate electrode 3 is as short as 10 μm, and the gate oxide film 2 is formed by the antenna effect at the time of forming the first layer aluminum wiring and depositing the second interlayer insulating film. The deterioration is caused by the first first layer aluminum wiring 7
Is only one thousandth of that when the length is 10 mm.

Next, as shown in FIG. 1C, contact holes 10, 11 and 50 contact holes are formed above the first and second first layer aluminum wirings 7, 8 in the silicon oxide film 9. After the contact hole group 12 is formed, the second layer aluminum wiring 13 having a length of 8 μm for electrically connecting the first first layer aluminum wiring 7 and the second first layer aluminum wiring 8 and the second A second layer aluminum wiring group 14 consisting of 50 aluminum wirings for electrically connecting the first layer aluminum wiring 8 to other blocks is formed.

The gate electrode 3 is electrically connected to the second first-layer aluminum wiring 8 in which 50 contact holes are opened through the second-layer aluminum wiring 13, but the contact hole When forming, the gate electrode 3 is the first
Since the gate oxide film 2 is connected only to the first-layer aluminum wiring 7 of the above, deterioration of the gate oxide film 2 due to the antenna effect at the time of forming the contact hole is caused by opening 50 contact holes on the first first-layer aluminum wiring 7. 1 / 50th of what is done
There is nothing.

As described above, according to the first embodiment, the first first-layer aluminum wiring 7 which is a metal wiring connected to the gate electrode 3 but not connected to the diffusion layer 7 is used.
Is set to a length of 10 μm, which is a length that does not deteriorate the gate oxide film 2 by charged particles generated in the plasma process and incident on the first first-layer aluminum wiring 7, and is connected to the diffusion layer. Since it is connected to the second aluminum wiring 13 and the second aluminum wiring group 14 which are the uppermost metal wirings (if necessary, like the first embodiment, the second aluminum wiring 13 and the second aluminum wiring 13
The aluminum wiring group 14 can be connected to the second first-layer aluminum metal wiring 8), and finally, in the plasma process, the wiring length is short and the number of contact holes to be opened is small even though the circuit configuration is the same. Because there are few
The antenna effect that collects the charged particles entering the metal wiring or the contact portion and deteriorates the gate oxide film of a minute area connected to the metal wiring does not occur.

Therefore, according to the first embodiment, a highly reliable semiconductor integrated circuit device can be manufactured without adding a protection diode that deteriorates the circuit operation speed.

In a SRAM cell or the like whose gate electrode is connected to the diffusion layer through a metal wiring, the diffusion layer serves as a protection diode, and therefore the length of the metal wiring in the first layer is the above. Even if it is a predetermined length or more, it is not necessary to pass the metal wiring of the first layer through the metal wiring of the uppermost layer.

In the first embodiment, the case where the metal wiring group is the aluminum wiring having the two-layer structure has been described. However, when the metal wiring group is the aluminum wiring having the three-layer structure, the gate electrode 3 is used. The same effect can be obtained by setting the aluminum wiring to be connected to the wiring to a length equal to or less than the predetermined wiring length (within 10 μm in the first embodiment) and passing through the third layer aluminum wiring which is the uppermost metal wiring. Obtainable.

(Second Embodiment) FIG. 2 is a layout diagram showing a method of manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention. The manufacturing method is automatically arranged as described below. An aluminum wiring having a three-layer structure is formed by a wiring method.

When designing a semiconductor integrated circuit using the automatic placement and routing method, standard cells 21, 22 and 23 each of which are composed of a plurality of transistors and have a predetermined function are arranged, and these standard cells 21, 22 and 22 are arranged. A first signal line group 24 made up of a plurality of second layer aluminum wirings and a second signal line group 25 made up of a plurality of third layer aluminum wirings for exchanging signals between 23 are wired by the automatic placement and routing method. It

Since each standard cell 21, 22, 23 is sufficiently smaller than the chip size and usually has a size of about 50 μm square, each standard cell 21, 22, 23 has a size of several mm.
There are no long wires. However, since the signal lines are generated by the automatic placement and routing method, it is not possible to know what length aluminum wiring is connected to the standard cells 21, 22, and 23 until the wiring placement is completed.

The standard cell 21 sends signals to the first input line 26 and the second input line 27 which take in signals from the signal lines of the first signal line group 24 and the signal lines of the first signal line group 24. The first output line 28 and the second output line 29 are connected to each other, but only the gate electrode is connected to the first input line 26.

FIG. 3 is a sectional view showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention. The same parts as those in the first embodiment are designated by the same reference numerals as those in the first embodiment. Is omitted.

In FIG. 3, 13A is a first second layer aluminum wiring, 13B is a second second layer aluminum wiring, 31 is a signal line constituting the first signal line group 24, and 32 is a signal line.
Is a silicon oxide film as a third interlayer insulating film, 33 is a third layer aluminum wiring which is the uppermost metal wiring in the standard cell, and 34 is a first and second second layer aluminum wiring 1.
The first input line 26 is a contact hole for connecting the 3A and 13B and the third-layer aluminum wiring 33.
It is connected to the third aluminum wiring 34 which is the uppermost metal wiring. In the second embodiment, the first input line 26 is the first first-layer aluminum wiring 7, and the first first line
The layer aluminum wiring 7 includes the first second layer aluminum wiring 13A, the third layer aluminum wiring 34, and the second second layer aluminum wiring 13A.
It is connected to the second first layer aluminum wiring 8 through the layer aluminum wiring 13B.

As described above, also in the second embodiment, the first first-layer aluminum wiring 7 which is the first input line 26 connected to the gate electrode has the same circuit configuration as described above. In the plasma process, the wiring length is short and the number of contact holes to be opened is small. Therefore, the gate oxide film of a minute area connected to the metal wiring is collected by collecting charged particles entering the metal wiring or the contact portion. There is no "antenna effect" that causes it.

Therefore, according to the second embodiment, a highly reliable semiconductor integrated circuit device can be manufactured without adding a protection diode that deteriorates the circuit operation speed.

In the second embodiment, the first first layer aluminum wiring 7 and the second first layer aluminum wiring 8 are connected to the first and second second layer aluminum wirings 13.
Although the second first layer aluminum wiring 8 was connected to the signal line 31 by connecting A, B and the third layer aluminum wiring 34, instead of this, as shown in FIG. The second second layer aluminum wiring 13B may be connected to the signal line 31. Alternatively, as shown in FIG. 4B, the second first layer aluminum wiring 8 and the second second layer aluminum wiring 1 may be connected.
Both 3B and the third layer aluminum wiring 34 may be connectable to the signal line 31.

In the second embodiment described above, the input line of the standard cell of about 50 μm square is referred to. However, for example, when the deterioration of the gate oxide film does not occur in the wiring of several mm,
As shown in FIG. 5, the input line of the block of the inter-block wiring 35 connecting between the blocks constituted by a plurality of standard cells is configured to pass through the metal wiring of the uppermost layer, whereby all the inputs of the standard cell are input. It is not necessary to use the method of the second embodiment in which the wire is routed through the uppermost metal wiring.

[0034]

As described above, according to the first aspect of the present invention, the metal wiring connected to the gate electrode of the MOS type semiconductor device has the same circuit configuration in the end, but the wiring is used in the plasma process. "Antenna effect", which is short and has a small number of contact holes, which collects charged particles from metal wires and contact parts and deteriorates a small area gate oxide film connected to metal wires. Therefore, a highly reliable semiconductor integrated circuit device can be realized without adding a protection diode that deteriorates the circuit operation speed.

According to the method of manufacturing a semiconductor integrated circuit device of the second aspect of the present invention, charged particles which are generated in a plasma process and are incident on the metal wiring connected to the gate electrode of the MOS semiconductor element are charged particles. After forming the gate oxide film to a predetermined wiring length that does not deteriorate the metal wiring, the metal wiring is routed through the uppermost metal wiring. Therefore, the semiconductor integrated circuit device according to the first aspect of the invention can be reliably manufactured.

Further, according to the method of manufacturing a semiconductor integrated circuit device in accordance with the third aspect of the present invention, the metal wiring connected to the gate electrode which is each input portion of the plurality of standard cells has the uppermost metal in the standard cell. After passing through the wiring, each of the metal wirings connected to the gate electrode is connected by the automatic placement and wiring method. Therefore, the metal wiring has a short wiring length and is routed through the uppermost metal wiring in the standard cell. Therefore, in the plasma process, the wiring length is short and the number of contact holes to be opened is small so that the "antenna effect" does not occur in the plasma process.

Therefore, according to the third aspect of the present invention, a highly reliable semiconductor integrated circuit device can be reliably manufactured without adding a protection diode that deteriorates the circuit operation speed.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a step of a semiconductor integrated circuit device and a method for manufacturing the semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a layout diagram showing a method for manufacturing a semiconductor integrated circuit device according to a second embodiment of the invention.

FIG. 3 is a cross-sectional view showing the method of manufacturing the semiconductor integrated circuit device according to the second embodiment.

FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor integrated circuit device according to the first modification of the second embodiment.

FIG. 5 is a layout diagram showing a method of manufacturing a semiconductor integrated circuit device according to a second modification of the second embodiment.

FIG. 6 is a schematic diagram illustrating a deterioration phenomenon of a gate oxide film that occurs in a plasma process.

FIG. 7 is a cross-sectional view showing a conventional semiconductor integrated circuit device.

[Explanation of symbols]

1 p-type silicon substrate 2 gate oxide film 3 gate electrode 7 first first layer aluminum wiring (metal wiring connected to the gate electrode) 8 second first layer aluminum wiring 10, 11 contact hole 13 second layer aluminum Wiring (uppermost metal wiring) 13A First second-layer aluminum wiring 13B Second second-layer aluminum wiring 34 Third-layer aluminum wiring (uppermost metal wiring)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication H01L 21/90 B 7514-4M 9169-4M H01L 21/82 B

Claims (3)

[Claims] 1. A metal wiring, which is connected to a gate electrode of a MOS type semiconductor element and is not connected to a diffusion layer, has charged particles which are generated in a plasma process and are incident on the metal wiring. A semiconductor integrated circuit device characterized in that a predetermined wiring length is set so as not to deteriorate the gate oxide film, and the metal wiring of the uppermost layer is provided. 2. A gate oxide film of the MOS type semiconductor device, in which charged particles generated in a plasma process generate a metal line connected to a gate electrode of the MOS type semiconductor device but not connected to a diffusion layer and incident on the metal line. Is formed to a predetermined wiring length that does not deteriorate the metal wiring, and the metal wiring is passed through the uppermost metal wiring. 3. A method of manufacturing a semiconductor integrated circuit device, comprising connecting a standard cell group composed of a plurality of standard cells each composed of a plurality of transistors by an automatic placement and routing method, wherein each input of the plurality of standard cells. After the metal wiring connected to the gate electrode, which is a part of the standard cell, is routed through the uppermost metal wiring in the standard cell, each of the metal wiring connected to the gate electrode is connected by the automatic placement and wiring method. A method for manufacturing a semiconductor integrated circuit device, comprising: