JP3350308B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, for example, a nonvolatile semiconductor memory device in which a plurality of memory cells are connected in series or in parallel to form a memory cell unit such as a NAND cell, an AND cell, and a DINOR cell. It relates to a storage device.

[0002]

2. Description of the Related Art Conventionally, as one of the semiconductor memory devices, an electrically rewritable EEPROM has been known. Above all, NAN by connecting a plurality of memory cells in series
NAND cell type EEPROM forming D cell block
Are attracting attention as being capable of high integration because the number of bit line contacts can be reduced.

FIG. 21 shows such a NAND cell type EEP.
FIG. 9 is a circuit configuration of a conventional row decoder of a ROM and an equivalent circuit diagram of a memory cell array.

In FIG. 21, a NAND cell block decode signal and a row decoder start signal RDECD are input from a NAND circuit 1 and a NOT circuit 2 via a NOR circuit 3, and a voltage is switched by a voltage switching circuit 4. The signal is supplied from the voltage switching circuit 4 to the row decoders 5a and 5b via the nodes N1 and N2 and to the memory cell array 6 composed of a plurality of memory cells.

[0005] One memory cell in such a NAND cell type EEPROM has an FETMOS structure in which a floating gate (charge storage layer) and a control gate are stacked on a semiconductor substrate via an insulating film. A plurality of memory cells are connected in series in such a manner that adjacent memory cells share a source and a drain to form a NAND cell, and one end of the NAND cell is used as a unit to form a bit through a select gate transistor. It is connected to the wire. Such NAND cells are arranged in a matrix to form a memory cell array. Note that the memory cell array 6
It is integrated and formed in a p-type substrate or a p-type well.

The other end of the NAND cell is connected to a common source line via a select gate transistor. The control gate of the memory transistor and the gate electrode of the select gate transistor are commonly connected as a control gate line (word line) and a select gate line in the row direction of the memory cell array 6, respectively.

Next, the operation of the NAND cell type EEPROM will be described with reference to FIGS.

FIGS. 22, 23 and 24 are timing charts of data reading, writing and erasing operations using the row decoders 5a and 5b shown in FIG. 21, respectively.

The data writing operation is performed sequentially from the memory cell located farthest from the bit line contact.
A high voltage Vpp is applied to the control gate of the selected memory cell.
(= Approximately 20 V), an intermediate potential VM (= approximately 10 V) is applied to the control gate and select gate of the memory cell on the bit line contact side, and 0 V or intermediate potential is applied to the bit line according to data. The potential VM is applied.

When 0 V is applied to the bit line, the potential is transmitted to the drain of the selected memory cell, and electrons are injected from the drain to the floating gate. As a result, the threshold value of the selected memory cell, which has been set to be negative, is shifted in the positive direction. This state is, for example, “1”. On the other hand, when an intermediate potential is applied to the bit line, electron injection does not occur, so that the threshold value of the memory cell does not change and remains negative. This state is "0".

Data erasure is performed simultaneously on all memory cells in the selected NAND cell block.
That is, all the control gates in the selected NAND cell block are set to 0 V, and the bit line, the source line, the p-type well (or p-type substrate), the control gate in the non-selected NAND cell block and all the selection gates are connected. , High voltage 20
A voltage of about V is applied. Thereby, the selected NAND
In all the memory cells in the cell block, the electrons of the floating gate are emitted to the p-type well (or the p-type substrate), and the threshold voltage is shifted, including the memory cells shifted in the positive direction.
All memory cells are set in the negative direction.

The data read operation is performed by setting the control gate of the selected memory cell to 0 V and setting the control gates and select gates of the other memory cells to the power supply voltage Vcc or a voltage VH higher than the power supply voltage. This is performed by detecting whether or not a current flows in.

FIG. 25 shows an arrangement of traversing wirings of the NAND cell block to the row decoder to the memory cell array when the row decoders 5a and 5b shown in FIG. 21 are used, and a potential state in a read operation of the traversing wirings of the memory cell array. It is shown. FIG. 26 shows the arrangement of the NAND cell block, the row decoder, the memory cell array traversing wiring when the row decoders 5a and 5b shown in FIG. 21 are used, and the potential state at the time of writing and erasing operations of the memory cell array traversing wiring. It is shown.

As can be seen from FIGS. 21, 25 and 26, conventionally, row decoders 5a and 5b are arranged on both left and right sides of the memory cell array 6, and two row decoders 5a and 5b are provided between the left and right sides of the memory cell array 6. The memory cell array transverse wirings (nodes) N1 and N2 are provided.
One of these two crossing lines N1 and N2 is at 0V and the other is at "H (high)" level potential in each NAND cell block. Normally, several hundred NAND cell blocks
Since there are several thousands, the number of wirings at the “H” level potential is also several hundred to several thousand, and accordingly, the load capacitance at the “H” level potential is increased.

Further, a high voltage (V) generated inside the chip
When a voltage (higher than cc) is charged in the transverse wires N1 and N2 of the memory cell array 6, the time required for charging the high voltage is long because the capability of supplying the high voltage is small. Therefore, the operation speed of the operation for performing the high-voltage charging is reduced,
There was a problem that. Further, when the supply capability of the high voltage is increased in order to shorten the high voltage charging time, the pattern area of the high voltage generation circuit increases, and thus the chip size increases.

[0016] Such a problem is caused by EEs other than the NAND type.
The same can occur in a PROM or the like.

[0017]

As described above, the conventional N
In an EEPROM of an AND cell type or the like, there are two transverse lines of a memory cell array per one NAND cell block, and one of the two transverse lines is charged to the "H" level potential. Therefore, when the "H" level potential is a boosted voltage inside the chip higher than Vcc, there is a problem that the time required for charging the boosted voltage becomes longer and the operating speed is reduced.

Further, in order to reduce the time required for charging the boosted voltage, the supply capacity of the boosted voltage is increased.
There is a problem that the chip area increases.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a nonvolatile semiconductor memory device capable of operating at a higher speed than before without increasing the chip area. Is to do.

[0020]

That is, the present invention provides a memory cell array in which a plurality of at least one memory cell is connected, and memory cell blocks including a plurality of word lines are arranged in an array. A column selecting means for selecting a bit line, and a first side of the memory cell and a second side opposite to the first side with the memory cell array interposed therebetween, and
First and second row selection means for selecting as one unit;
A first row selecting means provided for each memory cell block and arranged on a first side of the memory cell array and a second row selecting means arranged on a second side of the memory cell array. A first wiring to be connected and a first potential which is provided on a first side of the memory cell array and is set to a different first potential depending on whether or not a corresponding memory cell block is in a selected state. First potential setting means, second potential setting means provided on the second side of the memory cell array and set to a second potential corresponding to an inverted state of the signal of the first wiring; A second wiring for supplying a second potential to the second row selecting means, wherein the first wiring and the word line are made of wiring materials provided in different wiring layers, respectively. It is characterized by the following.

In the present invention, the number of wirings traversing the memory cell array can be reduced to one per NAND cell block, so that the number of wirings for charging the boosted voltage can be reduced, and therefore the chip size can be almost reduced. The time required for charging the boosted voltage can be shortened without increasing, and the operation speed can be improved.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of a NAND cell type EEPROM system according to an embodiment of the present invention.

In FIG. 2, a bit line control circuit 12 is provided for performing data write, rewrite, write verify read, and erase verify read on the memory cell array 11. This bit line control circuit 12
Are coupled to a data input / output buffer 13 and receive as an input the output of a column decoder 15 that receives an address signal from an address buffer 14.

The memory cell array 11 has a row decoder 16 for controlling a control gate and a selection gate.
And a substrate potential control circuit 17 for controlling the potential of the p-substrate (or p-type well) on which the memory cell array 11 is formed.

The high voltage generation circuit 18 reads, writes,
In order to read, write, and erase data from and to the memory cell 11 during an erasing operation,
This is for generating and supplying a high voltage for writing and erasing. The intermediate potential generating circuit 19 generates and supplies an intermediate potential (> Vcc potential) to be applied to a memory cell, a bit line, or the like during a write operation.

FIGS. 3A and 3B are a plan view of one NAND cell portion of the memory cell array 11 and an equivalent circuit diagram thereof, and FIGS. 4A and 4B respectively show FIGS.
FIG. 2A is a sectional view taken along lines II ′ and II-II ′.

A memory cell array comprising a plurality of NAND cells is formed on a p-type silicon substrate (or p-type well) 21 surrounded by an element isolation oxide film 22. Focusing on one NAND cell, in this embodiment, eight memory cells M _{1 to} M ₈ are connected in series to form one NAND cell.

Each of the memory cells M _{1 to} M ₈ is
1 has a floating gate 24 (2
4 _1, 24 _2, ..., 24 ₈₎ are formed, the control gate 26 (26 ₁ via an interlayer insulating film 25 thereon, 26 _2,
, 26 ₈ ) are formed. The n-type diffusion layers 27 (2
7 ₀ , 27 ₁ ,..., 27 ₁₀ ) are connected so as to be shared by adjacent ones, whereby the memory cells are connected in series.

[0030] The drain side and source side of the NAND cell, the floating gate of the memory cell, the control gate selection formed simultaneously with the gate 24 _9, 26 ₉ and 24 _10, 26
₁₀ are provided respectively. The substrate on which the elements are formed is covered with a CVD oxide film 29 including a later-described transverse wiring 28, and a bit line 30 is provided on the CVD oxide film 29.

The bit line 30 is in contact with the drain diffusion layer 27 at one end of the NAND cell. The control gates 24 of the NAND cells arranged in the row direction share control gate lines CG (1), CG (2),.
It is arranged as. These control gate lines become word lines. Select gate 24 _9, 26 ₉ and 24 _10, 26
₁₀ , the selection gate lines SG ₁ ,
It is arranged as SG _2.

In FIG. 4, the transverse wiring 28 is arranged in the CVD oxide film 29 below the bit line 30. However, if the transverse wiring 28 is arranged in a wiring layer different from the control gate 26. good.

For example, as shown in FIG. 5, the transverse wiring 28 'may be provided in the CVD oxide film 29' on the bit line 30.

The selection gates 24 ₉ and 24 ₁₀ and the substrate 2
1 may be made thicker than the gate insulating film in the memory cell portion to enhance its reliability.

FIG. 6 shows an equivalent circuit of a memory cell array in which such NAND cells are arranged in a matrix.

In the NAND cell type EEPROM, selection and non-selection are performed using a NAND cell block shown by a broken line in FIG. 6 as one unit. Then, in the read operation or the write operation, one of the eight control gates CG (1) to CG (8) in the selected block is selected.
In the erase operation, only selection and non-selection are performed in block units, and eight control gates in the selected block are collectively selected or deselected.

In the following description of the embodiments,
Although the case where CG (3) is selected from the eight control gates in the selected block is taken as an example, the present invention is applicable to a case where any one of the seven control gates other than CG (3) is selected. Is similarly feasible and effective.

FIG. 1 is a circuit configuration of a row decoder and an equivalent circuit diagram of a memory cell array according to an embodiment of the present invention.

In FIG. 1, a NAND cell block decode signal and a row decoder start signal RDECD are input from a NAND circuit 31 and a NOT circuit 32 via a NOR circuit 33, and the voltage is switched by a voltage switching circuit 34.
From the voltage switching circuit 34, the nodes N1 and N2L
And a row decoder 35a having a first complementary signal generator
, And to the row decoder 35b via the node N1. These row decoders 35a and 35b have elements on both left and right sides of a memory cell array 36 composed of a plurality of memory cells.

Each of the row decoders 35a and 35b includes one traversing wire (node) N1 traversing the memory cell array 36 (see also FIGS. 12 and 13). A feature of the circuit configuration of the row decoders 35a and 35b is that the number of wirings traversing the memory cell array 36 is one. Then, in order to realize this one number of wires, the second complementary signal generator 3 is provided on the row decoder 35b side.
7 and a node N2R.

As shown in FIG. 1, the row decoder 35
The elements in a and 35b are arranged on the left and right sides of the memory cell array 36 because the pitch of the control gate lines in the memory cell array 36 is small and the number of elements in a row decoder circuit per control gate line is three. This is because the row decoder circuit cannot be accommodated on only one side of the memory cell array because there are many.

Next, referring to the timing charts of FIGS. 7, 8 and 9, each of the memory cell data read operation, write operation and erase operation realized using the row decoder shown in FIG. explain.

First, the memory cell data read operation timing will be described with reference to the timing chart of FIG. However, the cell p-well node in FIG. 7 represents the potential of the well (or substrate) in which the memory cell is formed.

When the read operation starts, first, the row decoder start signal RDECD becomes Vcc. Then, in the block selected by the row address, the node S1 becomes Vcc, so that the row decoder corresponding to the selected block is activated. That is, the nodes N1, N2R,
N2L becomes Vcc, 0V, and 0V, respectively, and the row decoder enters a selected state.

Next, after the bit line is precharged from 0 V to Vcc, CGDi (Control Gate Drain) (i
= 1, 2, 4-8), SGD (Select Gate Drain),
When the SGS (Select Gate Source) is charged to Vcc, CG (i) (i = 1, 2, 4) in the selected block
8), SG (Select Gate) (1), SG (2)
Charged to cc.

Subsequently, the high voltage generation circuit 18 inside the chip
As a result, a voltage higher than Vcc is generated, and VPPRW, VPPRW,
CGDi (i = 1, 2, 4 to 8), SGD, SGS or node N1, CG (i) (i = 1, 2, 4
8), SG (1), SG (2), etc.
_H (where _VH is higher than Vcc, for example, 4 to 5 V for 3 V of Vcc). This state is maintained for a while.

At this time, if the threshold voltage of the selected memory cell (the memory cell connected to the control gate CG (3)) is positive, no cell current flows through the corresponding NAND cell and the bit line potential becomes The bit line is at the “H” level potential without lowering. If the threshold voltage of the selected memory cell is negative, a cell current flows through the corresponding NAND cell, and the bit line potential drops to the “L (low)” level potential.

Subsequently, CGDi (i = 1, 2, 4-
8), SGD, SGS and CG (i) (i
= 1,2,4~8), SG (1) , after the SG (2) becomes 0V, and the sense bit line potential (part of the T ₁₁ in FIG. 7), the determination of the memory cell data Done.

Next, the generation of the V _H potential by the high voltage generation circuit 18 is stopped, and each node at the V _H potential is set to the Vcc potential. Finally, the row decoder activation signal RDECD is set to 0 V, so that the row decoder is deactivated and the memory cell data read operation ends.

Next, with reference to the timing chart of FIG. 8, a description will be given of a data write operation to a memory cell realized by using the row decoder shown in FIG. However, FIG.
The middle cell p-well node indicates the well (or substrate) potential of the memory cell. The operation timing of FIG. 8 will be described below.

When the write operation starts, first, the row decoder activation signal RDECD becomes Vcc. Then, in the block selected by the row address, the node S1 is connected to Vcc
Therefore, the row decoder corresponding to the selected block is activated. That is, the nodes N1 and N2
R and N2L become Vcc, 0V and 0V, respectively, and the row decoder is in the selected state.

Subsequently, CGDi (i = 1 to 8), SGD
Is charged to Vcc, so that C in the selected block
G (i) (i = 1 to 8) and SG (1) are charged to Vcc. At this time, the bit line connected to the memory cell for writing “0” data (the memory cell that does not change the threshold voltage of the memory cell from the state before the write operation) is also charged to the Vcc potential.

Next, the high voltage generation circuit 18 inside the chip
, A voltage higher than Vcc is generated. VPPRW, VPPRW,
The node N1 in the selected block and the nodes N2R and N2L in the unselected block are charged from Vcc to 20V (where 20V is higher than Vcc). Similarly, a voltage higher than Vcc is generated by the intermediate voltage generation circuit 19 inside the chip. Then, via the voltage output node VM of the intermediate voltage generating circuit 19, CGDi (i =
1,2,4-8), SGD and CG (i) in the selected block
(I = 1, 2, 4 to 8), SG (1) is increased from Vcc by 10
V (10V is higher than Vcc).

Next, when CGD3 is charged from Vcc to 20V, CG (3) in the selected block becomes 20V.
It is charged to V. This state is maintained for a while, and data is written to the selected memory cell.

Thereafter, CGDi (i = 1 to 8), SGD
Is discharged to 0 V, so that C in the selected block is
G (i) (i = 1 to 8) and SG (1) are discharged to 0V. Subsequently, a bit line connected to a memory cell for writing “0” data (a memory cell that does not change the threshold voltage of the memory cell from the state before the write operation) is discharged to 0V. Further, the high voltage generation circuit 18 and the intermediate voltage generation circuit 19
And stop the generation of a voltage higher than Vcc
And the node at 10 V is set to the Vcc potential.

Finally, the row decoder activation signal RDECD
Is set to 0 V, the row decoder is deactivated, and the data write operation to the memory cell is completed.

Next, an operation of erasing data from a memory cell realized by using the row decoder shown in FIG. 1 will be described with reference to a timing chart of FIG. However,
The cell p-well node in FIG. 9 indicates a potential of a well (or a substrate) in which a memory cell is formed. The operation timing of FIG. 9 will be described below.

When the erasing operation starts, first, the row decoder activation signal RDECD becomes Vcc. Then, in the block selected by the row address, the node S1 is connected to Vcc
Becomes Therefore, the row decoder corresponding to the selected block is activated. That is, node N
1, N2R and N2L become Vcc, 0V and 0V, respectively, and the row decoder enters a selected state.

Subsequently, SGD, SGS, SGDS are set to Vcc.
Charge in the selected block
(1), SG (2) is charged to Vcc, SG (1) and SG (2) in the non-selected block become Vcc, and CG (i) in the non-selected block (i = 1 to 8) Is (Vcc-V
_thn ) (where V _thn is the threshold voltage of an n-channel transistor between the SGDS node and CG (i) (i = 1 to 8)). In addition, a cell p-well which is a well (or a substrate) in which a memory cell is formed, a source line cell / source in a memory cell array, and a bit line are charged to the Vcc potential.

Next, the high voltage generation circuit 18 inside the chip
As a result, a voltage higher than Vcc is generated. Then, via the voltage output node VPP of the high voltage generation circuit 18,
VPPRW, SGD, SGDS, cell p-well, cell
Source, bit line, node N1, SG in selected block
(1), SG (2), node N2 in unselected block
R, N2L, SG (1) and SG (2) are each Vcc
To 20V (where 20V is higher than Vcc), and CG (i) (i = 1 to 8) in the non-selected block is
It is charged from cc to (20V-Vthn). This state is maintained for a while, and data in the memory cells in the selected block is erased.

Thereafter, SGD, SGS, SGDS, cell p-well, cell source, and bit line are changed from 20 V to Vcc.
By dropping to about the potential, SG in the selected block
(1), SG (2) and CG (i) (i =
1-8), SG (1) and SG (2) drop to about the Vcc potential.

Subsequently, the generation of a voltage higher than Vcc by the high voltage generating circuit 18 is stopped, and the node at 20 V is set to the Vcc potential. Also, SGD, SGS, SGD
By discharging S, the cell p-well, the cell source, and the bit line to 0 V, SG (1), S
G (2), CG (i) in an unselected block (i = 1 to 8),
SG (1) and SG (2) are discharged to 0V.

Finally, the row decoder activation signal RDECD
Is set to 0 V, the row decoder is deactivated, and the data erase operation ends.

FIG. 10 shows a modification of the circuit configuration of the row decoder and the equivalent circuit of the memory cell array shown in FIG.

The circuit configuration of the row decoder 35b 'shown in FIG. 10 differs from the circuit configuration of the row decoder 35b of FIG. 1 only in the circuit configuration of the potential setting portion of SG (2) in the cell array 36.

In the case where the row decoders 35a and 35b 'of FIG. 10 are used, the potential of each node at the time of the writing operation and the erasing operation is completely different from the case where the row decoders 35a and 35b of FIG. 1 are used. The result is the same as shown in FIGS. 8 and 9, respectively. The operation between the row decoder of FIG. 1 and the row decoder of FIG. 10 differs only during the read operation.

FIG. 11 is a timing chart for explaining a read operation when the row decoders 35a and 35b 'shown in FIG. 10 are used. The timing chart of FIG. 7 differs from the timing chart of FIG. 11 only in the operation of SG (2) in the non-selected block, and the other parts have exactly the same operation timing.

Next, the point that the present embodiment is superior to the conventional example will be described.

FIG. 12 shows a NAND according to the above embodiment.
It shows the arrangement of cell blocks and row decoders and the potential state of the node N1 during a read operation.
FIG. 13 shows the arrangement of the NAND cell blocks and row decoders according to the above embodiment, and the potential state of the node N1 at the time of writing and erasing operations.

FIG. 21 shows a circuit configuration of a conventional row decoder. FIG. 22 shows a conventional operation timing chart at the time of read operation, write operation, and erase operation when the row decoder of FIG. 21 is used. FIG. 23 and FIG. Further, the arrangement of the NAND cell block and the row decoder according to the conventional example, and the node N in the read operation
1. The potential state of the node N2 is shown in FIG.
FIG. 26 shows the arrangement of the AND cell block and the row decoder, and the potential states of the nodes N1 and N2 during the write and erase operations.

In the conventional row decoder, the number of wirings connecting the circuits at the left and right ends of the memory cell array, that is, the number of wirings traversing the memory cell array is two, and the node N
2 is common to the left and right circuits of the memory cell array.
On the other hand, in FIGS. 1 and 10, the wiring to be connected is divided into a node N2R and a node N2L.

When the conventional row decoder shown in FIG. 21 is used, each of the read, write and erase operations requires a shorter operation time than the operations of the circuits having the configurations shown in FIGS. Becomes longer. This is shown in FIG. 7 (T ₁₁ ), FIG.
(T _12), as compared to the duration of the portion of FIG. 9 (T _13), each view 22 (T _1), FIG. 23 (T _2), FIG. 24
This is because the time required for (T ₃ ) is much longer. The reason for this will be described below with reference to FIGS. 12, 13, 25, and 26.
This will be described with reference to FIG.

The conventional row decoder 5 shown in FIG.
When a and 5b are used, the number of wirings traversing the memory cell array 6 is two. These two crossing wires N1, N
2 is 0 V, and the other is at the “H” level potential (V _H
25 and 26 V) (see FIGS. 25 and 26), there is one transverse line of the memory cell array at the “H” level potential in one NAND cell block.
Therefore, it is necessary to charge the transverse wirings of the memory cell array to the “H” level potential by the same number as the number of the NAND cell blocks.

However, since the number of NAND cell blocks is usually several hundred to several thousand, the load capacity of the "H" level voltage is very large. In particular, when the “H” level potential is V
If the "H" level voltage is higher than cc and the "H" level voltage is a voltage generated inside the chip, the supply capability of the "H" level voltage is much smaller than the supply capability of the power supply voltage. The time required to charge the transverse wirings of one hundred to several thousand memory cell arrays is very long. In addition, if the ability to supply a high voltage is increased in order to shorten the required charging time, the pattern area of the high-voltage generating circuit must be significantly increased, and thus the chip area is greatly increased. there were.

On the other hand, when the row decoder having the circuit configuration shown in FIGS. 1 and 10 is used, the memory cell array 36
Is one. The potential of the transverse wiring N1 of the memory cell array 36 is at the “H” level potential (potential such as V _H or 20 V) in the selected block, and is at 0 V in the non-selected block (FIGS. 12 and 13).
Therefore, the number of memory cell array traversing wires at the “H” level potential is the same as the number of selected blocks.

The number of selected blocks is usually one during the read operation and the write operation. Therefore, the memory cell array at the "H" level potential has only one transverse line, and the load capacitance at the "H" level potential is much smaller than when the conventional row decoder shown in FIG. 21 is used. Become.

Even when the "H" level potential is higher than Vcc and the "H" level voltage is a voltage generated inside the chip, the supply capability of the "H" level voltage is higher. Despite being much smaller than the power supply voltage, the load capacity of the “H” level potential is not so large, so the required time for charging the “H” level potential does not become too long. This means that, for example, T ₁₁ in FIG. 7 and T ₁₂ in FIG.
T ₁ of the respective Figure 22, corresponds to substantially shorter than the T ₂ of the Figure 23. Therefore, the time required for the read operation and the write operation can be greatly reduced as compared with the case where the conventional row decoder of FIG. 21 is used.

In the erasing operation, the number of selected blocks is not always limited to one, but may be plural. The number of traversing wirings of the memory cell array charged with a high voltage during the erase operation is the same as the number of selected blocks. Therefore,
The smaller the number of selected blocks, the smaller the high-voltage load capacity, and the shorter the time required for high-voltage charging, that is, the time required for erasing operation.

Actually, when the number of selected blocks is sufficiently smaller than the number of NAND cell blocks, the number of transverse wirings of the memory cell array at the "H" level potential is sufficiently smaller than the number of NAND cell blocks. Therefore, as compared with the case where the row decoder of FIG. 21 is used, the load capacitance of the “H” level potential can be significantly reduced, that is, the time required for charging the “H” level potential can be significantly reduced. This can, for example, T ₁₃ in FIG. 9 is equivalent to considerably shorter than T ₃ in FIG. 23.

When the row decoder having the structure shown in FIGS. 1 and 10 is used, the second complementary signal generator 37 is used as compared with the conventional row decoder circuit shown in FIG.
The number of elements is increased by two elements in the section. However, in the row decoder shown in FIG. 1 and the like, since about 70 elements are included per one NAND cell block, even if the number of elements increases by about 2, the amount of increase in the pattern area does not increase. Very small with respect to the pattern area of the entire row decoder. Therefore, when the conventional row decoder shown in FIG. 21 is used and the row decoder of FIG. 1 is used as compared with the case where the operating speed equivalent to the operating speed when the row decoder of the configuration of FIG. 1 is used. In this case, the increase in the chip area is much smaller.

FIG. 14 shows still another modification of the circuit configuration of the row decoder and the equivalent circuit of the memory cell array shown in FIG.

A row decoder having the structure shown in FIG.
The differences in the circuit configuration of the row decoder having the configuration shown in FIG. 1 are as follows.

That is, in FIG. 14, the NOR circuit 33
A third complementary signal generating section 38 is provided between the first complementary signal generating section 38 and the voltage switching circuit 34. Further, in FIG. 1, CG (i) (i =
14 to 8) are connected via an n-channel transistor from the SGDS, whereas in FIG. 14, the nodes are at 0V.

Here, the signal ERASE in FIG.
Is a signal that goes high during an erase operation and goes low except during an erase operation. Therefore, there is no difference between the case of using the row decoder of FIG. 1 and the case of using the row decoder of FIG. 14 between the read operation and the write operation.

Next, a read operation, a write operation, and an erase operation using the row decoder having the configuration shown in FIG. 14 will be described.

The row decoder 35 having the structure shown in FIG.
a 'and 35b ", the read operation timing and the write operation timing are the same as those of the row decoders 35a and 35b shown in FIG.
Exactly the same as with 5b is obtained. That is,
The read operation timing and the write operation timing when the row decoders 35a 'and 35b "in Fig. 14 are used are the same as those in the timing charts in Fig. 7 and Fig. 8. Similarly, in the read operation and the write operation, respectively. In this case, the potential state of the transverse wiring N1 of the memory cell array 36 in the case where the row decoders 35a and 35b of FIG. 1 are used and the case where the row decoders 35a 'and 35b "of FIG. 14 are used are the same.

That is, the potential state of the transverse wiring N1 of the memory cell array 36 during the read operation and the write operation when the row decoder of FIG. 14 is used is shown in FIG.
2. The state shown in FIG. 13 is obtained. Therefore, by using the row decoder having the configuration shown in FIG.
As in the case where the row decoder having the configuration shown in FIG. 10 or FIG. 10 is used, a high-speed read operation and a high-speed write operation can be realized.

On the other hand, at the time of the erasing operation, the voltage of each section is different between the case where the row decoder having the configuration of FIG. 1 is used and the case where the row decoder having the configuration of FIG. 14 is used.

At the time of the erasing operation, the signal ERASE is set to "H".
Level, the voltage levels of the nodes S1 and S2 become the same. Here, during all operations in the row decoder of FIG. 1 and during operations other than the erase operation in the row decoder of FIG. 14, the voltage levels of the nodes S1 and S2 are different, that is, the voltage levels are in an inverted state. is there.

FIG. 15 is a timing chart showing an erasing operation timing when the row decoder having the configuration shown in FIG. 14 is used.

As can be seen from FIGS. 9 and 15, during the erase operation, the node N1 in FIG. 1 and the node N2 in FIG.
R and the node N2L have the same potential, and the nodes N2R and N2L in FIG. 1 and the node N1 in FIG. 14 have the same potential. Therefore, when the row decoder shown in FIG. 14 is used, as shown in FIG. 16, the potential of the transverse wiring of the memory cell array 36 in the selected block is 0 V, and the potential of the transverse wiring of the memory cell array 36 in the non-selected block is 0. The potential of the wiring is 20V.

Therefore, when the row decoder of FIG. 14 is used, the number of traversing wires of the memory cell array 36 for charging a high voltage is equal to the number of NAND cell blocks−the number of selected blocks. That is, when the row decoder of FIG. 1 is used, the load capacity of high voltage decreases as the number of selected blocks decreases, whereas when the row decoder of FIG. 14 is used, the number of selected blocks increases. The higher the load capacity of high voltage becomes, the smaller the load capacity becomes.

In any case, irrespective of the number of selected blocks, even when the row decoder shown in FIG. 14 is used, compared with the case where the conventional row decoder shown in FIG. 21 is used. In addition, the number of wires for charging the high voltage is reduced, and the load capacity of the high voltage can be reduced. That is, the time required for high-voltage charging can be shortened, and the erasing operation can be speeded up.

In the row decoder shown in FIGS. 1, 10, and 14, the wiring material of the transverse wiring of the memory cell array has a higher resistivity than the wiring material used as the control gate line and the selection gate line. It is desirable to use a wiring material having a low level. The reason will be described below.

The transverse wiring of the memory cell array has a resistance value, and the capacitance includes the gate capacitance of the transistor in addition to the capacitance value of the wiring itself. Therefore, a signal transmission delay occurs on the left and right sides of the transverse wiring N1 of the memory cell array in FIGS. 1, 10, and 14.

In this case, CG (1), CG (3) and CG among the control gate lines in FIGS.
(5) The charge start timing of CG (7) is CG
(2), CG (4), CG (6), and CG (8) are delayed from the charge start timing by the delay time when a signal is transmitted from left to right of the memory cell array traversing wiring. If the delay time is equal to or longer than the delay time at the time of charging / discharging of the control gate line and the selection gate line, the delay time of the memory cell array traversing wiring may cause the operating time to be significantly increased. .

Since the delay time of the transverse wiring can be reduced by reducing the resistance value of the transverse wiring of the memory cell array, it is desirable that the resistance value of the transverse wiring be smaller. As shown in FIG. 3 to FIG. 5, it is difficult to form the memory cell array crossing wiring using the same wiring layer as the control gate lines and the selection gate lines due to the arrangement of the control gate lines and the selection gate lines in the memory cell array portion. You can see that there is.
It is apparent from the drawing that there is no gap for newly adding a wiring of the same wiring layer as the control gate line.

Therefore, the wiring material of the memory cell array crossing wiring is a wiring layer different from the control gate lines and the selection gate lines. Therefore, it is not so difficult to make the resistivity of the wiring material of the memory cell array transverse wiring smaller than the resistance values of the wiring material of the control gate line and the selection gate line. That is, by using a wiring material having a low resistivity, it is possible to reduce the resistance value of the transverse wiring and further reduce the delay time.

However, even in the case where the resistivity of the wiring material of the above-mentioned traverse wiring is substantially equal to or lower than that of the control gate line and the selection gate line, the row decoder having the configuration shown in FIGS. Needless to say, the use of such a device enables the operation to be performed at a higher speed than before.

Although the present invention has been described with reference to the embodiment, the present invention is not limited to the above-described embodiment and can be variously modified.

For example, the second complementary signal generator 37 in the row decoder circuit having the configuration shown in FIGS. 1, 10 and 14 is replaced with the circuits 37 'and 37 "having the configuration shown in FIG. The present invention is also effective when used.

In the above embodiment, the NA
The case where eight memory cells are connected in series between the bit line contact and the source line as the ND cell has been described as an example. However, the number of memory cell arrays connected in series is not eight, but is, for example, 2, 4, 16, 32. , 64, etc., the present invention is similarly applicable.

In the above embodiment, the NAN
Although the description has been made by taking the D cell type EEPROM as an example, the present invention is not limited to the above embodiment, and other devices such as a NOR cell type EEPROM, a DINOR
The present invention can be similarly applied to a cell type EEPROM, an AND cell type EEPROM and the like.

Further, other than the non-volatile memory, for example, N
The present invention is also effective in a DRAM having an AND structure or a cascade structure. In addition, various modifications can be made without departing from the scope of the present invention.

FIG. 18 shows a general NOR cell type EEPR.
FIG. 4 is an equivalent circuit diagram of a memory cell array in the OM. FIG. 19 is an equivalent circuit diagram of a memory cell array in a DINOR cell type EEPROM. This DINOR cell type EEPROM is based on "H. Onoda".
et al. , IEDM Tech. Digest,
1992, p. 599-602 ", the details of which are omitted.

FIG. 20 shows an AND cell type EEPROM.
FIG. 3 shows an equivalent circuit diagram of a memory cell array in M. For details of the AND cell type EEPROM, see “H. Kume et al., IEDM Tec.
h. Digest, 1992, p. 991-993 "
The description is omitted.

The present invention has been described with reference to the embodiment. However, the present invention can be variously modified without departing from the gist thereof.

[0108]

As described above, according to the present invention, in a device having row decoder circuits on both the left and right sides of a memory cell array, the wiring connected to the left and right row decoders and traversing the memory cell array is connected to the cell block 1. Since the number of wirings can be one, the number of wirings for charging a high voltage can be reduced. Therefore, data reading, writing, and
The load capacity of the high voltage generated inside the chip during each erase operation can be reduced, and each data read, write, and erase operation speed can be increased.

[Brief description of the drawings]

FIG. 1 shows a NAND cell type E according to an embodiment of the present invention.
FIG. 3 is a circuit configuration of a row decoder of an EPROM system and an equivalent circuit diagram of a memory cell array.

FIG. 2 shows a NAND cell type EE according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a schematic configuration of a PROM system.

FIGS. 3A and 3B are memory cell arrays 1 of FIG. 2;
FIG. 1 is a plan view of one NAND cell part and an equivalent circuit diagram thereof.

FIGS. 4 (a) and (b) show I- in FIG. 3 (a), respectively.
It is sectional drawing along the I 'line and II-II' line.

FIG. 5 shows one NAND of the memory cell array 11 of FIG. 2;
It is sectional drawing which shows the other example of a cell part.

FIG. 6 is an equivalent circuit diagram of a memory cell array in which NAND cells are arranged in a matrix.

FIG. 7 is a timing chart illustrating data read operation timing according to the embodiment of the present invention.

FIG. 8 is a timing chart illustrating data write operation timing according to the embodiment of the present invention.

FIG. 9 is a timing chart illustrating data erase operation timing according to the embodiment of the present invention.

10 is a diagram showing a modification of the circuit configuration of the row decoder shown in FIG. 1 and an equivalent circuit of the memory cell array.

FIG. 11 shows row decoders 35a and 35 shown in FIG.
6 is a timing chart illustrating a read operation timing when b ′ is used.

FIG. 12 is a diagram showing an arrangement of a NAND cell block, a row decoder, and a memory cell array traversing line and a potential of the memory cell array traversing line during a data read operation according to an embodiment of the present invention;

FIG. 13 is a diagram showing the arrangement of NAND cell blocks, row decoders, and memory cell array traversing wires according to an embodiment of the present invention, and the potential of the memory cell array traversing wires during data write and erase operations.

FIG. 14 is a diagram showing still another modification of the circuit configuration of the row decoder and the equivalent circuit of the memory cell array shown in FIG. 1;

FIG. 15 is a timing chart showing the timing of the erase operation when the row decoder having the configuration shown in FIG. 14 is used.

FIG. 16 is a diagram showing the arrangement of NAND cell blocks, row decoders, and memory cell array traversing lines when the row decoder having the configuration shown in FIG. 14 is used, and the potential state of the memory cell array traversing lines during a data erase operation; It is.

FIG. 17 is a diagram showing another configuration example of the second complementary signal generation unit 37 in the row decoder circuit having the configuration shown in FIGS. 1, 10 and 14;

FIG. 18 is an equivalent circuit diagram of a memory cell array in a general NOR cell type EEPROM.

FIG. 19 is a diagram showing an equivalent circuit diagram of a memory cell array in a DINOR cell type EEPROM.

FIG. 20 is an equivalent circuit diagram of a memory cell array in an AND cell type EEPROM.

FIG. 21 is a circuit configuration of a conventional row decoder of a NAND cell type EEPROM and an equivalent circuit diagram of a memory cell array.

FIG. 22 is a timing chart of a data read operation when the row decoders 5a and 5b shown in FIG. 21 are used.

23 is a timing chart of a data write operation when the row decoders 5a and 5b shown in FIG. 21 are used.

FIG. 24 is a timing chart of a data erase operation when the row decoders 5a and 5b shown in FIG. 21 are used.

FIG. 25 is a diagram showing an arrangement of NAND cell blocks, row decoders, memory cell array traversing lines, and a potential state during a read operation of the memory cell array traversing lines when the row decoders 5a and 5b shown in FIG. 21 are used. It is.

FIG. 26 shows the arrangement of NAND cell blocks, row decoders, memory cell array traversing lines, and the potential states during the writing and erasing operations of the memory cell array traversing lines when the row decoders 5a and 5b shown in FIG. 21 are used. FIG.

[Explanation of symbols]

6, 11, 36 memory cell array, 12 bit line control circuit, 13 data input / output buffer, 14 address buffer, 15 column decoder, 16 row decoder, 17 substrate potential control circuit, 18 high voltage generation circuit,
19: intermediate voltage generation circuit, 21: p-type silicon substrate (p
Type well), 22 ... device isolation oxide film, 23 ... gate insulating film, 24 (24 _1, 24 _2, ..., 24 ₈₎ ... floating gate, 24 _9, 24 _10, 26 _9, 26 ₁₀ ... select gate, 2
5 interlayer insulating film, 26 (26 ₁ , 26 ₂ ,..., 26 ₈ )
... Control gate, 27 (27 ₀ , 27 ₁ , ..., 27 ₁₀ ) ...
n-type diffusion layer, 28 cross-sectional wiring, 29, 29 'CVD oxide film, 30 bit line, 35a, 35a', 35b, 3
5b ', 35b "... Row decoder.

Claims (8)

(57) [Claims] 1. A memory cell array in which a plurality of at least one memory cell is connected and memory cell blocks including a plurality of word lines are arranged in an array, and a column selecting means for selecting a bit line of the memory cell array. A first side which is disposed on a first side of the memory cell and a second side opposite to the first side across the memory cell array, and selects the memory cell block as one unit;
And a second row selecting means, provided for each memory cell block, and provided on a first side of the memory cell array and a first row selecting means provided on a second side of the memory cell array. A first wiring connected between the first and second row selection means, and a first wiring provided on a first side of the memory cell array, depending on whether or not a corresponding memory cell block is in a selected state. Potential setting means for setting the first potential to a different first potential, and a second potential provided on a second side of the memory cell array and corresponding to an inverted state of a signal of the first wiring. A second potential setting means, and a second potential setting means for supplying the second potential to the second row selecting means.
Wherein the first wiring and the word line are made of wiring materials provided in different wiring layers. 2. The nonvolatile semiconductor memory device according to claim 1, wherein a resistivity of a wiring material of said first wiring is lower than a resistivity of a wiring material of said word line. 3. A first operation period in which a first voltage higher than a power supply voltage is input to the first and second row selection means,
2. The nonvolatile semiconductor memory device according to claim 1, wherein one of said first wiring and said second wiring is set to said first voltage in said memory cell block. 4. The memory cell has a charge storage layer laminated on a semiconductor substrate and a control gate, and is electrically rewritable by transfer of charge between the charge storage layer and the semiconductor substrate. The nonvolatile semiconductor memory device according to claim 1, wherein the operation is performed. 5. The nonvolatile semiconductor memory device according to claim 4, wherein said memory cell performs a data rewriting operation during said first operation period. 6. The nonvolatile semiconductor memory device according to claim 1, wherein said memory cell block is a NAND cell formed by connecting a plurality of said memory cells in series. 7. The nonvolatile semiconductor memory device according to claim 1, wherein said memory cell block is an AND cell formed by connecting a plurality of said memory cells in parallel. 8. The nonvolatile semiconductor memory device according to claim 1, wherein said memory cell block is a DINOR cell formed by connecting a plurality of said memory cells in parallel.