JP4422223B2 - IC test equipment - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an IC test apparatus for testing various ICs.
[0002]
[Prior art]
ICs tend to increase in the number of mixed ICs equipped with a logic part and a memory part in the future. In this mixed IC, the number of pins for the memory unit is about several tens of pins, while the number of pins for the logic unit is large, and the total number of pins is, for example, 128 to 256 pins.
[0003]
On the other hand, since the number of pins that can be tested is limited in the IC test apparatus, the number of ICs that can be tested simultaneously is limited by the number of pins of the IC to be tested. For example, according to a 256-pin IC test apparatus, only two 128-pin mixed ICs can be tested simultaneously.
FIG. 4 shows a schematic configuration of a conventional IC test apparatus. In the figure, 11 is a pattern generator, 12 is a timing generator, 13 is a waveform formatter, 14 is a driver, 15 is an IC under test, 16 is a comparator, and 17 is a logical comparator.
[0004]
The pattern generator 11 outputs test pattern data of “1” or “0”. The test pattern data is generated by the waveform formatter 13 in accordance with the timing signal supplied from the timing generator 12 to generate a test pattern signal having an analog actual waveform whose rising and falling timings are defined.
The timing generator 12 is conceptually expressed by a large number of variable delay devices 12A, 12B, 12C... 12F, and appropriately sets a delay time for the plurality of variable delay devices. By giving the clock RATE1 and the clock REFCLK that define the reference phase to each of the variable delay devices 12A to 12F, the clock REFCLK is delayed and output according to each set delay time from the reference phase defined by the clock RATE1. The waveform formatter 13 is controlled using this delay pulse as a timing signal.
[0005]
The waveform formatter 13 includes a waveform generator 13A and an S-R flip-flop 13B. The waveform generator 13A generates a pulse to be applied to the set terminal S and the reset terminal R of the S-R flip-flop 13B by using timing signals having various timings provided from the timing generator 12, and a set to be applied to the set terminal S. The waveform of the test pattern signal is raised to logic H at the timing of the pulse SP, and the waveform of the test pattern signal is lowered to logic L at the timing of the reset pulse RP applied to the reset terminal R. In this way, a test pattern signal for repeating H logic and L logic is output from the SR flip-flop 13B.
[0006]
The test pattern signal output from the S-R flip-flop 13B is supplied to the IC 15 under test through the driver 14.
The response output signal of the IC under test 15 is taken into the logic comparator 17 through the comparator 16. The comparator 16 determines whether or not the logical value of the response output signal output from the IC 15 under test has a normal voltage. When the logic value of the response output signal output from the IC under test 15 does not reach the normal voltage, the logic H indicating the failure is output.
[0007]
The comparison result output from the comparator 16 is taken into the logical comparator 17. The logical comparator 17 compares the response output signal output from the IC 15 under test with the expected value pattern output from the pattern generator 11 to detect the occurrence of mismatch. When the occurrence of mismatch is detected, the IC is determined to be defective. Although not particularly shown in FIG. 4, a failure analysis memory is provided. When a mismatch occurs, the address where the mismatch occurs, a test pattern, and the like are stored and used for failure analysis.
[0008]
The configuration shown in FIG. 4 is a configuration required to test one pin of the IC 15 under test. Actually, for example, about 256 units UN having such a configuration are prepared, and using these 256 units UN, for example, two IC pins 15 to be tested having 128 pins are tested simultaneously.
[0009]
[Problems to be solved by the invention]
As described above, the number of ICs that can be tested by the IC test apparatus is limited by the number of IC pins. That is, when testing an IC with a large number of pins, the number of ICs that can be tested simultaneously is limited to a small number. If a large number of ICs can be tested at the same time, the processing capability can be improved and the throughput can be improved.
[0010]
However, conventionally, the number of pins that can be tested in one IC test device is limited to about 256 pins or 512 pins for the reason described above, so a large number of ICs can be tested at one time. It is not possible.
Further, if an IC test apparatus capable of simultaneously testing a large number of multi-pin ICs is to be configured, the number of units UN must be increased. The economic burden is significant.
[0011]
An object of the present invention is to provide an IC test apparatus capable of doubling the number of ICs that can be tested at one time while suppressing an increase in cost.
[0012]
[Means for Solving the Problems]
In the present invention, a configuration capable of supplying test pattern signals to a plurality of ICs for each unit is added, and an IC test apparatus capable of doubling the number of testable ICs without increasing the number of units UN. Is to provide.
For this reason, in the present invention, a first switching circuit and a second switching circuit are provided in the subsequent stage of the waveform formatter and the input side of the logical comparator, respectively, and the test pattern signal output from the waveform formatter by the first switching circuit is provided. In synchronization with the test cycle, time-division is distributed to a plurality of ICs to be tested, and the same test pattern is given to the plurality of ICs to be tested by shifting the time by the test cycle.
[0013]
The second switching circuit inputs the response output signals output from the plurality of ICs to be tested to the logic comparator while shifting the time by the test time, and performs the logic comparison by time division.
Therefore, according to the present invention, the number of ICs that can be tested simultaneously can be doubled without increasing the number of units. When a test pattern is given to N ICs per unit, the number of ICs that can be tested is N times.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows an embodiment of the present invention. Parts corresponding to those in FIG. 4 are denoted by the same reference numerals. The feature of the present invention is that the first switching circuit 21 is provided at the subsequent stage of the waveform generating unit 13A, and the second switching circuit 22 is provided on the input side of the logic comparator 17.
[0015]
The embodiment shown in FIG. 1 shows a case where two ICs 15A and 15B can be tested using a unit UN for one pin. For this purpose, the first switching circuit 21 is composed of two gate circuits 21A and 21B that alternately open and close the two gates G1 and G2, and each of the gates G1 and G2 of the two gate circuits 21A and 21B. For example, set pulses SP1 and SP2 output by the waveform generator 13A by alternately opening and closing are alternately supplied to the set terminals S of the two SR flip-flops 13B and 13C by one gate circuit 21A (see FIGS. 2F and H). The reset pulses RP1 and RP2 output from the waveform generator 13A are alternately input to the reset terminals R of the two SR flip-flops 13B and 13C (see FIGS. 2G and I) by the other gate circuit 21B.
[0016]
The switching of the gates of these gate circuits 21A and 21B is executed periodically in accordance with the internal rate clock RATE2 (see FIG. 2C) that serves as a reference for the test cycle. By alternately setting and resetting the S-R flip-flops 13B and 13C, the ICs 15A and 15B to be tested are given the same test pattern at different times as shown in FIGS. The second switching circuit 22 alternately takes the determination results of the comparators 16A and 16B into the logical comparator 17, and compares the two ICs 15A and 15B under the same condition by comparing them with the same expected value pattern by the logical comparator 17. Can be tested.
[0017]
The external rate clock RATE1 shown in FIG. 2A indicates a rate clock that defines the cycle of the test pattern signal output from the driver 14A. In this embodiment, the internal rate clock RATE2 is a clock that changes at twice the speed of the external rate clock RATE1, and the S-R flip-flops 13B and 13C are operated at twice the normal speed to perform the same test as before. Twice as many ICs can be tested in time. Therefore, the throughput can be improved by a factor of two.
[0018]
FIG. 3 shows a modified embodiment of the present invention. In this embodiment, an OR gate 24 is provided on the output side of the switching control unit 23, and “1” logic is forcibly input to the OR gate 24 from a logic memory 25 such as a flip-flop or a register, whereby the first switching circuit 21. The second switching circuit 22 is fixed to one switching state, and a test pattern can be given to one IC 15A per unit UN.
[0019]
In this mode, since the test pattern is output at the cycle of the internal rate clock RATE2, the test can be performed at a speed twice as high as the conventional test cycle.
By adding this configuration, when testing a high-speed IC, one IC is used per unit. For an IC that does not require high-speed, the logic memory 25 can store “0” logic from one unit. Test patterns can be supplied to a plurality of ICs in a time-sharing manner, and throughput can be improved.
[0020]
【The invention's effect】
As described above, according to the present invention, each unit is used in a time-sharing manner so that test pattern signals are distributed to a plurality of ICs and a plurality of ICs can be tested simultaneously. Only the first switching circuit 21, the second switching circuit 22, and the switching control unit 23 can be added. Therefore, the number of ICs that can be tested at the same time can be doubled with a slight increase in cost, and the effect is very large for practical use.
[0021]
In the above-described embodiment, the configuration in which the test pattern signal is supplied to the two ICs by the unit for one pin has been described. However, the test pattern signal is supplied to the N ICs by the unit for one pin. You can also In this case, it is necessary to increase the operation speed N times in any of the pattern generator 11, the timing generator 12, and the waveform format 13, but the cost for that can be increased only slightly.
[Brief description of the drawings]
FIG. 1 is a block diagram for explaining an embodiment of the present invention.
FIG. 2 is a timing chart for explaining the operation of FIG. 1;
FIG. 3 is a block diagram for explaining a modified embodiment of the present invention.
FIG. 4 is a block diagram for explaining a conventional technique.
[Explanation of symbols]
UN unit 11 pattern generator 12 timing generator 13 waveform formatter 14 driver 15 IC under test
16 comparator 17 logic comparator 21 first switching circuit 22 second switching circuit 23 switching control unit

Claims (2)

A. A pattern generator for generating test pattern data;
B. A timing generator for generating various timing signals;
C. A waveform generator that generates a set pulse and a reset pulse based on test pattern data and timing signals output from the pattern generator and the timing generator;
D. First switching means for providing the set pulse and the reset pulse output by the waveform generation unit in a time-sequential manner to a plurality of flip-flops in synchronization with the test cycle;
E. The flip-flop that receives the set pulse and the reset pulse and outputs a test pattern;
F. A plurality of drivers for supplying a test pattern signal output from each flip-flop to the IC under test;
G. A plurality of comparators for comparing the response output signals output from the plurality of ICs to be tested with a predetermined voltage and outputting the comparison results;
H. Second switching means for selectively giving the outputs of the plurality of comparators to the logic comparator in synchronization with the test period;
I. The logical comparator for determining whether the output signal of the second switching means matches a predetermined expected value;
An IC test apparatus characterized by comprising:   2. The IC test apparatus according to claim 1, wherein a fixing signal is forcibly given to the first switching circuit and the second switching circuit, the first switching circuit and the second switching circuit are fixed at a fixed switching position, An IC test apparatus comprising means for switching to a state in which a test pattern is supplied to the IC.

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