JP4526176B2 - IC test equipment - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an IC test apparatus, and more particularly to an IC test apparatus that can easily cope with an output cycle shift of a device under measurement without rewriting an expected value pattern.
[0002]
[Prior art]
In order to confirm whether or not an IC (integrated circuit) operates according to a predetermined function, a function test is performed by an IC test apparatus such as ATE. In the function test, a test pattern is sequentially applied to the input terminal of the device under test, and a comparison check is performed to determine whether the pattern appearing at the output terminal is as expected.
[0003]
Here, a basic configuration example of a conventional IC test apparatus will be described with reference to FIG. A conventional IC test apparatus includes a test pattern generation unit 1, a timing generator 3, and a logic comparison circuit 2 as basic components in order to test a device under measurement (DUT) 4.
[0004]
The test pattern generator 1 expects data to be output when the drive pattern (input signal data group) S1 input to the DUT 4 and the DUT 4 to which the drive pattern S1 is input operate according to a predetermined function. A value pattern (output signal data group) S2 is generated.
The logic comparison circuit 2 compares the output data S4 of the IC to which the drive pattern S1 is input with the expected value pattern S2, and determines whether the IC is good or bad.
[0005]
In comparison, the output value corresponding to the same signal in the drive pattern S1 must be compared with the expected value. On the other hand, there is a time lag after the signal of the drive pattern S1 is input to the IC until the output data S4 corresponding to the signal is output.
Therefore, the strobe signal S3 is generated from the expected value pattern S2 by the timing generator 3, and the logic comparison circuit 2 compares the output data S4 and the expected value pattern S2 at the timing defined by the strobe signal S3.
[0006]
[Problems to be solved by the invention]
By the way, the output data of the IC which is the device under measurement may cause a cycle shift. In this case, the cycle in which the output value and the expected value corresponding to the same signal in the drive pattern are input to the logic comparison circuit is shifted. As a result, even if the comparison is performed at the timing defined by the strobe, it is difficult to perform a correct comparison. For this reason, conventionally, the expected value pattern has to be rewritten in accordance with the cycle shift of the output data.
[0007]
In the comparison circuit of the IC test system described in JP-A-9-5394, only the expected value signal input to the comparison circuit is cycle-shifted by the expected value cycle shift circuit. There is room for improvement because the cycle is not shifted.
[0008]
The present invention has been made to solve the above-described problem, and even when a cycle shift occurs in output data of a device under measurement, an IC test apparatus that can easily cope with a test pattern without rewriting. The purpose is to provide
[0009]
[Means for Solving the Problems]
In order to achieve this object, according to the IC test apparatus of the present invention , a test pattern generator that generates a drive pattern and an expected value pattern, a timing generator that receives the expected value pattern and outputs a strobe signal, An IC test apparatus including a logic comparison circuit that compares output data of an IC to which a drive pattern is input with an expected value pattern at a timing specified by a strobe signal and determines whether the IC is good or bad,
A cycle shift unit is provided for shifting the expected value pattern input to the timing generator and the logic comparison circuit by the same number of cycles.
[0010]
Thus, according to the IC test apparatus of the present invention, the cycle shift unit is provided. For this reason, when the output data of the IC which is the device under test causes a cycle shift, the expected value pattern can be cycle-shifted in accordance with the cycle shift. As a result, it is possible to easily cope with a cycle shift without rewriting the test pattern.
[0011]
In particular, by shifting not only the expected value pattern input to the logic comparison circuit but also the expected value pattern input to the timing generator by the same number of cycles, the strobe signal can also be shifted by the same number of cycles. As a result, even when the cycle shift is performed, the output data and the expected value data can be compared with accurate timing.
[0012]
According to the present invention, the cycle shift unit includes a plurality of flip-flops and an expected value pattern that does not pass through the flip-flops, or a multiplexer that selectively outputs the output of any flip-flop. is there. With such a configuration, the expected value pattern can be shifted by a desired cycle with a simple configuration.
[0013]
When the expected value pattern to be input to the logical comparison circuit and the expected value pattern to be input to the timing generator are shifted by the individual cycle shift units, each cycle shift unit starts from the flip flip of the same number of stages. These outputs may be selected by a multiplexer.
[0014]
By the way, when the expected value pattern is cycle-shifted, the expected value pattern for the first number of shift cycles output from the cycle shift unit is not the expected value pattern input from the test pattern generating unit. For example, as the first several cycles, the last part of the remaining pattern used at the previous IC test may be output first. As a result, it is difficult for the logical comparison circuit to accurately compare the expected value pattern with the output data.
[0015]
Therefore, according to the present invention, the cycle shift unit is configured to reset the first output for the number of cycles shifted when the expected value pattern is cycle shifted.
If the first output is reset in this way, the expected value pattern for the first number of shift cycles becomes an invalid pattern. As a result, in the logic comparison circuit, the first output is not compared. For this reason, an accurate comparison between the original base value pattern and the output data can be performed.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[First embodiment]
First, as a first embodiment, a basic configuration example of an IC test apparatus according to the present invention will be described with reference to FIG. The IC test apparatus according to the first embodiment includes a cycle shift unit 5 in addition to the test pattern generation unit 1, the timing generator 3, and the logic comparison circuit 2 in order to test the IC 4 as a measurement target device (DUT). ing.
[0017]
The test pattern generator 1 generates a drive pattern S1 and an expected value pattern S2, respectively. The timing generator 3 to which the expected value pattern S2 is input outputs a strobe signal S3. Then, the logic comparison circuit 2 compares the output data S4 of the IC4 to which the drive pattern S1 is input with the expected value pattern S2 at the timing defined by the strobe signal S3, and determines whether the IC4 is good or bad.
[0018]
Further, as shown in FIG. 1, in this embodiment, cycle shift units 5 are provided on signal paths from the test pattern generation unit 1 to the logic comparison circuit 2 and the timing generator 3, respectively.
Here, FIG. 2 shows a configuration of each cycle shift unit 5.
The circuit configuration of each cycle shift unit 5 is the same.
[0019]
As shown in FIG. 2, the cycle shift unit 5 includes a plurality of stages of flip-flops 51 and a multiplexer 52. Then, the expected value pattern that does not pass through the flip-flop 51 or the output of one of the flip-flops 51 is selectively output by the multiplexer 52.
[0020]
In each cycle shift unit 5, the expected value pattern S2 input to the timing generator 3 and the expected value pattern S2 input to the logic comparison circuit 2 are matched with the cycle shift of the output data S4 of the IC4, Shift by the same number of cycles. That is, in each cycle shift unit 5, the multiplexer 52 selects the output from the flip flip 51 having the same number of stages.
[0021]
In this way, not only the expected value pattern S2 input to the logic comparison circuit 2 but also the expected value pattern S2 input to the timing generator 3 can be shifted by the same number of cycles. For this reason, the strobe signal S3 can also be shifted by the same number of cycles. As a result, even when the expected value pattern S2 is cycle-shifted, the output data and the expected value data can be compared with accurate timing. As a result, it is possible to easily cope with a cycle shift without rewriting the test pattern.
[0022]
Furthermore, in this embodiment, when the expected value pattern S2 is cycle-shifted, each cycle shift unit 5 resets the first output for the number of cycles shifted. Specifically, each cycle shift unit 5 resets each flip-flop 5 by the number of shift cycles.
If the first output is reset in this way, the expected value pattern for the first number of shift cycles becomes an invalid pattern and is not compared in the logic comparison circuit 2. As a result, even when the cycle shift is performed, the comparison can be performed accurately.
[0023]
[Second Embodiment]
Next, as a second embodiment, a specific configuration example of the IC test apparatus of the present invention will be described with reference to FIG.
In FIG. 3, illustration of the DUT 4 shown in FIG. 1 and the signal paths of the drive pattern S1 and the output data S4 is omitted.
[0024]
In the second embodiment, the test pattern generation unit 1 is configured by “ExpH” and “ExpL”. An expected value pattern ExpH is output from “ExpH”, and an expected value pattern ExpL is output from “ExpL”. In addition, an expected value pattern OpenH is generated from ExpH via an inverter, and an expected value pattern OpenL is generated from ExpL via an inverter.
[0025]
Each expected value pattern ExpH, ExpL, OpenH, and OpenL is input to the logic comparison circuit 2 via the cycle shift unit 5. The configuration of each cycle shift unit 5 is the same as the configuration of the cycle shift unit 5 in the first embodiment shown in FIG.
[0026]
Further, as shown in FIG. 1, the expected value patterns OpenH and OpenL are input to the timing generator 3 via the cycle shift unit 5. Each timing generator 3 delays the expected value pattern by the delay signal (RATE), and further synchronizes with the reference clock signal (CLK) and outputs it as the strobe signal S3. The strobe signal S3 is input to the logic comparison circuit 2.
[0027]
Also in the second embodiment, as in the first embodiment, each cycle shift unit 5 shifts the expected value pattern by the same number of cycles according to the cycle shift of the output data of the DUT. As a result, the strobe signal S3 can also be shifted by the same number of cycles as the expected value signal S2. As a result, it is possible to easily cope with a cycle shift without rewriting the test pattern.
[0028]
[Third embodiment]
Next, a third embodiment of the present invention will be described with reference to FIG.
The configuration of the IC test apparatus in the third embodiment is the same as the configuration of the IC test apparatus in the first embodiment shown in FIG. 1 except for the arrangement of the cycle shift unit 5, and thus detailed description thereof is omitted. To do.
[0029]
As shown in FIG. 4, the single cycle shift unit 5 is provided in the IC test apparatus of the third embodiment. The expected value data S2 output from the single cycle shift unit 5 is input to the logic comparison circuit 2 and the timing generator 3, respectively.
[0030]
In this way, if the expected value pattern S2 is cycle-shifted by the single cycle shift unit 5, the expected value pattern S2 input to the timing generator 3 and the logic comparison circuit 2 is reliably shifted by the same number of cycles. be able to.
Moreover, since the cycle shift unit 5 is single, the apparatus configuration can be simplified.
[0031]
In the above-described embodiment, the example in which the present invention is configured under specific conditions has been described. However, the present invention can be variously modified. For example, in the above-described embodiment, an example in which three stages of flip-flops are provided for the cycle shift has been described. However, in the present invention, the number of flip-flop stages, that is, the maximum number of cycles that can be shifted is not limited to this. .
[0032]
Further, the configuration of the cycle shift unit is not limited to the flip-flop and the multiplexer. For example, a serial input / parallel output shift register may be used instead of the flip-flop.
[0033]
【The invention's effect】
As described above in detail, according to the present invention, the cycle shift unit is provided. For this reason, when the output data of the IC, which is the device under test, undergoes a cycle shift, the expected value pattern can be cycle shifted in accordance with the cycle shift. As a result, it is possible to easily cope with a cycle shift without rewriting the test pattern.
[0034]
In particular, by shifting not only the expected value pattern input to the logic comparison circuit but also the expected value pattern input to the timing generator by the same number of cycles, the strobe signal can also be shifted by the same number of cycles. As a result, even when the cycle shift is performed, the output data and the expected value data can be compared with accurate timing.
[Brief description of the drawings]
FIG. 1 is a block diagram for explaining a basic configuration of an IC test apparatus according to a first embodiment.
FIG. 2 is a block diagram for explaining a configuration of a cycle shift unit.
FIG. 3 is a circuit diagram for explaining a main configuration of an IC test apparatus according to a second embodiment.
FIG. 4 is a block diagram for explaining a basic configuration of an IC test apparatus according to a third embodiment.
FIG. 5 is a block diagram for explaining the configuration of a conventional IC test apparatus.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Test pattern generation part 2 Logic comparison circuit 3 Timing generator 4 DUT
5 cycle shift unit 51 flip-flop 52 multiplexer

Claims (3)

A test pattern generator for generating a drive pattern and an expected value pattern;
A timing generator that receives the expected value pattern and outputs a strobe signal;
An IC test apparatus comprising a logic comparison circuit that compares output data of an IC to which the drive pattern is input with the expected value pattern at a timing defined by the strobe signal and determines whether the IC is good or bad. And
A cycle shift unit for shifting the expected value pattern input to the timing generator and the logic comparison circuit by the same number of cycles ;
The cycle shift unit is provided on a signal path from the test pattern generation unit to the logic comparison circuit and the timing generator, and shifts an expected value pattern before being input to the timing generator and the logic comparison circuit. IC test equipment characterized by the above. The cycle shift unit is
A multi-stage flip-flop;
The IC test apparatus according to claim 1, comprising an expected value pattern that does not pass through the flip-flop, or a multiplexer that selectively outputs an output of any one of the flip-flops. The IC test apparatus according to claim 1, wherein the cycle shift unit resets initial outputs for the number of cycles shifted when the expected value pattern is cycle-shifted.

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