JP4354663B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device that dynamically stores data using a channel body of a transistor as a storage node.
[0002]
[Prior art]
In a conventional DRAM, a memory cell is composed of a MOS transistor and a capacitor. The miniaturization of DRAM is greatly advanced by adopting a trench capacitor structure or a stacked capacitor structure. Currently, the unit memory cell size (cell size) is 2F × 4F = 8F, where F is the minimum processing dimension. ² It has been reduced to the area of. That is, the minimum processing dimension F becomes smaller with the generation, and the cell size is generally set to αF. ² , The coefficient α becomes smaller with the generation, and α = 8 is realized at present when F = 0.18 μm.
[0003]
[Problems to be solved by the invention]
In order to secure the same cell size or chip size trend as before, it is required to satisfy α <8 when F <0.18 μm, and α <6 when F <0.13 μm. How to form a cell size in a small area along with processing becomes a big problem. Therefore, the memory cell of 1 transistor / 1 capacitor is 6F ² And 4F ² Various proposals have been made to make the size of. However, there are technical difficulties such as having to make the transistor vertical, problems such as increased electrical interference between adjacent memory cells, and difficulties in manufacturing technology such as processing and film generation, and practical application is not easy. Absent.
[0004]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor memory device capable of dynamically storing data using a memory cell having a simple transistor structure.
[0005]
[Means for Solving the Problems]
A semiconductor memory device according to the present invention is a semiconductor memory device having a plurality of MIS transistors for constituting a memory cell, and each MIS transistor includes:
A semiconductor layer;
A source region formed in the semiconductor layer;
A drain region formed apart from the source region in the semiconductor layer, wherein the semiconductor layer between the source region and the drain region becomes a channel body in a floating state; and
A first gate for forming a channel in the channel body;
A second gate for controlling the potential of the channel body by capacitive coupling;
A high concentration region formed on the second gate side of the channel body, the high concentration region having the same conductivity type as the channel body and having an impurity concentration higher than the impurity concentration of the channel body;
With
The MIS transistor dynamically stores a first data state in which the channel body is set to a first potential and a second data state in which the channel body is set to a second potential.
It is characterized by that.
[0006]
Further, a semiconductor memory device according to the present invention is a semiconductor memory device having a plurality of MIS transistors for constituting a memory cell, and each MIS transistor includes:
A semiconductor layer;
A source region formed in the semiconductor layer;
A drain region formed apart from the source region in the semiconductor layer, wherein the semiconductor layer between the source region and the drain region becomes a channel body in a floating state; and
A first gate for forming a channel in the channel body;
With
The first gate is disposed so that the amount of overlap with the source region is positive and the amount of overlap with the drain region is negative, and the first gate is offset with respect to the drain region. ,
A drain region of the MIS transistor is connected to a bit line; a first gate of the MIS transistor is connected to a first word line; and a source region of the MIS transistor is connected to a source line;
The source region and the drain region are composed of an n-type semiconductor layer, and the channel body between the source region and the drain region is composed of a p-type semiconductor layer,
With the source line potential fixed at 0V, the first word line is set to a positive potential and the bit line is set to a positive potential, thereby writing the first data state to the MIS transistor; The apparatus further comprises writing means for writing the second data state to the MIS transistor by setting the first word line to a positive potential and the bit line to a negative potential.
[0007]
A semiconductor memory device according to the present invention is a semiconductor memory device having a plurality of MIS transistors for constituting a memory cell, and each MIS transistor includes:
A semiconductor layer;
A source region formed in the semiconductor layer;
A drain region formed apart from the source region in the semiconductor layer, wherein the semiconductor layer between the source region and the drain region becomes a channel body in a floating state; and
A gate for forming a channel in the channel body;
With
A drain region of the MIS transistor is connected to a bit line, a gate of the MIS transistor is connected to a word line, and a source region of the MIS transistor is connected to a source line;
The source region and the drain region are composed of an n-type semiconductor layer, and the channel body between the source region and the drain region is composed of a p-type semiconductor layer,
The first data state is written to the MIS transistor by setting the word line to a negative potential and the bit line to a positive potential in a state where the potential of the source line is fixed at 0V, and the word line A writing means for writing the second data state to the MIS transistor by setting the bit line to a negative potential and the bit line to a negative potential;
It is characterized by that.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0009]
[Basic concept]
FIG. 1 shows a basic sectional structure of a unit memory cell MC of a DRAM according to each embodiment described later, and FIG. 2 shows an equivalent circuit thereof. The memory cell MC is composed of an N-channel MIS transistor having an SOI structure. That is, an SOI substrate in which a silicon oxide film 11 is formed as an insulating film on a silicon substrate 10 and a p-type silicon layer 12 is formed on the silicon oxide film 11 is used. A gate electrode 13 is formed on the silicon layer 12 of this substrate via a gate oxide film 16, and n-type source / drain diffusion layers 14 and 15 are formed in self-alignment with the gate electrode 13.
[0010]
The sources and drains 14 and 15 are formed to a depth reaching the bottom silicon oxide film 11. Therefore, if the channel body made of the p-type silicon layer 12 is separated by an oxide film in the channel width direction (direction perpendicular to the drawing sheet), the bottom surface and the side surface in the channel width direction are insulated from each other, The channel length direction is a floating state with pn junction separation.
[0011]
When the memory cells MC are arranged in a matrix, the gate 13 is connected to the word line WL, the source 15 is connected to a fixed potential line (ground potential line), and the drain 14 is connected to the bit line BL.
[0012]
FIG. 3 shows a layout of the memory cell array, and FIGS. 4A and 4B show AA ′ and BB ′ cross sections of FIG. 3, respectively. The p-type silicon layer 12 is patterned in a lattice pattern by embedding the silicon oxide film 22. That is, two transistor regions sharing the drain are arranged in the direction of the word line WL while being separated by the silicon oxide film 22. Alternatively, the element isolation in the lateral direction may be performed by etching the silicon layer 12 instead of embedding the silicon oxide film 22. The gate 13 is continuously formed in one direction, and this becomes the word line WL. The source 15 is continuously formed in the direction of the word line WL and becomes a fixed potential line (common source line).
[0013]
The transistor is covered with an interlayer insulating film 23, and a bit line BL is formed thereon. The bit line BL is disposed so as to contact the drain 14 shared by the two transistors and cross the word line WL. In order to reduce the wiring resistance of the fixed potential line (common source line) of the source 15, a metal wiring parallel to the word line WL is formed above or below the bit line BL, and this is formed for each of a plurality of bit lines. It may be connected to a fixed potential line.
[0014]
As a result, the silicon layer 12 which is the channel body of each transistor is kept in a floating state by separating the bottom surface and the side surface in the channel width direction from each other by the oxide film and from each other by the pn junction in the channel length direction.
[0015]
In this memory cell array configuration, assuming that the word lines WL and the bit lines BL are formed at a pitch of the minimum processing dimension F, the unit cell area is 2F × 2F = 4F as shown by the broken line in FIG. ² It becomes.
[0016]
The operation principle of the memory cell MC composed of the n-channel type MIS transistor utilizes accumulation of holes which are majority carriers in the channel body of the MIS transistor (p-type silicon layer 12 insulated and isolated from others). That is, by operating the transistor in the pentode region, a large current flows from the drain 14 and impact ionization occurs in the vicinity of the drain 14. Holes, which are majority carriers generated by this impact ionization, are held in the p-type silicon layer 12, and the hole accumulation state is, for example, data “1”. Data “0” is defined as a state in which the pn junction between the drain 14 and the p-type silicon layer 12 is forward-biased and excessive holes in the p-type silicon layer 12 are discharged to the drain side.
[0017]
Data “0” and “1” are stored as a difference in channel body potential, and thus as a threshold voltage difference between transistors. That is, the threshold voltage Vth1 in the data “1” state in which the potential of the channel body is high due to hole accumulation is lower than the threshold voltage Vth0 in the data “0” state. In order to maintain the “1” data state in which holes, which are majority carriers, are stored in the body, it is necessary to apply a negative bias voltage to the word line. In theory, this data holding state does not change even if the read operation is performed as long as the read operation is performed in the linear region and the reverse data write operation (erase) is not performed. That is, unlike a one-transistor / one-capacitor DRAM that uses capacitor charge storage, non-destructive readout is possible.
[0018]
There are several possible methods for reading data. The relationship between the word line potential Vwl and the channel body potential VB is as shown in FIG. 5 in relation to the data “0” and “1”. Therefore, in the first method of reading data, a read potential that is intermediate between the threshold voltages Vth0 and Vth1 of the data “0” and “1” is applied to the word line WL, and current flows in the memory cell of “0” data. The fact that the current flows in the memory cell of “1” data is used. Specifically, for example, the bit line BL is precharged to a predetermined potential VBL, and then the word line WL is driven. Thereby, as shown in FIG. 6, in the case of “0” data, there is no change in the bit line precharge potential VBL, and in the case of “1” data, the precharge potential VBL decreases.
[0019]
The second read method utilizes the fact that the rising speed of the bit line potential varies depending on the conductivity of “0” and “1” by supplying current to the bit line BL after the word line WL is raised. To do. Briefly, the bit line BL is precharged to 0V, the word line WL is raised as shown in FIG. 7, and a bit line current is supplied. At this time, it is possible to discriminate data by detecting the difference in potential rise of the bit line using the dummy cell.
[0020]
The third reading method is a method of reading a difference between bit line currents different between “0” and “1” when the bit line BL is clamped to a predetermined potential. In order to read out the current difference, a current-voltage conversion circuit is required. Finally, the potential difference is differentially amplified to output a sense output.
[0021]
In the present invention, in order to selectively write "0" data, that is, holes are emitted only from the channel body of the memory cell selected by the potential of the word line WL and bit line BL selected in the memory cell array. In this case, capacitive coupling between the word line WL and the channel body becomes essential. When holes are accumulated in the channel body with data “1”, the word line is sufficiently biased in the negative direction, and the gate-channel body capacitance of the memory cell becomes the gate oxide film capacitance (that is, the surface is depleted). It is necessary to hold in a state in which no layer is formed.
[0022]
In the write operation, both “0” and “1” preferably reduce power consumption as pulse write. When “0” is written, a hole current flows from the channel body to the drain of the selection transistor and an electron current flows from the drain to the channel body, but holes are not injected into the channel body.
[0023]
More specific operation waveforms will be described. 8 to 11 show operation waveforms of read / refresh and read / write in the case of using the first read method in which data is discriminated based on the presence / absence of discharge of the bit line by the selected cell.
[0024]
8 and 9 show read / refresh operations of “1” data and “0” data, respectively. Until time t1, the data is held (non-selected state), and a negative potential is applied to the word line WL. At time t1, the word line WL is raised to a predetermined positive potential. At this time, the word line potential is set between the threshold values Vth0 and Vth1 of “0” and “1” data. As a result, in the case of “1” data, the bit line VBL precharged in advance becomes a low potential by discharging. In the case of “0” data, the bit line potential VBL is held. Thereby, “1” and “0” data are discriminated.
[0025]
At time t2, the potential of the word line WL is further increased. At the same time, when the read data is “1”, a positive potential is applied to the bit line BL (FIG. 8), and when the read data is “0”. A negative potential is applied to the bit line BL (FIG. 9). As a result, when the selected memory cell is “1” data, a large channel current flows due to the pentode operation, impact ionization occurs, excessive holes are injected and held in the channel body, and “1” data is written again. In the case of “0” data, the drain junction becomes a forward bias, and “0” data in which excess holes are not held in the channel body is written again.
[0026]
At time t3, the word line WL is biased in the negative direction, and the read / refresh operation is terminated. In other unselected memory cells connected to the same bit line BL as the memory cell from which “1” data is read, the word line WL is held at a negative potential, and therefore the channel body is held at a negative potential, and impact ionization does not occur. In other unselected memory cells connected to the same bit line BL as the memory cell from which “0” data is read, the word line WL is also held at a negative potential, and no hole emission occurs.
[0027]
10 and 11 show read / write operations of “1” data and “0” data, respectively, by the same read method. The read operation at time t1 in FIGS. 10 and 11 is the same as that in FIGS. 8 and 9, respectively. After reading, when the word line WL is set to a higher potential at time t2 and “0” data is written to the same selected cell, a negative potential is simultaneously applied to the bit line BL (FIG. 10) and “1” data is written. A positive potential is applied to the bit line BL (FIG. 11). As a result, in the cell to which “0” data is given, the drain junction becomes a forward bias, and the channel body hole is emitted. In a cell to which “1” data is given, impact ionization occurs near the drain, and excess holes are injected and held in the channel body.
[0028]
12 to 15 use the second reading method in which the bit line BL is precharged to 0 V, a current is supplied to the bit line BL after the word line is selected, and data is discriminated based on the potential rise speed of the bit line BL. The read / refresh and read / write operation waveforms are shown.
[0029]
12 and 13 show read / refresh operations of “1” data and “0” data, respectively. The word line WL held at the negative potential is raised to the positive potential at time t1. At this time, as shown in FIG. 7, the word line potential is set to a value higher than the threshold values Vth0 and Vth1 of “0” and “1” data. Alternatively, the word line potential may be set between the threshold values Vth0 and Vth1 of “0” and “1” data, as in the first reading method. Then, current is supplied to the bit line at time t2. Thereby, in the case of “1” data, the memory cell is turned on deeply and the potential rise of the bit line BL is small (FIG. 12). In the case of “0” data, the current of the memory cell is small (or no current flows). The bit line potential rises rapidly. Thereby, “1” and “0” data are discriminated.
[0030]
At time t3, when the read data is “1”, a positive potential is applied to the bit line BL (FIG. 12), and when the read data is “0”, a negative potential is applied to the bit line BL (FIG. 12). FIG. 13). As a result, when the selected memory cell is “1” data, drain current flows, impact ionization occurs, excess holes are injected and held in the channel body, and “1” data is written again. In the case of “0” data, the drain junction becomes a forward bias, and “0” data without excess holes in the channel body is written again.
[0031]
At time t4, the word line WL is biased in the negative direction, and the read / refresh operation is terminated.
[0032]
14 and 15 show read / write operations of “1” data and “0” data, respectively, by the same read method. Read operations at times t1 and t2 in FIGS. 14 and 15 are the same as those in FIGS. 12 and 13, respectively. After reading, when writing “0” data to the same selected cell, a negative potential is applied to the bit line BL (FIG. 14), and when writing “1” data, a positive potential is applied to the bit line BL (FIG. 15). ). As a result, in the cell to which “0” data is given, the drain junction becomes a forward bias, and excess holes in the channel body are discharged. In a cell to which “1” data is given, a large drain current flows, impact ionization occurs near the drain, and excess holes are injected and held in the channel body.
[0033]
As described above, the memory cell MC according to the present invention is configured by a simple MIS transistor having a floating channel body electrically isolated from other elements. ² Cell sizes can be achieved. Further, the potential control of the floating channel body uses capacitive coupling from the gate electrode, and the source is also at a fixed potential. That is, the read / write control is performed by the word line WL and the bit line BL and is simple. Further, since the memory cell MC is basically non-destructive reading, it is not necessary to provide a sense amplifier for each bit line, and the layout of the sense amplifier becomes easy. Furthermore, since it is a current reading method, it is resistant to noise, and for example, reading is possible even with an open bit line method. Also, the manufacturing process of the memory cell is simple.
[0034]
The SOI structure is an important technology when considering future performance improvement of logic LSIs. The DRAM according to the present invention is very promising when it is mixed with a logic LSI having such an SOI structure. This is because, unlike a conventional DRAM using a capacitor, a process different from that of a logic LSI is not required, and the manufacturing process is simplified.
[0035]
Furthermore, the SOI structure DRAM according to the present invention has an advantage that superior memory retention characteristics can be obtained as compared with a conventional one-transistor / one-capacitor DRAM having an SOI structure. That is, when the conventional one-transistor / one-capacitor DRAM has an SOI structure, holes are accumulated in the floating channel body, the threshold value of the transistor is lowered, and the subthreshold current of the transistor is increased. This degrades the memory retention characteristics. On the other hand, in the memory cell having only one transistor according to the present invention, there is no transistor path for reducing the stored charge, the data retention characteristic is determined solely by the leakage of the pn junction, and the problem of subthreshold leakage is eliminated.
[0036]
In the basic memory cell described so far, how large the threshold voltage difference between data “0” and “1” stored as the channel body potential difference is important for the memory characteristics. According to the result of simulation regarding this point, when data is written with potential control of the channel body by capacitive coupling from the gate, the subsequent data is compared with the channel body potential difference between “0” and “1” data immediately after the writing. It has been clarified that the channel body potential difference between “0” and “1” data in the holding state becomes small. The simulation result will be described next.
[0037]
The device conditions are as follows: gate length Lg = 0.35 μm, p-type silicon layer 12 has a thickness of tSi = 100 nm, and acceptor concentration is NA = 5 × 10. ¹⁷ / Cm ³ And the donor concentration of the source 14 and drain 15 is ND = 5 × 10 ²⁰ / Cm ³ The gate oxide film thickness is tox = 10 nm.
[0038]
FIG. 16 shows the gate potential Vg, the drain potential Vd, and the channel body potential VB in the “0” data write and the subsequent data retention and data read (respectively shown instantaneously). FIG. 17 similarly shows the gate voltage Vg, the drain voltage Vd, and the channel body voltage VB in “1” data writing, and subsequent data holding and data reading (respectively shown instantaneously).
[0039]
Further, in order to see the threshold voltage Vth0 of the “0” data and the threshold voltage Vth1 of the “1” data in the data read operation at the time t6-t7, the drain current Ids and the gate-source voltage Vgs at that time. Is drawn as shown in FIG. However, the channel width W and the channel length L are W / L = 0.175 μm / 0.35 μm, and the drain-source voltage is Vds = 0.2V.
[0040]
From FIG. 18, the difference ΔVth between the threshold voltage Vth0 of the “0” write cell and the threshold voltage Vth1 of the “1” write cell is ΔVth = 0.32V. From the above analysis results, the problem is that in FIG. 16 and FIG. 17, the channel body potential immediately after writing “0” (time t3) is VB = −0.77 V, and the channel body potential immediately after writing “1”. While VB = 0.85V and the difference is 1.62V, in the data holding state (time t6), the channel body potential of the “0” write cell is VB = −2.04V, “1” write The body potential of the cell is VB = −1.6 V, and the difference is 0.44 V, which is smaller than that immediately after writing.
[0041]
There are two possible causes for the difference between the channel body potential data in the subsequent data holding state as compared to immediately after writing.
[0042]
One is that the capacitive coupling from the gate to the channel body varies with the data. Immediately after writing "0" (t3-t4), the drain is -1.5V, but immediately after writing "1", the drain is 2V. Therefore, when the gate potential Vg is subsequently lowered, the channel is easily lost in the “1” write cell, the capacitance between the gate and the channel body becomes obvious, and holes are gradually accumulated in the channel body, thereby increasing the capacitance. On the other hand, in the “0” write cell, the channel does not disappear easily, and the gate-channel body capacitance does not become apparent.
[0043]
If the drain potential is reset to 200 mV before starting to lower the gate potential, it seems that the above-mentioned imbalance is eliminated. However, in this case, in the cell in which “0” is written, the drain potential rises in a state where the channel is formed, and a current due to the triode operation flows. Then, the channel body potential lowered by writing “0” is increased due to capacitive coupling between the n-type drain and channel inversion layer and the p-type channel body, which is not preferable.
[0044]
The other is that the channel body potential is influenced by the capacitance of the pn junction between the source or drain and the channel body between times t4 and t5 after writing, and this is the signal amount of “0” and “1” data. It is to act in the direction to reduce the.
[0045]
Therefore, a gate (second gate) for controlling the potential of the channel body by capacitive coupling is added to the basic memory cell in addition to a gate (first gate) for controlling channel formation. . In order to ensure the capacitance between the second gate and the channel body, the accumulation state (accumulation state) is maintained without forming the channel inversion layer on the surface on the second gate side. A high concentration region having the same conductivity type as the channel body is formed. The second gate is driven in synchronization with the first gate, for example, at a lower potential than the first gate or at the same potential. Alternatively, the second gate may be fixed at, for example, a reference potential applied to the source or a lower potential (a negative potential in the case of the n channel).
[0046]
Specific embodiments will be described below.
[0047]
[Embodiment 1]
FIG. 19A shows the structure of memory cell MC according to the first embodiment of the present invention, corresponding to FIG. The basic structure is the same as that of FIG. 1. The difference from FIG. 1 is that, apart from the first gate 13 that performs channel control, a second layer that is capacitively coupled to the silicon layer 12 via the gate insulating film 19. The gate 20 is buried in the oxide film 11 and the surface of the silicon layer 12 on the second gate 20 side has a high concentration of p so that no channel inversion layer is formed. ⁺ The mold layer 21 is formed. That is, the silicon layer 12 has the same conductivity type as the silicon layer 12 and has an impurity concentration higher than the impurity concentration of the silicon layer 12. ⁺ A mold layer 21 is formed. This p ⁺ Due to the presence of the mold layer 21, even when writing is performed by applying a positive potential to the first gate 13 and the second gate 20, a channel is formed in the channel body on the first gate 13 side. However, a channel is formed in the channel body on the second gate 20 side.
[0048]
In the memory cell MC of this embodiment, the gate insulating film 19 has the same thickness as the gate insulating film 16 on the first gate 13 side.
[0049]
In an actual memory cell array configuration, a plurality of memory cells MC shown in FIG. 19A are arranged in a matrix, the first gate 13 is formed continuously as the first word line WL1, and the second gate 20 is parallel to this. Arranged as the second word line WL2.
[0050]
FIG. 19B shows an equivalent circuit of a memory cell array in which a plurality of such memory cells MC are arranged in a matrix. The first gate (G1) 13 of the plurality of memory cells MC arranged in one direction is connected to the first word line WL1, and the second gate (G2) 20 is connected to the second word line WL2. . A bit line BL to which the drain of the memory cell MC is connected is arranged in a direction crossing these word lines WL1 and WL2. The sources 15 of all the memory cells MC are connected to a fixed potential line (ground potential line VSS).
[0051]
19C shows a layout of the memory cell array, and FIGS. 19D and 19E show cross sections taken along the lines AA ′ and BB ′ of FIG. 19C, respectively. The p-type silicon layer 12 is patterned in a lattice pattern by embedding the silicon oxide film 22. That is, two transistor regions sharing the drain 14 are arranged in the direction of the word lines WL1 and WL2 while being separated from each other by the silicon oxide film 22. Alternatively, the element isolation in the lateral direction may be performed by etching the silicon layer 12 instead of embedding the silicon oxide film 22. The first gate 13 and the second gate 20 are continuously formed in one direction, and these become the word lines WL1 and WL2. The source 15 is continuously formed in the direction of the word lines WL1 and WL2, and this becomes a fixed potential line (common source line). The transistor is covered with an interlayer insulating film 17, and a bit line (BL) 18 is formed thereon. The bit line 18 is disposed so as to contact the drain 14 shared by the two transistors and intersect the word lines WL1 and WL2.
[0052]
As a result, the silicon layer 12 that is the channel body of each transistor is kept in a floating state by separating the bottom surface and the side surface in the channel width direction from each other by the oxide film and from each other by the pn junction in the channel length direction.
[0053]
In this memory cell array configuration, assuming that the word lines WL1 and WL2 and the bit lines BL are formed with a pitch of the minimum processing dimension F, the unit cell area is 2F × 2F = 4F as shown by the broken line in FIG. 19C. ² It becomes.
[0054]
In such a configuration, the same operation as described above using the basic memory cell is performed. At this time, the second word line WL2 is driven at a lower potential than the first word line WL1 in synchronization with the first word line WL1. In this manner, by driving the second gate 20 together with the first gate 13, data “0” and “1” having a large threshold voltage difference can be written. That is, the channel body potential is increased by capacitive coupling by setting the second gate 20 to a negative potential in the data holding state and increasing the potential at the time of data writing while maintaining a good accumulation state of “1” data. Thus, data writing can be ensured.
[0055]
That is, in the case of writing “0” data, a positive potential is applied to the first gate 13. Then, a channel inversion layer is formed on the first gate 13 side of the channel body. However, when the channel inversion layer is formed, this channel inversion layer becomes a hindrance factor, and the capacitive coupling to the channel body by the first gate 13 is weakened. For this reason, even if a positive potential is applied to the first gate 13, the potential of the channel body cannot be sufficiently increased.
[0056]
However, in this embodiment, the potential of the channel body can be sufficiently increased by applying a positive potential also to the second gate 20. Because p ⁺ Since the mold layer 21 is formed, the channel inversion layer is not formed on the second gate 20 side of the channel body. Therefore, by applying a positive potential to the second gate 20, the channel is capacitively coupled. The potential of the body can be raised sufficiently. Therefore, accurate “0” data can be written.
[0057]
Further, data retention is performed by lowering the potential of the unselected first word line WL1, but at this time, the potential of the second word line WL2 making a pair is also lowered to control the channel body potential to be the same. When “0” data is written in another cell connected to the bit line, data destruction in an unselected cell holding “1” data is reliably prevented. Further, in the non-selected “0” data cell connected to the “1” write bit line, there is a concern of data breakdown due to surface breakdown or GIDL current. In this embodiment, the second word line Lowering the channel body potential also eliminates these concerns.
[0058]
Further, when the potential of the bit line is greatly lowered at the time of writing “0”, a current flows from the source to the bit line. In this embodiment, since the channel body potential is increased by the second gate 20, There is no need to reduce the potential so much. For example, the current flowing from the source to the bit line can be suppressed by setting the bit line potential to the same level as the reference potential of the source.
[0059]
Also, when reading data, it is necessary to perform a triode operation so as not to erroneously write “1”. Therefore, although the bit line potential is lower than that at the time of writing “1”, the depletion layer extension between the drain and the channel body is smaller than that at the time of writing “1”, so that the capacitive coupling between the bit line and the channel body is increased. . This causes the carrier injected into the channel body at the time of writing to be redistributed, causing a drop in the channel body potential. In this embodiment, the majority carrier accumulation state of the channel body can be satisfactorily maintained by the control by the second gate 20.
[0060]
In the above description, the second gate 20 is driven at a low potential with respect to the first gate 13, but the channel body surface on the second gate 20 side has p on the surface. ⁺ Since the mold layer 21 is formed, the channel inversion layer is not formed even if the second gate 20 is driven at the same potential as that of the first gate 13, and the potential of the channel body is large by capacitive coupling. Can be controlled.
[0061]
Further, the gate insulating film 16 on the first gate 13 side and the gate insulating film 19 on the second gate 20 side do not have to be the same in thickness, and are optimally set according to the required capacity coupling. can do.
[0062]
Further, in this embodiment, the first gate 13 and the second gate 20 are opposed to the upper and lower surfaces of the silicon layer, but may be opposed to the same surface. Specifically, the first gate and the second gate are provided as one body, and a high concentration region that prevents the formation of the channel inversion layer is formed in a part of the channel region. Can be operated. The first gate and the second gate can be separately disposed on the same surface of the silicon layer.
[0063]
FIG. 19F is a perspective view showing the configuration of the memory cell MC in which the first gate 13 and the second gate 20 are integrated, and FIG. 19G shows the AA ′ cross section of FIG. 19F. FIG. 19B shows a BB ′ cross section of FIG. 19F.
[0064]
As can be seen from these drawings, in this example, the second gate 20 is not formed, and the first gate 13 plays the same role as the second gate 20. For this reason, a high concentration p is formed in the region on the surface side half of the silicon layer 12. ⁺ A mold layer 21 is formed. That is, in this example, the silicon layer 12 has a low impurity concentration p. ⁻ Formed as a mold region, p ⁺ The p-type layer 21 has a higher impurity concentration than this. ⁺ It is formed as a mold area.
[0065]
p ⁺ The mold layer 21 is formed in an approximately half region of the silicon layer 12 in plan view. p ⁺ The mold layer 21 is formed to a depth between the gate insulating film 16 and the oxide film 11. Alternatively, it may reach the oxide film 11. This p ⁺ The size of forming the mold layer 21 is arbitrary, and it is sufficient that the channel inversion layer is not formed when the first gate 13 is driven and the potential can be controlled with a large capacitive coupling to the channel body.
[0066]
FIG. 19I is a diagram showing a layout of a memory cell array in which the memory cells MC shown in FIG. 19F are arranged in a matrix, and corresponds to FIG. 19C. 19J is a view showing a cross section taken along line AA ′ of FIG. 19I, FIG. 19K is a view showing a cross section taken along line BB ′ of FIG. 19I, and FIG. 19L is a cross section taken along line CC ′ of FIG. FIG.
[0067]
As can be seen from these figures, the gate 13 is continuously formed in one direction to form one word line WL. However, in this example, since the second gate 20 described above does not exist, the second word line WL2 is not formed. The bit line 18 is disposed so as to contact the drain 14 shared by the two transistors and cross the word line WL. Then, in a part of the channel body between the drain 14 and the source 15 on the word line WL side, p ⁺ A mold layer 21 is formed.
[0068]
In this memory cell MC, as shown in FIG. ⁺ The mold layer 21 is formed in contact with the drain region 14 and the source region 15 in the BB ′ cross-sectional direction. However, it is not necessarily p ⁺ The mold layer 21 may not be in contact with the drain region 14 and the source region 15.
[0069]
Such an example is shown in FIGS. 19M and 19N. FIG. 19M is a perspective view showing the configuration of the memory cell MC, and corresponds to FIG. 19F. 19N is a diagram showing a BB ′ cross section in FIG. 19M and corresponds to FIG. 19H. The cross section AA ′ in FIG. 19M is the same as FIG. 19G described above.
[0070]
As shown in FIGS. 19M and 19N, p ⁺ The mold layer 21 is not in contact with the drain region 14 and the source region 15. By doing in this way, it can avoid that the retention time of this memory cell MC becomes short. More specifically, p ⁺ If the type layer 21, the n-type drain region 14, and the source region 15 are in direct contact with each other, the extension of the depletion layer when a reverse bias is applied to the pn junction is reduced. Then, the strength of the electric field increases, the leakage current at the pn junction increases, and the retention time, which is the time that the memory cell MC can hold data, is shortened.
[0071]
On the other hand, as shown in FIGS. 19M and 19N, p ⁺ Such a situation can be avoided by forming the mold layer 21 so as not to contact the drain region 14 and the source region 15. That is, p ⁺ Compared to the case where the mold layer 21 is in contact with the drain region 14 and the source region 15, the retention time of the memory cell MC can be lengthened.
[0072]
[Embodiment 2]
FIG. 20 shows the structure of the memory cell MC according to the second embodiment. Unlike the embodiment of FIG. 19A, in this embodiment, the second gate 20 is not patterned as a wiring, but is disposed as a common gate (back plate) so as to cover the entire cell array region. That is, the second gate 20 is provided in common to all the MIS transistors in this memory cell array. With such a structure, it is not necessary to align the second gate 20 and the first gate 13, and the manufacturing process is simplified.
[0073]
As such a configuration, the second gate 20 is fixed to, for example, a source potential or a potential lower than that, and the same operation as described in the basic memory cell is performed. Also in this case, the signal difference between “0” and “1” data can be increased by increasing the amplitude of the first gate 13 (word line WL). That is, when the second gate 20 is capacitively coupled to the channel body at a fixed potential, the capacitive coupling from the first gate 13 to the channel body is reduced by capacitive division compared to the case of the basic memory cell. However, by increasing the drive amplitude of the first gate 13 accordingly, the potential of the channel body by the first gate 13 can be controlled in a state where there is no significant difference between “0” and “1” data. The threshold voltage difference between “0” and “1” data can be increased in the data holding state.
[0074]
[Embodiment 3]
FIG. 21 shows the layout of the memory cell array according to the third embodiment, and FIG. 22 shows the AA ′ cross section. In the embodiments described so far, an SOI substrate is used to make a transistor having a floating channel body. In this embodiment, a floating channel transistor (SGT) structure is used to form a floating channel. A memory cell is constituted by a vertical MIS transistor having a body.
[0075]
In the silicon substrate 10, the p-type columnar silicon 30 is arranged and formed by processing grooves running vertically and horizontally by RIE. The first gate 13 and the second gate 20 are formed so as to face both side surfaces of each columnar silicon 30. The first gate 13 and the second gate 20 are alternately buried between the columnar silicons 30 in the cross section of FIG. The first gate 13 is separated and formed as an independent gate electrode with respect to the adjacent columnar silicon 30 between the adjacent columnar silicons 30 by the technique of leaving the side wall. On the other hand, the second gate 20 is buried between the adjacent columnar silicons 30 so as to be shared. The first and second gates 13 and 20 are successively patterned as first and second word lines WL1 and WL2, respectively.
[0076]
An n-type drain diffusion layer 14 is formed on the upper surface of the columnar silicon 30, and an n-type source diffusion layer 15 shared by all the cells is formed below. The side surface of the columnar silicon layer 30 on the second gate 20 side is p. ⁺ A mold layer 21 is formed. Thereby, a memory cell MC composed of a vertical transistor in which each channel body is floating is formed. An interlayer insulating film 17 is formed on the substrate in which the gates 13 and 20 are embedded, and a bit line 18 is disposed thereon.
[0077]
Also in this embodiment, the same operation as in the previous embodiments can be performed. According to this embodiment, it is not necessary to use an SOI substrate. Therefore, only a memory cell has a floating channel body made of a vertical transistor, and peripheral circuits such as a sense amplifier, a transfer gate, and a row / column decoder other than the cell array are provided. A normal planar transistor can be used. Therefore, unlike the case where an SOI substrate is used, it is not necessary to form a contact for fixing the channel body potential of the peripheral circuit transistor in order to eliminate the instability of the circuit due to the channel body floating effect. The area of the part can be reduced.
[0078]
[Embodiment 4]
FIG. 23 and FIG. 24 show the layout of the cell array of the embodiment using the same SGT structure as that of the third embodiment and its AA ′ cross section corresponding to FIG. 21 and FIG. The difference from the third embodiment is that the gates 13 and 20 are integrally provided around the columnar silicon layer 30 and arranged as a common word line WL. As in the third embodiment, p is formed on the side surface of the columnar silicon layer 30 facing the gate 20. ⁺ A mold layer 21 is formed.
[0079]
In the case of this embodiment, the gates 13 and 20 are integrally driven at the same potential as the word line WL. Gate 20 side is p ⁺ Since the mold layer 21 is present, a channel inversion layer is not formed. Therefore, the word line WL can be coupled to the channel body with a large capacity and its potential can be controlled. This p ⁺ The surface on which the mold layer 21 is formed is not limited to one surface of the columnar silicon layer 30 and may be formed on two surfaces and three surfaces. That is, p ⁺ The mold layer 21 may be formed on one or more surfaces of the columnar silicon layer 30.
[0080]
[Embodiment 5]
FIG. 25A shows the structure of the memory cell MC of the embodiment that can improve the reliability of writing “0” data in correspondence with FIG. The memory cell structure of this embodiment is different from that of FIG. 1 in that the gate 13 has an offset with respect to the drain 14. That is, the gate 13 is formed on the source 15 on the channel body side via the gate insulating film 16. That is, the overlap amount of the gate 13 with respect to the source 15 is positive. On the other hand, the gate 13 is not formed on the drain 14. That is, the overlap amount of the gate 13 with respect to the drain 14 is negative.
[0081]
As shown in FIG. 25A, this can be easily realized by making the ion implantation of the drain 14 and the source 15 into oblique ion implantation. Alternatively, the same offset structure can be obtained by performing normal ion implantation in a state where the sidewall insulating film is formed only on the gate side wall on the drain side without using oblique ion implantation. Others are the same as FIG.
[0082]
In the memory cell in the above-described embodiment, “0” writing applies a forward bias between the drain region 14 and the channel body, and causes the majority carriers in the channel body to be emitted to the drain region 14. In this case, in the normal transistor structure shown in FIG. 1, a channel inversion layer is formed, which becomes a shield layer between the gate 13 and the channel body, and capacitive coupling between the channel inversion layer and the channel body is increased. As a result, when the drain region 14 is returned from the negative potential to 0 V, the channel body potential rises due to capacitive coupling between the channel inversion layer and the channel body, and there is a possibility that “0” cannot be written sufficiently. Further, since the capacitance between the gate 13 and the channel body is reduced due to the channel inversion layer, it is more easily affected by the bit line. When a channel inversion layer is further formed, a channel current (electron current in the case of n channel) flows. This channel current is unnecessary for the write operation and not only increases the write power, but if impact ionization occurs, the “1” write mode is entered and the reliability of the “0” write decreases. .
[0083]
On the other hand, as shown in FIG. 25A, when an offset structure is provided on the drain side, a normal potential is applied to the drain region 14 to reverse bias the drain junction. As shown, a depletion layer DL extending from the drain region 14 extends to a position immediately below the gate 13. For this reason, by applying a positive voltage to the gate 13, a channel inversion layer CH is formed between the depletion layer DL and the source region 15 from the drain region 14, and between the drain region 14 and the source region 15. A channel current flows. That is, the memory cell MC shown in FIG. 25A operates normally as a MIS transistor as shown in FIG. FIG. 26 is a graph showing the relationship between the voltage Vd applied to the drain region 14 and the current Id flowing between the source / drain. And the characteristic at the time of changing the voltage Vg applied to the gate 13 is shown.
[0084]
However, when a negative potential is applied to the drain region 14, the drain and source functions are reversed as a transistor operation, and the depletion layer DL is formed on the source region 15 side as shown in FIG. 25C. A channel inversion layer CH is formed away from the source region 14. For this reason, as shown in FIG. 26, almost no channel current flows between the drain region 14 and the source region 15.
[0085]
Therefore, according to this embodiment, when “0” is written (that is, when a forward bias is applied between the drain region 14 and the channel body as shown in FIG. 25C), the drain region 14 and the channel body are not used. An increase in the channel body potential due to the capacitive coupling can be suppressed, and the “0” write margin can be increased. In addition, unnecessary channel current can be suppressed when writing “0”, the write current flowing through the bit line BL can be reduced, and the write power can be reduced.
[0086]
In the above, the case where almost no current flows in the reverse direction has been described, but by providing a light asymmetry with a difference of 10% or more in the channel current, the effect of reducing the current can be obtained in the same manner. Further, providing the drain region 14 with an offset is one of means for making the channel current when the source and drain are reversed asymmetry. Techniques can also be used. That is, the MIS transistor has different characteristics when a channel current flows from the source region 15 to the drain region 14 and when a channel current flows from the drain region 14 to the source region 15 even when the same potential is applied to the gate 13. What is necessary is just to have it.
[0087]
[Embodiment 6]
FIGS. 27 and 28 show embodiments in which a gate offset structure is similarly introduced for the memory cells MC of FIGS. 19A and 20, respectively. Similarly in this embodiment, useless current at the time of writing “0” can be reduced.
[0088]
29A and 29B show an embodiment in which a gate offset structure is similarly introduced to a memory cell MC using an SGT structure. FIG. 29A is a plan view showing a layout of a memory cell array composed of such memory cells MC, and FIG. 29B is a diagram showing a cross section taken along line AA ′ of FIG. 29A. As shown in FIGS. 29A and 29B, the gate 13 is an integral part surrounding the columnar silicon layer 30. The columnar silicon 30 has p ⁺ The high concentration region of the mold layer 21 is not formed.
[0089]
As shown in FIG. 29B, a gate 13 is formed around the source 15 on the channel body side in the columnar silicon layer 30 via a gate insulating film. That is, the overlap amount of the gate 13 with respect to the source 15 is positive. On the other hand, the gate 13 is not formed around the drain 14 in the columnar silicon layer 30. That is, the overlap amount of the gate 13 with respect to the drain 14 is negative.
[0090]
FIG. 30A is a plan view showing a layout of a memory cell array composed of memory cells into which a gate offset structure is introduced in the third embodiment of FIGS. 21 and 22. FIG. FIG. 30B is a diagram showing a cross section taken along line AA ′ in FIG. 30A. As shown in FIGS. 30A and 30B, the first gate 13 is formed shifted to the source region 15 side. That is, the first gate 13 is formed on the side surface of the source 15 in the columnar silicon layer 30 via the gate insulating film. That is, the amount of overlap of the first gate 13 with respect to the source 15 is positive. On the other hand, the first gate 13 is not formed on the side surface of the drain 14 in the columnar silicon layer 30. That is, the overlap amount of the first gate 13 with respect to the drain 14 is negative. Other configurations are the same as those in the third embodiment described above, and the first gate 13 and the second gate 20 are arranged as separate word lines.
[0091]
FIG. 30C is a plan view showing a layout of a memory cell array including memory cells into which a gate offset structure is introduced in the fourth embodiment shown in FIGS. FIG. 30D is a diagram showing an AA ′ cross section in FIG. 30C. As shown in FIGS. 30C and 30D, the first gate 13 is formed shifted to the source region 15 side. That is, the first gate 13 is formed on the side surface of the source 15 in the columnar silicon layer 30 via the gate insulating film. That is, the amount of overlap of the first gate 13 with respect to the source 15 is positive. On the other hand, the first gate 13 is not formed on the side surface of the drain 14 in the columnar silicon layer 30. That is, the overlap amount of the first gate 13 with respect to the drain 14 is negative. The other configuration is the same as that of the above-described fourth embodiment, and the first gate 13 and the second gate 20 are arranged as a common word line.
[0092]
In the sixth embodiment as well, unnecessary current at the time of writing “0” can be eliminated.
[0093]
[Embodiment 7]
In the embodiments so far, the substrate current due to impact ionization in the vicinity of the drain junction is used for writing “1”, but instead of impact ionization, drain leakage current induced by the gate, so-called GIDL current is used. You can also. FIG. 31 shows the gate voltage-drain current characteristics in a MISFET with gate length / gate width = 0.175 μm / 10 μm. When the gate length is shortened, a large substrate current flows when a positive drain voltage Vd is applied in a region where the gate voltage Vg is negative as shown in the figure. This is the GIDL current, and “1” can be written using this current.
[0094]
FIG. 32 shows operation waveforms of “1” write / read using the GIDL current. Unlike the case of using impact ionization, when “1” is written, the gate voltage Vg is negative and the drain voltage Vd is positive. Thereby, holes can be injected and accumulated in the channel body by the GIDL current.
[0095]
Note that the “1” write method using the GIDL current can be similarly applied to the memory cell structure of each embodiment shown in FIG. 19A and subsequent drawings as well as the basic memory cell structure shown in FIG. .
[0096]
[Embodiment 8]
33, 34A and 34B show an embodiment in which the silicon layer 12 is formed in a convex stripe shape on the insulating film 11. FIG. FIG. 33 is a plan view showing the layout of the memory cell array of such memory cells, FIG. 34A is a diagram showing a cross section along AA ′ in FIG. 33, and FIG. 34B is a diagram showing a cross section along BB ′ in FIG. FIG.
[0097]
In this case, it can be said that the gate 13 is formed by integrally forming the first gate and the second gate of the above-described embodiments, and is opposed to the upper surface and both side surfaces of the convex silicon layer 12. Specifically, this structure is obtained by embedding the silicon layer 12 in a protruding state when the element isolation insulating film 24 is embedded. Of the three faces of the silicon layer 12 facing the gate 13, for example, p on both sides. ⁺ The mold layer 21 is formed, and this is a capacitive coupling portion where the channel inversion layer is not formed. P ⁺ The mold layer 21 may be formed on one or more of the three surfaces including the upper surface and both side surfaces of the silicon layer 12.
[0098]
Thereby, the same operation as in the previous embodiments can be performed.
[0099]
[Embodiment 9]
According to each embodiment described above, a memory cell array capable of dynamic storage is configured with one MIS transistor as a 1-bit memory cell MC. As described above, when the first gate 13 and the second gate 20 are formed separately, the first word line WL1 and the second word line WL2 may be synchronously driven with different potentials. These may be driven synchronously at the same potential.
[0100]
35A and 35B show voltage waveforms of the word lines WL1 and WL2 and the bit line BL at the time of data writing. The first word line WL1 and the second word line WL2 forming a pair are driven in synchronization. FIG. 35A shows that when the first gate 13 and the second gate 20 are formed separately, the second gate 20 is controlled at a potential lower than that of the first gate 13, and the second gate of the channel body is controlled. The majority carrier can be accumulated on the 20 side. On the other hand, in FIG. 35B, the first gate 13 and the second gate 20 are driven at the same potential to allow majority carrier accumulation on the second gate 20 side of the channel body. The voltage waveform of FIG. 35B is similarly applied to the case where the first gate 13 and the second gate 20 are formed in common.
[0101]
In the case of FIG. 35A, when “1” data is written, a positive potential VWL1H higher than the reference potential VSS is applied to the selected first word line WL1, and a potential lower than that is simultaneously applied to the selected second word line WL2. VWL2H (a positive potential higher than the reference potential VSS in the example in the drawing) is applied, and a positive potential VBLH higher than the reference potential VSS is applied to the selected bit line BL. As a result, impact ionization occurs due to pentode operation in the selected memory cell MC, and holes are accumulated in the channel body.
[0102]
In data retention, a negative potential VWL1L lower than the reference potential VSS is applied to the first word line WL1, and a lower potential VWL2L is applied to the second word line WL2. Thus, “1” data, which is a state in which excess holes are accumulated in the channel body, is held.
[0103]
When "0" data is written, the same potentials VWL1H and VWL2H as when "1" is written are applied to the selected first and second word lines WL1 and WL2, respectively, and the reference potential VSS is applied to the selected bit line BL. A lower negative potential VBLL is applied. As a result, in the selected memory cell MC, the drain junction becomes a forward bias, the hole of the channel body is discharged to the drain 14, and data “0” in which the channel body potential is low is written.
[0104]
In the case of FIG. 35B, when “1” data is written, a positive potential VWLH higher than the reference potential VSS is applied to the selected first and second word lines WL1 and WL2, and the selected bit line BL is applied with the reference potential VSS. A high positive potential VBLH is applied. As a result, impact ionization occurs due to pentode operation in the selected memory cell MC, and holes are accumulated in the channel body.
[0105]
In data retention, a negative potential VWLL lower than the reference potential VSS is applied to the first and second word lines WL1 and WL2. Thus, “1” data, which is a state in which excess holes are accumulated in the channel body, is held.
[0106]
When "0" data is written, the same potential VWLH is applied to the selected first and second word lines WL1 and WL2 as when "1" is written, and the selected bit line BL is a negative potential lower than the reference potential VSS. Give VBLL. As a result, the drain junction is forward-biased in the selected memory cell MC, the hole in the channel body is discharged to the drain, and “0” data in which the channel body potential is low is written.
[0107]
Next, an example of a specific circuit configuration of the row decoder and the word line driver in this embodiment will be described. FIG. 35C is a diagram illustrating an example of a row decoder and an example of a word line driver WDDV1 for generating voltage waveforms of the word lines WL1 and WL2 illustrated in FIG. 35B.
[0108]
As shown in FIG. 35C, the row decoder RDEC includes a NAND circuit C10. The word line driver WDDV1 includes an inverter circuit C11, a level conversion circuit C12, a level conversion circuit C13, and an output buffer circuit C14. It is comprised by. With this configuration, the word line driver WDDV1 selected by the row decoder RDEC converts the high-level potential into VWLH that is higher than the positive potential VCC and supplies it to the word lines WL1 and WL2.
[0109]
More specifically, the row address signal RADD and the word line enable signal WLEN are input to the NAND circuit C10. The high-level row address signal RADD and the high-level word line enable signal WLEN are all input to the word line driver WDDV1 corresponding to the selected word lines WL1 and WL2. Therefore, the output of the NAND circuit C10 of the word line driver WDDV1 corresponding to the selected word lines WL1 and WL2 becomes low level, that is, the reference potential VSS. The output of the NAND circuit C10 is input to the inverter circuit C11.
[0110]
The inverter circuit C11 inverts the input signal and outputs it. Therefore, in the selected word line driver WDDV1, the output of the inverter circuit C11 is at a high level, that is, the positive potential VCC. The output of the inverter circuit C11 is input to the level conversion circuit C12 and the level conversion circuit C13. The output of the NAND circuit C10 is also input to the level conversion circuit C12 and the level conversion circuit C13.
[0111]
The outputs of the level conversion circuit C12 and the level conversion circuit C13 are input to the output buffer circuit C14. The level conversion circuit C12 and the output buffer circuit C14 convert the output of VCC, which is the high level output potential of the inverter circuit C11, to VWLH, which is a positive potential higher than VCC, and supply it to the word lines WL1, WL2. . Further, the level conversion circuit C13 and the output buffer circuit C14 convert the output of VSS, which is the low level output potential of the inverter circuit C11, to VWLL, which is a potential lower than VSS, and supply it to the word lines WL1, WL2. .
[0112]
In this embodiment, the level conversion circuit C12 includes p-type MOS transistors PM10 and PM11 and n-type MOS transistors NM10 and NM11. The source terminals of the p-type MOS transistors PM10 and PM11 are each connected to a supply line for the potential VWLH, and the drain terminals thereof are connected to the drain terminals of the n-type MOS transistors NM10 and NM11, respectively. The gate terminal of the p-type MOS transistor PM10 is connected to a node between the p-type MOS transistor PM11 and the n-type MOS transistor NM11. The gate terminal of the p-type MOS transistor PM11 is connected to the p-type MOS transistor PM10 and the n-type MOS transistor PM10. It is connected to a node between the type MOS transistors NM10.
[0113]
The output of the inverter circuit C11 is input to the gate terminal of the n-type MOS transistor NM10, and the output of the NAND circuit C10 is input to the gate terminal of the n-type MOS transistor NM11. The source terminals of these n-type MOS transistors NM10 and NM11 are each connected to a supply line of potential VSS.
[0114]
On the other hand, the level conversion circuit C13 includes p-type MOS transistors PM12 and PM13 and n-type MOS transistors NM12 and NM13. The source terminals of the p-type MOS transistors PM12 and PM13 are connected to the supply line of the potential VCC, respectively, and the drain terminals thereof are connected to the drain terminals of the n-type MOS transistors NM12 and NM13, respectively. The output of the inverter circuit C11 is input to the gate terminal of the p-type MOS transistor PM12, and the output of the NAND circuit C10 is input to the gate terminal of the p-type MOS transistor PM13.
[0115]
The gate terminal of the n-type MOS transistor NM12 is connected to a node between the p-type MOS transistor PM13 and the n-type MOS transistor NM13, and the gate terminal of the n-type MOS transistor NM13 is connected to the p-type MOS transistor PM12 and the n-type MOS transistor NM13. It is connected to a node between the MOS transistor NM12. The source terminals of these n-type MOS transistors NM12 and NM13 are connected to the supply line of the potential VWLL, respectively.
[0116]
The output buffer circuit C14 is configured by connecting p-type MOS transistors PM14 and PM15 and n-type MOS transistors NM14 and NM15 in series.
[0117]
The source terminal of the p-type MOS transistor PM14 is connected to the supply line of the potential VWLH, and the gate terminal thereof is connected to the gate terminal of the p-type MOS transistor PM11 in the level conversion circuit C12. The drain terminal of the p-type MOS transistor PM14 is connected to the source terminal of the p-type MOS transistor PM15. The potential VSS is input to the gate terminal of the p-type MOS transistor PM15. For this reason, the p-type MOS transistor PM15 is a normally-on MOS transistor. The drain terminal of the p-type MOS transistor PM15 is connected to the drain terminal of the n-type MOS transistor NM14. A voltage for driving the word lines WL1 and WL2 is output from a node between the p-type MOS transistor PM15 and the n-type MOS transistor NM14.
[0118]
The potential VCC is supplied to the gate terminal of the n-type MOS transistor NM14. For this reason, the n-type MOS transistor NM14 is a normally-on MOS transistor. The source terminal of the n-type MOS transistor NM14 is connected to the drain terminal of the n-type MOS transistor NM15. The gate terminal of the n-type MOS transistor NM15 is connected to the gate terminal of the n-type MOS transistor NM13 in the level conversion circuit C13. The source terminal of the n-type MOS transistor NM15 is connected to the supply line for the potential VWLL.
[0119]
Using the row decoder RDEC and the word line driver WDDV1 configured as described above, the potentials VWLH and VWLL shown in FIG. 35B are generated and supplied to the word lines WL1 and WL2. In FIG. 35C, each MOS transistor has a back gate connection, but this is not always necessary.
[0120]
The output buffer circuit C14 of the word line driver WDDV1 includes normally-on MOS transistors PM15 and NM14. This is because a potential difference between the potential VWLH and the potential VWLL is directly applied to the MOS transistors PM14 and NM15. This is to prevent it from happening. That is, the normally-on MOS transistors PM15 and NM14 reduce the potential difference by a voltage corresponding to the threshold drop. Therefore, if this potential difference may be directly applied to the MOS transistors PM14 and PM15, the MOS transistors PM15 and NM14 can be omitted as shown in FIG. 35D.
[0121]
A layout diagram in which the row decoder RDEC and the word line driver WDDV1 shown in FIG. 35C or FIG. 35D are arranged in the memory cell array MCA is shown in FIG. 35E. As shown in FIG. 35E, when the layout pitch of the word line driver WDDV1 matches the wiring pitch of the word lines WL1 and WL2, the row decoder RDEC and the word line driver WDDV1 are arranged on one side of the memory cell array MCA. be able to.
[0122]
On the other hand, when the layout area of the word line driver WDDV1 becomes large and the layout pitch of the word line driver WDDV1 cannot be matched with the wiring pitch of the word lines WL1 and WL2, a layout as shown in FIG. 35F is considered. It is done. That is, the row decoder RDEC and the word line driver WDDV1 are arranged on both sides of the memory cell array MCA. For example, the row decoder RDEC and the word line driver WDDV1 on the left side of the memory cell array MCA can decode the odd-numbered word lines WL1, WL2. Driving is performed, and even-numbered word lines WL1 and WL2 are decoded and driven by the row decoder RDEC and the word line driver WDDV1 on the right side of the memory cell array MCA.
[0123]
Next, the circuit configuration of the row data and word line driver corresponding to FIG. 35A will be described. FIG. 35G is a diagram showing an example of the row decoder and an example of the word line driver WDDV2 for generating the voltage waveforms of the word lines WL1 and WL2 shown in FIG. 35A.
[0124]
As shown in FIG. 35G, the row decoder RDEC includes a NAND circuit C10. The word line driver WDDV2 includes an inverter circuit C11, a level conversion circuit C22, a level conversion circuit C23, and an output buffer circuit C24. , A level conversion circuit C25 and an output buffer circuit C26. The voltage level relationship here is VWL1H>VWL2H>VSS>VWL1L> VWL2L according to the example of FIG. 35A.
[0125]
Explaining only the differences from FIG. 35C, the level conversion circuit C22 basically has the same configuration as the level conversion circuit C12 of FIG. 35C, and includes p-type MOS transistors PM20 and PM21 and n-type MOS transistors NM20 and NM21. ing. However, the source terminals of the p-type MOS transistors PM20 and PM21 are connected to the supply line of the potential VWL1H.
[0126]
The level conversion circuit C23 has basically the same configuration as the level conversion circuit C13 of FIG. 35C, and includes p-type MOS transistors PM22 and PM23 and n-type MOS transistors NM22 and NM23. However, the source terminals of the n-type MOS transistors NM22 and NM23 are connected to the supply line of the potential VWL1L.
[0127]
The output buffer circuit C24 has basically the same configuration as the output buffer circuit C14 in FIG. 35C, and includes p-type MOS transistors PM24 and PM25 and n-type MOS transistors NM24 and NM25 connected in series. . However, the source terminal of the p-type MOS transistor PM24 is connected to the supply line of the potential VWL1H, and the source terminal of the n-type MOS transistor NM25 is connected to the supply line of the potential VWL1L.
[0128]
In addition, the word line driver WDDV2 of FIG. 35G includes a level conversion circuit C25 and an output buffer circuit C26. The configuration of the level conversion circuit C25 is the same as that of the level conversion circuit C23, and includes p-type MOS transistors PM26 and PM27, and n-type MOS transistors NM26 and NM27. However, the source terminals of the n-type MOS transistors NM26 and NM27 are connected to the supply line of the potential VWL2L.
[0129]
The output buffer circuit C26 has the same configuration as the output buffer circuit C24, but includes two MOS transistors, a p-type MOS transistor PM28 and an n-type MOS transistor NM28. The source terminal of the p-type MOS transistor PM28 is connected to the supply line of the potential VWL2H, and the source terminal of the n-type MOS transistor NM28 is connected to the supply line of the potential VWL2L.
[0130]
The reason why the normally-on MOS transistor is not inserted is that the potential difference between the potential VWL2H and the potential VWL2L is not so large, as can be seen from FIG. 35A, even if this potential difference is directly applied to the MOS transistors PM28 and NM28. This is because no problem occurs.
[0131]
As can be seen from this configuration, the output of the output buffer circuit C24 oscillates between the potential VWL1H and the potential VWL1L, thereby driving the first word line WL1. Further, the output of the output buffer circuit C26 swings between the potential VWL2H and the potential VWL2L in synchronization with the output of the output buffer circuit C24, thereby driving the second word line WL2. In FIG. 35G, each MOS transistor has a back gate connection, but this is not always necessary.
[0132]
Similarly to the word line driver WDDV1 shown in FIG. 35D, the p-type MOS transistor PM25 and the n-type MOS transistor NM24 can be omitted in the word line driver WDDV2 as shown in FIG. 35H.
[0133]
A layout diagram in which the row decoder RDEC and the word line driver WDDV2 shown in FIG. 35G or FIG. 35H are arranged in the memory cell array MCA is shown in FIG. 35I. In the word line driver WDDV2 shown in FIGS. 35G and 35H, the layout area is shown in FIGS. 35C and 35D because the first word line WL1 and the second word line WL2 are driven synchronously at different potentials. It becomes larger than the word line driver WDDV1 shown. Therefore, it is considered difficult to make the layout pitch of the word line driver WDDV2 coincide with the wiring pitch of the word lines WL1 and WL2. Therefore, in the layout shown in FIG. 35I, the row decoder RDEC and the word line driver WDDV2 are arranged on both sides of the memory cell array MCA. That is, the left row decoder RDEC and the word line driver WDDV2 in the memory cell array MCA decode and drive the odd-numbered word lines WL1 and WL2, and the right row decoder RDEC and the word line driver WDDV2 in the memory cell array MCA The second word lines WL1 and WL2 are decoded and driven.
[0134]
As shown in FIG. 35J, for example, the word line driver WDDV3 for the first word line WL1 is arranged on the left side of the memory cell array MCA, and the word line driver WDDV4 for the second word line WL2 is arranged on the memory cell array MCA. It may be arranged on the right side. By arranging in this way, the wiring of the power supply wiring can be facilitated. That is, the potential supply lines of the potential VWL1H and the potential VWL1L are wired only on the left side of the memory cell array MCA in which the word line driver WDDV3 for the first word line WL1 is provided, and the word line driver WDDV4 for the second word line WL2 is connected. The potential supply lines of the potential VWL2H and the potential VWL2L may be wired only on the right side of a certain memory cell array MCA.
[0135]
However, in this layout, the row decoder RDEC is separately required for both the word line driver WDDV3 and the word line driver WDDV4. An example of such a word line driver WDDV3 is shown in FIG. 35K, and an example of the word line driver WDDV4 is shown in FIG. 35L.
[0136]
As shown in FIG. 35K, the word line driver WDDV3 for the first word line WL1 includes a level conversion circuit C22 connected to the row decoder RDEC via the inverter circuit C11, and a level conversion directly connected to the row decoder RDEC. A circuit C23 and an output buffer circuit C24 are provided. These configurations are the same as those of the word line driver WDDV2 of FIG. 35G described above.
[0137]
On the other hand, as shown in FIG. 35L, the word line driver WDDV4 for the second word line WL2 includes a row decoder RDEC, an inverter circuit C11, a level conversion circuit C25, and an output buffer circuit C26. Yes. The configurations of the level conversion circuit C25 and the output buffer circuit C26 are the same as those of the word line driver WDDV2 of FIG. 35G described above. However, since the word line driver WDDV4 is provided on the right side of the memory cell array MCA, the row decoder RDEC cannot be shared with the word line driver WDDV3. Therefore, the row decoder RDEC and the inverter circuit C11 are provided independently.
[0138]
Since the row address signals RADD and WLEN are synchronously input to the row decoder RDEC of the word line driver WDDV3 and the row decoder RDEC of WDD4, the word line driving potentials synchronized with different voltage amplitudes are consequently obtained. Is output.
[0139]
In FIG. 35K and FIG. 35L, back gate connection is made in each MOS transistor, but this is not always necessary. Also in the word line driver WDDV3 shown in FIG. 35K, as shown in FIG. 35M, the p-type MOS transistor PM25 and the n-type MOS transistor NM24 can be omitted.
[0140]
【The invention's effect】
As described above, according to the present invention, one memory cell is formed by one simple transistor having a floating semiconductor layer, and the cell size is 4F. ² And can be made smaller. The source of the transistor is connected to a fixed potential, and read, rewrite, and refresh are controlled only by controlling the bit line connected to the drain and the word line connected to the gate. A second gate facing the channel body of the transistor is provided, and a high-concentration layer is provided on a surface portion facing the second gate, whereby the second gate is capacitively coupled to the channel body, thereby “0”. The threshold voltage difference between “1” and “1” data can be increased.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a basic structure of a memory cell according to a basic concept of the present invention.
FIG. 2 is an equivalent circuit of the memory cell.
FIG. 3 is a layout when a memory cell array of a DRAM is configured using the memory cells.
4A is a cross-sectional view taken along the line AA ′ of FIG.
4B is a cross-sectional view taken along the line BB ′ of FIG.
FIG. 5 is a diagram showing a relationship between a word line potential and a channel body potential of the memory cell.
FIG. 6 is a diagram for explaining a reading method of the memory cell;
FIG. 7 is a diagram for explaining another reading method of the memory cell;
FIG. 8 is a diagram showing operation waveforms for “1” data read / refresh of the DRAM;
FIG. 9 is a diagram showing operation waveforms for “0” data read / refresh of the DRAM;
FIG. 10 is a diagram showing operation waveforms of “1” data read / “0” data write of the DRAM;
FIG. 11 is a diagram showing operation waveforms of “0” data read / “1” data write of the DRAM;
FIG. 12 is a diagram showing operation waveforms of “1” data read / refresh according to another read method of the DRAM;
FIG. 13 is a diagram showing operation waveforms of “0” data read / refresh according to another read method of the DRAM;
FIG. 14 is a diagram showing operation waveforms of “1” data read / “0” data write by another read method of the DRAM;
FIG. 15 is a diagram showing operation waveforms of “0” data read / “1” data write by another read method of the DRAM;
FIG. 16 is a diagram showing channel body potential change by simulation of “0” writing / reading of the same memory cell;
FIG. 17 is a diagram showing channel body potential change by simulation of “1” write / read of the same memory cell;
FIG. 18 is a diagram showing drain current-gate voltage characteristics when “0” and “1” data are read by the simulation.
FIG. 19A is a cross sectional view showing the structure of the memory cell according to the first embodiment of the present invention.
19B is a diagram showing an equivalent circuit of a memory cell array in which the memory cells shown in FIG. 19A are arranged in a matrix.
19C is a diagram showing a layout of a memory cell array in which the memory cells shown in FIG. 19A are arranged in a matrix.
FIG. 19D is a cross-sectional view taken along line AA ′ of FIG. 19C.
19E is a cross-sectional view taken along the line BB ′ of FIG. 19C.
FIG. 19F is a perspective view showing a modification of the memory cell according to the first embodiment.
19G is a cross-sectional view taken along the line AA ′ of the memory cell of FIG. 19F.
19H is a cross-sectional view taken along the line BB ′ of the memory cell in FIG. 19F.
19I is a diagram showing a layout of a memory cell array in which the memory cells shown in FIG. 19F are arranged in a matrix.
FIG. 19J is a cross-sectional view taken along the line AA ′ of FIG. 19I.
19K is a cross-sectional view taken along the line BB ′ of FIG. 19I.
FIG. 19L is a cross-sectional view taken along the line CC ′ of FIG. 19I.
FIG. 19M is a perspective view showing another modification of the memory cell according to the first embodiment.
19N is a cross-sectional view of the memory cell along BB ′ in FIG. 19M.
FIG. 20 is a cross-sectional view showing the structure of a memory cell according to the second embodiment.
FIG. 21 is a plan view of a memory cell array according to the third embodiment.
22 is a cross-sectional view taken along the line AA ′ of FIG. 21. FIG.
FIG. 23 is a plan view of a memory cell array according to the fourth embodiment.
24 is a cross-sectional view taken along line AA ′ of FIG.
FIG. 25A is a cross-sectional view showing the structure of the memory cell according to the fifth embodiment.
25B is a schematic diagram showing the state of the memory cell in the case where a positive potential is applied to the drain region, a positive potential is applied to the gate, and the source region is connected to the ground in the memory cell shown in FIG. 25A. is there.
25C is a schematic diagram showing the state of the memory cell in the case where a negative potential is applied to the drain region, a positive potential is applied to the gate, and the source region is connected to the ground in the memory cell shown in FIG. 25A. is there.
FIG. 26 is a diagram showing characteristics of the memory cell of the same embodiment;
FIG. 27 is a cross-sectional view showing a structure of a memory cell according to a sixth embodiment.
FIG. 28 is a cross-sectional view showing another structure of the memory cell according to the sixth embodiment.
FIG. 29A is a plan view of a memory cell array when a gate offset structure is applied to a memory cell with an SGT structure (sixth embodiment);
29B is a cross-sectional view of the memory cell array along AA ′ in FIG. 29A.
30A is a plan view of a memory cell array when a gate offset structure is introduced in Embodiment 3 (Embodiment 6); FIG.
30B is a cross-sectional view taken along the line AA ′ of the memory cell array according to FIG. 30A.
30C is a plan view of a memory cell array when a gate offset structure is introduced in Embodiment 4 (Embodiment 6); FIG.
30D is a cross-sectional view of the memory cell array along AA ′ in FIG. 30C.
FIG. 31 is a characteristic diagram showing a GIDL current of a MISFET (Embodiment 7);
FIG. 32 is an operation waveform diagram of “1” write / read using a GIDL current;
33 is a plan view of a memory cell array according to the eighth embodiment. FIG.
34A is a cross-sectional view taken along the line AA ′ of FIG. 33. FIG.
34B is a cross-sectional view taken along the line BB ′ of FIG. 33. FIG.
FIG. 35A is a waveform diagram showing a write operation of a memory cell in the case where a first gate and a second gate are synchronously driven with different potentials (Embodiment 9).
FIG. 35B is a waveform diagram showing a write operation of a memory cell in the case where a first gate and a second gate are driven at the same potential (Embodiment 9).
35C is a diagram showing an example of a circuit configuration of a word line driver and a row decoder for generating the write operation waveform of FIG. 35B.
FIG. 35D is a diagram showing a modification of the word line driver shown in FIG. 35C.
35E is a diagram showing an example of a layout when the row decoder and the word line driver shown in FIG. 35C or FIG. 35D are arranged with respect to the memory cell array (one-sided arrangement).
FIG. 35F is a diagram showing an example of a layout when the row decoder and the word line driver shown in FIG. 35C or FIG. 35D are arranged with respect to the memory cell array (two-sided arrangement);
FIG. 35G is a diagram showing an example of a circuit configuration of a word line driver and a row decoder for generating the write operation waveform of FIG. 35A.
FIG. 35H is a diagram showing a modification of the word line driver shown in FIG. 35G.
FIG. 35I is a diagram showing an example of a layout when the row decoder and the word line driver shown in FIG. 35G or FIG. 35H are arranged in the memory cell array (first word line and second word line); When a row decoder and a word line driver are alternately provided on the left and right sides of a pair of word lines consisting of
FIG. 35J is a diagram showing an example of a layout when the row decoder and the word line driver shown in FIG. 35G or FIG. 35H are arranged in the memory cell array (a row decoder for the first word line on one side); And a word line driver and a row decoder and word line driver for the second word line on the other side).
FIG. 35K is a diagram showing an example of a circuit configuration of a first word line row decoder and a word line driver in the case of employing the layout shown in FIG. 35J;
FIG. 35L is a diagram showing an example of a circuit configuration of a second word line row decoder and a word line driver when the layout shown in FIG. 35J is adopted;
FIG. 35M is a diagram showing a modification of the word line driver shown in FIG. 35K.
[Explanation of symbols]
10 Silicon substrate
11 Silicon oxide film
12 p-type silicon layer
13 First gate
14 Drain diffusion layer
15 Source diffusion layer
20 Second gate

Claims (25)

A semiconductor memory device having a plurality of MIS transistors for constituting a memory cell, wherein each MIS transistor is
A semiconductor layer;
A source region formed in the semiconductor layer;
A drain region formed apart from the source region in the semiconductor layer, wherein the semiconductor layer between the source region and the drain region becomes a channel body in a floating state; and
A first gate for forming a channel in the channel body;
A second gate for controlling the potential of the channel body by capacitive coupling;
A high concentration region formed on the second gate side of the channel body, the high concentration region having the same conductivity type as the channel body and having an impurity concentration higher than the impurity concentration of the channel body;
With
The MIS transistor dynamically stores a first data state in which the channel body is set to a first potential and a second data state in which the channel body is set to a second potential.
A semiconductor memory device. A drain region of the MIS transistor is connected to a bit line; a first gate of the MIS transistor is connected to a first word line; and a source region of the MIS transistor is connected to a source line;
The source region and the drain region are composed of an n-type semiconductor layer, and the channel body between the source region and the drain region is composed of a p-type semiconductor layer,
With the source line potential fixed at 0V, the first word line is set to a positive potential and the bit line is set to a positive potential, thereby writing the first data state to the MIS transistor; 2. The writing apparatus according to claim 1, further comprising: writing means for writing the second data state to the MIS transistor by setting the first word line to a positive potential and setting the bit line to a negative potential. The semiconductor memory device described.   The semiconductor memory device according to claim 1, wherein the first gate and the second gate are formed separately. A plurality of the MIS transistors are arranged in a matrix, the drain regions of the MIS transistors arranged in the first direction are the bit lines, the first gates of the MIS transistors arranged in the second direction are the first word lines, and the MIS transistors A memory cell array is formed by connecting a source region of the MIS transistor to a fixed potential and a second gate of the MIS transistor arranged in the second direction to a second word line, respectively.
The semiconductor memory device according to claim 3. A plurality of the MIS transistors are arranged in a matrix, the drain region of the MIS transistors arranged in the first direction is a bit line, the first gate of the MIS transistors arranged in the second direction is a word line, and the source region of the MIS transistor Is connected to the first fixed potential, and the second gate of the MIS transistor is connected to the second fixed potential as a common plate of all MIS transistors to form a memory cell array.
The semiconductor memory device according to claim 3. The semiconductor layer is formed by being separated by an insulating film on a semiconductor substrate,
The first gate is continuously disposed as a first word line above the semiconductor layer, and the second gate is a second parallel to the first word line below the semiconductor layer. Are arranged continuously as word lines,
The semiconductor memory device according to claim 3. The semiconductor layer is a columnar semiconductor formed on a semiconductor substrate,
The first gate is formed to face one side surface of the columnar semiconductor layer, and the second gate is formed on a side surface of the columnar semiconductor layer opposite to the first gate. The drain region is formed on the upper surface of the columnar semiconductor, and the source region is formed on the lower portion of the columnar semiconductor.
The semiconductor memory device according to claim 3.   4. The semiconductor memory device according to claim 3, wherein the first gate has a positive overlap with the source region and a negative overlap with the drain region.   6. The semiconductor memory device according to claim 5, wherein the first gate has a positive amount of overlap with the source region and a negative amount of overlap with the drain region.   8. The semiconductor memory device according to claim 7, wherein the first gate has a positive overlap with the source region and a negative overlap with the drain region.   A driving circuit for driving the first gate and the second gate, the driving circuit further driving the second gate in synchronization with a potential lower than that of the first gate; The semiconductor memory device according to claim 3.   4. The semiconductor memory device according to claim 3, further comprising a drive circuit that drives the first gate and the second gate in synchronization with the same potential.   The semiconductor memory device according to claim 1, wherein the first gate and the second gate are configured as a common gate formed in common.   14. The semiconductor memory device according to claim 13, wherein the high-concentration region is formed on a part of the common gate side surface of the channel body.   15. The semiconductor memory device according to claim 14, wherein the high concentration region is in contact with the source region and the drain region.   15. The semiconductor memory device according to claim 14, wherein the high concentration region is not in contact with either the source region or the drain region. The semiconductor layer is a columnar semiconductor layer formed on a semiconductor substrate,
The common gate is formed so as to surround a periphery of the columnar semiconductor layer, the high concentration region is formed on one or more side surfaces of the columnar semiconductor layer, the drain region is formed on the upper surface of the columnar semiconductor, and the source A region is formed under the columnar semiconductor,
The semiconductor memory device according to claim 13.   18. The semiconductor memory device according to claim 17, wherein the common gate has a positive amount of overlap with the source region and a negative amount of overlap with the drain region. The semiconductor layer is a convex semiconductor layer formed on a semiconductor substrate,
The common gate is formed to face the upper surface and both side surfaces of the convex semiconductor layer, and the high concentration region is formed on one or more side surfaces of the convex semiconductor layer facing the common gate, The drain region and the source region are formed across the common gate in a convex semiconductor layer,
The semiconductor memory device according to claim 13. A drain region of the MIS transistor is connected to a bit line; a first gate of the MIS transistor is connected to a first word line; and a source region of the MIS transistor is connected to a source line;
The source region and the drain region are composed of an n-type semiconductor layer, and the channel body between the source region and the drain region is composed of a p-type semiconductor layer,
With the source line potential fixed at 0V, the first word line is set to a negative potential and the bit line is set to a positive potential, thereby writing the first data state to the MIS transistor ; 2. The writing apparatus according to claim 1, further comprising: writing means for writing the second data state to the MIS transistor by setting the first word line to a positive potential and setting the bit line to a negative potential. The semiconductor memory device described. A semiconductor memory device having a plurality of MIS transistors for constituting a memory cell, wherein each MIS transistor is
A semiconductor layer;
A source region formed in the semiconductor layer;
A drain region formed apart from the source region in the semiconductor layer, wherein the semiconductor layer between the source region and the drain region becomes a channel body in a floating state; and
A first gate for forming a channel in the channel body;
With
It said first gate, said a quantity overlapping the source region is positive, and the amount of overlap with respect to the drain region is arranged such that the negative, and is offset to the first gate to said drain region ,
A drain region of the MIS transistor is connected to a bit line; a first gate of the MIS transistor is connected to a first word line; and a source region of the MIS transistor is connected to a source line;
The source region and the drain region are composed of an n-type semiconductor layer, and the channel body between the source region and the drain region is composed of a p-type semiconductor layer,
With the source line potential fixed at 0V, the first word line is set to a positive potential and the bit line is set to a positive potential, thereby writing the first data state to the MIS transistor; A semiconductor memory device , further comprising: writing means for writing the second data state to the MIS transistor by setting the first word line to a positive potential and the bit line to a negative potential. .   In the MIS transistor, even when the same potential is applied to the first gate, the channel current flowing from the drain region to the source region is larger than the channel current flowing from the source region to the drain region. The semiconductor memory device according to claim 21.   23. The semiconductor memory device according to claim 21, wherein the MIS transistor further includes a second gate for controlling the potential of the channel body by capacitive coupling separately from the first gate.   The MIS transistor further includes a high-concentration region formed on a surface of the channel body on the second gate side and having the same conductivity type as the channel body and having an impurity concentration higher than that of the channel body. The semiconductor memory device according to claim 21, wherein: A semiconductor memory device having a plurality of MIS transistors for constituting a memory cell, wherein each MIS transistor is
A semiconductor layer;
A source region formed in the semiconductor layer;
A drain region formed apart from the source region in the semiconductor layer, wherein the semiconductor layer between the source region and the drain region becomes a channel body in a floating state; and
A gate for forming a channel in the channel body;
With
A drain region of the MIS transistor is connected to a bit line, a gate of the MIS transistor is connected to a word line, and a source region of the MIS transistor is connected to a source line;
The source region and the drain region are composed of an n-type semiconductor layer, and the channel body between the source region and the drain region is composed of a p-type semiconductor layer,
The first data state is written to the MIS transistor by setting the word line to a negative potential and the bit line to a positive potential in a state where the potential of the source line is fixed at 0V, and the word line Writing means for writing the second data state to the MIS transistor by setting the bit line to a negative potential and the bit line to a negative potential ;
A semiconductor memory device.

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