JP2002260381A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which a memory cell has simple transistor structure and dynamic storage of binary data can be performed with less signal lines. SOLUTION: A plurality of memory cells are arranged making one MIS transistor formed on a silicon layer 12 of a SOI substrate as a memory cell MC of one bit, gates 13 of the memory cells MC arranged in the first direction are connected to word lines WL, drains 14 of the memory cell arranged in the second direction are connected to bit lines BL, sources 15 of all memory cell MC have the memory cell array connected to a fixed potential line. The memory cell MC stores a first data state in which excessive many carriers are held in the silicon layer 12 and which have first threshold voltage, a second data state in which excessive many carriers of the silicon layer 12 are discharged and which have second threshold voltage, also, rewriting of data can be performed with an arbitrary bit unit, further, the memory cell MC has initializing mode in which all memory cells MC of a memory cell array are written in the first data state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a dynamic semiconductor memory device (DRAM).

[0002]

2. Description of the Related Art In a conventional DRAM, a memory cell is constituted by a MOS transistor and a capacitor. DR
The miniaturization of AM has been greatly advanced by adopting a trench capacitor structure or a stacked capacitor structure. Current,
The size (cell size) of the unit memory cell is reduced to an area of 2F × 4F = 8F ² , where F is the minimum processing dimension. That is, when the minimum processing dimension F decreases with generation and the cell size is generally αF ² , the coefficient α also decreases with generation, and when F = 0.18 μm, α = 8
Has been realized.

[0003] In order to secure the same trend in cell size or chip size as in the past, F <0.
At 18 μm, α <8, and at F <0.13 μm, α
It is required to satisfy <6, and how to form the cell size in a small area together with the fine processing is a major issue. Therefore, various proposals have been made to make the memory cell of one transistor / one capacitor to have a size of 6F ² or 4F ² . However, there are technical difficulties such as the need to make the transistors vertical, problems such as increased electrical interference between adjacent memory cells, and difficulties in manufacturing techniques such as processing and film formation. Absent.

On the other hand, some DRAMs have been proposed as follows, in which one transistor is used as a memory cell without using a capacitor. JOHN E.LEISS et al, "dRAM Design Using the Taper-
Isolated Dynamic Cell "(IEEE JOURNAL OF SOLID-STATE
CIRCUITS, VOL.SC-17, NO.2, APRIL 1982, pp337-344) JP-A-3-171768 Marnix R. Tack et al, "The Multistable Charge-Cont
rolled Memory Effect in SOI MOS Transistors at Low
Temperatures "(IEEE TRANSACTIONS ON ELECTRONDEVICE
S, VOL. 37, MAY, 1990, pp1373-1382) Hsing-jen Wann et al, "A Capacitorless DRAM Cell
on SOI Substrate "(IEDM93, pp635-638)

[0005]

The memory cell of the present invention is constructed using MOS transistors having a buried channel structure. The surface inversion layer is charged and discharged by using a parasitic transistor formed in the tapered portion of the element isolation insulating film to perform binary storage. Memory cells use MOS transistors individually separated from each other in wells, and set a threshold value determined by the well potential of the MOS transistors to binary data. Are constituted by MOS transistors on an SOI substrate. By applying a large negative voltage from the side of the SOI substrate and utilizing the accumulation of holes at the interface between the oxide film of the silicon layer and the interface, binary storage is performed by discharging and injecting the holes. Are constituted by MOS transistors on an SOI substrate. Although there is one MOS transistor in structure, a reverse conductivity type layer is formed on the surface of the drain diffusion layer, and the structure is substantially a combination of a write PMOS transistor and a read NMOS transistor. Using the substrate region of the NMOS transistor as a floating node, binary data is stored according to the potential.

However, since the structure is complicated and a parasitic transistor is used, there is a problem in controllability of characteristics. Although the structure is simple, both the drain and the source of the transistor need to be connected to the signal line to control the potential. In addition, since the well is separated, the cell size is large, and rewriting for each bit cannot be performed. In such a case, the potential control from the SOI substrate side is required, so that it is not possible to rewrite for each bit, and there is a problem in controllability. Requires a special transistor structure, and a memory cell requires a word line, a write bit line, a read bit line, and a purge line, so that the number of signal lines increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of dynamically storing binary data with a small number of signal lines using a simple transistor structure as a memory cell.

[0008]

In a semiconductor memory device according to the present invention, a plurality of memory cells are arranged with one MIS transistor formed in a floating semiconductor layer as a 1-bit memory cell, and are arranged in a first direction. A memory cell array in which gates of the memory cells arranged in a row are connected to word lines, drains of the memory cells arranged in a second direction are connected to bit lines, and sources of all memory cells are connected to a fixed potential line; The cell has a first data state in which impact ionization occurs near the drain junction to set the semiconductor layer to the first potential and a second data state in which a forward current flows to the drain junction to set the semiconductor layer to the second potential. Two data states are dynamically stored, and
An initialization mode for writing all the memory cells of the memory cell array to the first data state is provided.

According to the present invention, one memory cell includes:
It is formed by a single simple MIS transistor having a floating semiconductor layer as a body region, and the cell size can be reduced to 4F ² . The source of the transistor is connected to a fixed potential line, and reading, rewriting and refreshing are controlled only by controlling the bit line connected to the drain and the word line connected to the gate. That is, data can be rewritten in arbitrary bit units. In addition, since the memory cell according to the present invention is basically a non-destructive read, it is not necessary to provide a sense amplifier for each bit line. There is no need to provide them, so that the layout of the sense amplifier is facilitated. Further, since the memory cell is a current read, it has excellent noise resistance, and an open bit line method can be used.

In the present invention, specifically, the first data state is obtained by causing the memory cell to operate as a pentode, causing impact ionization near the drain junction, and retaining the generated majority carriers in the semiconductor layer. The second data state is written by applying a forward bias between the drain and the semiconductor layer to which a predetermined potential is applied by capacitive coupling from the gate to pull out majority carriers in the semiconductor layer to the drain. These data states are held by applying a data holding potential lower than the reference potential applied to the source to the gate.

On the other hand, since the memory cell according to the present invention has a floating body, it is undefined what value the body potential will be in an initial state after power is turned on. Therefore, for example, there is a possibility that normal data writing cannot be performed because the initial body potential is too low. On the other hand, in the present invention, by providing the initialization mode in which the first data state is forcibly written to all the memory cells of the memory cell array, the subsequent normal operation can be guaranteed.

Specifically, the initialization mode may have the following several modes. (A) The first control potential and the third control potential at the time of writing the normal first data state are respectively applied to the word line and the bit line.
A method of giving a control potential higher than the control potential of Thus, it is possible to surely initialize to the first data state. (B) A method in which a word line is supplied with a control potential higher than the first control potential in the normal first data state write, and a bit line is supplied with the same third control potential as in the normal first data state write. Or conversely, the word line has the same first data state as in a normal first data state write.
And a control potential higher than the third control potential in the normal first data state writing. With this, it is possible to almost certainly initialize to the first data state. (C) The same first control potential as in the normal first data state write is applied to the word line, and the normal first control state is applied to the bit line.
A method of giving the same third control potential as in writing the data state. This method is not easy to initialize when the body in the initial state is at a low potential, but can be initialized to the first data state after a certain period of time.

Aspects (a) to (c) of the above initialization mode
All of the above methods perform initialization by the pentode operation of the same memory cell as in the normal writing of the first data state. On the other hand, the memory cell array is changed to the first according to another principle.
The following mode (d) of initializing to the data state is also conceivable. (D) In a state where the second control potential for maintaining the data holding state is applied to the word line, a higher potential than the third control potential in the normal first data state writing is applied to the bit line,
IDLC (Gate Induced Drain L
A method of initializing to the first data state by using the EAG (Current Current).

Preferably, in the present invention, the memory cell may have an auxiliary gate for controlling the potential of the floating semiconductor layer by capacitive coupling, separately from the normal gate. When such an auxiliary gate is provided, the body potential is controlled by capacitive coupling from the auxiliary gate, and the initialization operation can be performed more reliably. In the present invention, preferably, the initialization mode is automatically executed by detecting power-on inside the chip.

[0015]

FIG. 1 shows a sectional structure of a unit memory cell of a DRAM according to the present invention, and FIG. 2 shows an equivalent circuit thereof. The memory cell MC includes an N-channel MIS transistor having an SOI structure. That is,
A silicon oxide film 11 as an insulating film on a silicon substrate 10
Is formed, and an SOI substrate in which a p-type silicon layer 12 is formed on the silicon oxide film 11 is used. A gate electrode 13 is formed on a silicon layer 12 of the substrate with a gate oxide film 16 interposed therebetween, and n-type source / drain diffusion layers 14 and 15 are formed in self-alignment with the gate electrode 13.

The source and drain diffusion layers 14 and 15 are formed to a depth reaching the silicon oxide film 11 at the bottom. Therefore, if the body region made of the p-type silicon layer 12 is separated by an oxide film in the channel width direction (the direction perpendicular to the plane of the drawing), the bottom surface and the side surface in the channel width direction are insulated and separated from each other. The channel length direction is in a floating state in which a pn junction is separated. This memory cell M
When C is arranged in a matrix, the gate electrode 13 is connected to a word line WL, the source diffusion layer 15 is connected to a fixed potential line (ground potential line), and the drain diffusion layer 14 is connected to a bit line BL.

FIG. 3 shows the layout of the memory cell array, and FIGS. 4A and 4B show AA ',
BB 'section is shown. The p-type silicon layer 12 is formed in a lattice pattern by burying the silicon oxide film 21. That is, the regions of the two transistors sharing the drain are arranged in the word line WL direction by element isolation by the silicon oxide film 21. Or silicon oxide film 2
Instead of the embedding of 1, lateral isolation may be performed by etching the silicon layer 12. The gate electrode 13 is formed continuously in one direction, and this becomes the word line WL. The source diffusion layer 15 is connected to the word line WL
These are formed continuously in the direction, and this becomes a fixed potential line (common source line). The transistor is covered with an interlayer insulating film 23, on which a bit line BL is formed. Bit line BL
Is a drain diffusion layer 14 shared by two transistors.
, And arranged to cross the word line WL.

Thus, the bottom surface and the side surface in the channel width direction of the silicon layer 12, which is the body region of each transistor, are separated from each other by the oxide film, and are separated from each other by the pn junction in the channel length direction and are kept in a floating state. It is. In this memory cell array configuration, assuming that the word lines WL and the bit lines BL are formed at the pitch of the minimum processing dimension F, the unit cell area is 2F × 2F = 4F ² as shown by the broken line in FIG.

DRA comprising this NMOS transistor
The operating principle of the M cell utilizes the accumulation of holes, which are majority carriers, in the body region of the MOS transistor (the p-type silicon layer 12 insulated from the others). That is, by operating the MOS transistor in the pentode region, a large current flows from the drain diffusion layer 14 and impact ionization occurs near the drain diffusion layer 14. Holes, which are excess majority carriers generated by the impact ionization, are held in the p-type silicon layer 12, and the hole accumulation state is, for example, data "1". The state where the pn junction between the drain diffusion layer 14 and the p-type silicon layer 12 is forward-biased and excess holes in the p-type silicon layer 12 are discharged to the drain side is defined as data “0”.

The data "0" and "1" are the difference between the body potentials and are stored as the difference between the threshold voltages of the MOS transistors. That is, the threshold voltage Vth1 in the data “1” state where the potential of the body region is high due to the accumulation of holes is
It is lower than the threshold voltage Vth0 in the data “0” state. In order to maintain the "1" data state in which holes serving as majority carriers are accumulated in the body, it is necessary to apply a negative bias voltage to the word lines. This data holding state is the same unless the reverse data write operation (erase) is performed.
It does not change even if the read operation is performed. That is, D of one transistor / one capacitor utilizing the charge storage of the capacitor
Unlike RAM, non-destructive reading is possible.

Several data reading methods are conceivable. The relationship between the word line potential VWL and the body potential VB is as shown in FIG. 5 in relation to the data “0” and “1”.
Therefore, the first method of data reading is that the threshold voltage Vth0, Vth of data "0", "1" is applied to the word line WL.
A read potential that is intermediate between 1 and 1 is applied so that a current does not flow in a memory cell of “0” data and a current flows in a memory cell of “1” data. Specifically, for example, the bit line BL is precharged to a predetermined potential VBL, and then the word line WL is driven. As a result, FIG.
As shown in FIG. 7, in the case of "0" data, the bit line precharge potential VBL does not change, and in the case of "1" data, the precharge potential VBL decreases.

In the second read mode, a current is supplied to the bit line BL after the word line WL is started,
The fact that the rising speed of the bit line potential varies depending on the degree of conduction of “0” and “1” is used. Briefly, the bit line BL is precharged to 0V, and the word line WL is precharged as shown in FIG.
To supply a bit line current. At this time, data difference can be determined by detecting a difference in potential rise of the bit line by using a dummy cell.

The third reading method is a method of reading a difference between bit line currents different between "0" and "1" when the bit line BL is clamped at a predetermined potential. To read the current difference, a current-voltage conversion circuit is required, but finally, the potential difference is differentially amplified to output a sense output.

In the present invention, in order to selectively write "0" data, that is, excessive data is written only from the bulk region of the memory cell selected by the potential of the word line WL and bit line BL selected in the memory cell array. In order to release holes, the capacitive coupling between the word line WL and the body becomes essentially. The state in which holes are accumulated in the body region with data "1" is a state in which the word line is biased in a sufficiently negative direction, and the gate-substrate capacitance of the memory cell becomes the gate oxide film capacitance (that is, a depletion layer on the surface). (A state in which no is formed).

A more specific operation waveform will be described. Fig. 8-
FIG. 11 shows read / refresh and read / write operation waveforms in the case of using the first read method in which data is determined based on whether or not a selected cell discharges a bit line. 8 and 9 show “1” data and “0” data, respectively.
This is a data read / refresh operation. Until time t1, the data is in a data holding state (non-selected state), and a negative potential is applied to the word line WL. At time t1, the word line WL is raised to a predetermined positive potential. At this time, the word line potential is set to the threshold values Vth0, Vt of the "0", "1" data.
Set during h1. As a result, in the case of "1" data, the bit line VBL which has been precharged in advance becomes low potential by discharging. In the case of “0” data, the bit line potential VBL is held. Thus, "1" and "0" data are determined.

At time t2, the potential of the word line WL is further increased, and when the read data is "1", a positive potential is applied to the bit line BL (FIG. 8), and the read data becomes "0". In this case, a negative potential is applied to the bit line BL (FIG. 9). Thus, when the selected memory cell is "1" data, a large channel current flows due to the pentode operation, impact ionization occurs, excess holes are injected and held in the body, and "1" data is written again.
In the case of "0" data, the drain junction becomes forward biased, and "0" data in which excess holes are not held in the body is written again.

Then, at time t3, the word line WL is biased in the negative direction, and the read / refresh operation ends. In other unselected memory cells connected to the same bit line BL as the memory cell from which "1" data has been read, the word line WL is kept at a negative potential, and hence the body is kept at a negative potential, so that impact ionization does not occur. In other unselected memory cells connected to the same bit line BL as the memory cell from which "0" data has been read, the word line WL is also kept at a negative potential and no hole emission occurs.

FIGS. 10 and 11 show reading / writing of "1" data and "0" data by the same read method, respectively.
This is a write operation. The read operation at time t1 in FIGS. 10 and 11 is the same as in FIGS. 8 and 9, respectively.
After the reading, at time t2, the word line WL is set to a higher potential, and when writing "0" data to the same selected cell, a negative potential is applied to the bit line BL at the same time (FIG. 10), and "1"
When writing data, a positive potential is applied to the bit line BL (FIG. 11). As a result, in the cell to which "0" data is given, the drain junction becomes forward-biased, and holes in the body are emitted. In a cell to which “1” data is given, impact ionization occurs near the drain,
Excess holes are injected and held in the body.

FIGS. 12 to 15 show a second read operation in which the bit line BL is precharged to 0 V, a current is supplied to the bit line BL after the word line is selected, and the data is determined based on the potential rising speed of the bit line BL. / When using the method
It is an operation waveform of refresh and read / write. FIG. 12 and FIG. 13 show the read / refresh operation of “1” data and “0” data, respectively. The word line WL held at the negative potential is raised to the positive potential at time t1. At this time, as shown in FIG.
The threshold value is set to a value higher than any of the threshold values Vth0 and Vth1 of “0” and “1” data. Alternatively, the word line potential may be set between the threshold values Vth0 and Vth1 of “0” and “1” data as in the first reading method. Then, a current is supplied to the bit line at time t2. As a result, in the case of "1" data, the memory cell is turned on deeply and the potential rise of the bit line BL is small (FIG. 12).
In the case of "0" data, the current of the memory cell is small (or no current flows), and the bit line potential rises rapidly. Thus, "1" and "0" data are determined.

At time t3, when the read data is "1", a positive potential is applied to the bit line BL (FIG. 12). When the read data is "0", the bit line BL is applied.
Is given a negative potential (FIG. 13). Thus, when the selected memory cell is "1" data, a drain current flows and impact ionization occurs, excess holes are injected and held in the body, and "1" data is written again. In the case of "0" data, the drain junction becomes forward biased, and "0" data without excessive holes in the body is written again. At time t4, the word line WL is biased in the negative direction, and the read / refresh operation ends.

FIGS. 14 and 15 show reading / writing of “1” data and “0” data by the same read method, respectively.
This is a write operation. The read operation at times t1 and t2 in FIGS. 14 and 15 is the same as in FIGS. 12 and 13, respectively. After reading, when writing “0” data to the same selected cell, a negative potential is applied to the bit line BL (FIG. 14), and when writing “1” data, the bit line BL
Is given a positive potential (FIG. 15). As a result, in the cell to which "0" data is given, the drain junction becomes forward-biased, and excess holes in the body are emitted. In a cell to which "1" data is given, a large drain current flows, impact ionization occurs near the drain, and excess holes are injected and held in the body.

As described above, the DRAM cell according to the present invention is constituted by a simple MOS transistor having a floating body which is electrically isolated from the others,
A cell size of ² is feasible. The potential control of the floating body utilizes capacitive coupling from the gate electrode, and the source diffusion layer has a fixed potential. That is,
The read / write control is performed only by the word lines WL and the bit lines BL, and is simple. Further, since the memory cell is basically a non-destructive read, it is not necessary to provide a sense amplifier for each bit line, and the layout of the sense amplifier is simplified. Further, since the current reading method is used, the resistance to noise is high. For example, reading can be performed by an open bit line method. Also, the manufacturing process of the memory cell is simple.

Up to this point, the basic memory operation has been described, but operation guarantee is a problem immediately after power-on. That is, since the body of the memory cell is floating, the potential of the body is held at a built-in potential with respect to the reference potential of the source, but the lower one is undefined and may be too low. is there. Then, there is a possibility that the pentode operation for writing “1” data cannot be performed as it is.

This can be inferred from the characteristics shown in FIG. FIG. 16 shows the dependence of the drain current Id and the substrate current Isub on the gate voltage Vg for a normal MOS transistor using the body potential Vb as a parameter. When a high potential VWLH is applied to the gate to cause pentode operation to cause impact ionization, the generated hole current is observed as the substrate current Isub. FIG.
Indicates that when the body potential Vb is shifted in the negative direction, the substrate current Isub decreases. Therefore, also in the present invention, if the body potential is large negative in the initial state, there is a possibility that "1" data cannot be written until then. Therefore, in the present invention, an operation of initializing the memory cell array at the time of turning on the power or the like is performed.

An embodiment having such an initialization mode will be specifically described below. FIG. 17 shows the configuration of the entire DRAM chip. As shown in FIG. 18, the memory cell array 21 includes memory cells MC arranged in a matrix.
Word line W to which gates of a plurality of memory cells are commonly connected
L and a bit line BL to which the drains of a plurality of memory cells are commonly connected are arranged to intersect. The bit line BL of the memory cell array 21 is connected to a sense amplifier 23 via a column gate 22 controlled by a column decoder 24. Word line W of memory cell array 21
L is selected and driven by the row decoder / word line driver 25.

Data transfer between the sense amplifier 23 and the I / O terminal is performed via the I / O buffer 27. The external address is taken into the address buffer 26 via the I / O buffer 27, and the row address and the column address are supplied to the row decoder / word line driver 25 and the column decoder 24, respectively.

The potential generating circuit 29 generates a high potential VWLH applied to the word line WL at the time of data writing, a low potential VWLL at the time of data holding, and an intermediate potential VWLR at the time of data reading, and is applied to the bit line BL. A high potential VBLH at the time of writing “1” data, a low potential VBLL at the time of writing “0” data, a precharge potential VBLR at the time of data reading, and the like are generated.

This potential generating circuit 29 is connected to an external power supply VEX.
A required potential is generated under the control of the output of the power-on detection circuit 28 which detects the input of T. The control circuit 30 receives the output of the power-on detection circuit 28 and controls an initialization operation for initializing all the memory cells of the memory cell array 21. More specifically, the control circuit 30 operates, for example, an address counter provided in the address buffer 26, increments the address, and performs an initialization operation of forcibly writing “1” data to all the memory cells of the memory cell array 21. Control.

Alternatively, the control circuit 30 puts the row decoder 25 and the column decoder 24 in the all-selected state, and forcibly writes “1” data to all the memory cells of the memory cell array 21 collectively. May be performed. Further, when the memory cell array 21 is divided into a plurality of sub-cell arrays, it is possible to perform control to initialize each sub-cell array by time division. In addition, upon detection of power-on, the control circuit 30 automatically performs an initialization operation and receives a command input from an I / O terminal,
A similar initialization operation may be performed. Hereinafter, a specific initialization operation mode will be described.

[First Initialization Mode] In the first initialization mode, a potential higher than the high potential at the time of normal "1" data writing is applied to the word line WL and the bit line BL. FIG. 19 shows the high potential VWLH applied to the word line and the high potential VBLH applied to the bit line output from the potential generation circuit 29 in this case. After the power is turned on, for a fixed time T, the word line high potential VWLH1 and the bit line VBLH used for normal "1" data writing are used.
The potentials VWLH0 and VBLH0 higher than 1 are generated.

FIG. 20 shows the potentials of the word line WL and bit line BL and the body potential VB of the memory cell at that time after the initialization operation. In the initialization operation,
The potentials VWLH0 and VBLH higher than the normal "1" write time are applied to the word line WL and the bit line BL, respectively.
By giving 0, the body potential VB is sufficiently increased to cause impact ionization. This ensures that "1"
Data is written. Thereafter, the word line WL is set to the negative potential V.
The data is held at WLL, and the normal operation is performed thereafter. In the figure, the operation waveform of “1” data writing is shown.

[Second Initialization Mode] In the second initialization mode, the same high potential as the normal "1" write is used for the bit line BL, and the normal "1" data write is performed for the word line WL. Is applied. FIG.
Indicates the high potential VWLH applied to the word line and the high potential VBLH applied to the bit line output from the potential generation circuit 29 in this case. After the power is turned on, a potential VWLH0 higher than the word line high potential VWLH1 used for normal "1" data writing is generated for a predetermined time T. The bit line high potential VBLH is constant.

FIG. 22 shows the initializing operation, the potentials of the word line WL and the bit line BL, and the body potential VB of the memory cell at that time. In the initialization operation,
By applying a higher potential VWLH0 to the word line WL than at the time of normal "1" writing, the body potential VB is sufficiently increased to cause impact ionization. This allows
"1" data is surely written. After that, the word line WL
Is set to the negative potential VWLL to hold data, and thereafter normal operation is performed. In the figure, the operation waveform of “1” data writing is shown.

[Third Initialization Mode] In the third initialization mode, the same high potential as the normal "1" write is used for the word line WL, and the normal "1" data is written to the bit line BL. Is applied. FIG.
Indicates the high potential VWLH applied to the word line and the high potential VBLH applied to the bit line output from the potential generation circuit 29 in this case. After the power is turned on, a potential VBLH0 higher than the bit line high potential VBLH1 used for normal "1" data writing is generated for a predetermined time T. The word line high potential VWLH is constant.

FIG. 24 shows the initializing operation, the subsequent potentials of the word line WL and bit line BL, and the body potential VB of the memory cell at that time. In the initialization operation,
Although the same high potential VWLH is applied to the word line WL as in normal "1" writing, the potential VBLH0 is used for the bit line BL higher than in normal "1" writing, so that impact ionization is effectively performed. Can be caused. As a result, "1" data is reliably written.
After that, the word line WL is set to the negative potential VWLL to hold the data state, and thereafter the normal operation is performed. In the figure,
The operation waveform of "1" data writing is shown.

[Fourth Initialization Mode] In the fourth initialization mode, both the word line WL and the bit line use the same high potential as in normal "1" writing. However, in this case, in order to surely perform the initialization, it is desirable to set the time of the initialization operation to be longer than, for example, the normal writing time. If the initialization operation time is set to be longer than a certain level, the "1" data state can be initialized.

The above-mentioned initialization modes are arranged in the order of the degree of certainty of the initialization of the “1” data state, and the first initialization mode, the second initialization mode, the third initialization mode, and the fourth
In the initialization mode. This is because the body potential during the initialization operation becomes lower in this order. However, even in the initialization mode with low reliability, it is possible to perform a more reliable initialization operation by changing the memory cell structure as described below.

FIG. 25 shows such a memory cell structure in FIG.
Are shown correspondingly. In contrast to the structure of FIG.
5, the insulating film 11 (BOX) separating the silicon layer 12
The difference is that the back gate electrode 32 is embedded in the film. The back gate 32 is formed between the gate insulating film 31 and the bottom surface of the silicon layer 12 serving as the body of the transistor.
Capacitively coupled via. FIG. 26 shows an equivalent circuit of the memory cell MC in this case.

In such a memory cell structure, a negative fixed potential (a positive fixed potential when the memory cell is a p-channel) is applied to, for example, the back gate 32. As a result, it is possible to improve the retention characteristics of “1” data in the data retention state. The basic operation of the memory cell is achieved by controlling the body potential by the capacitive coupling from the front gate 13 as described above. However, the present inventors have found that when the capacitance coupling is too large, the threshold voltage difference between the data “0” and “1” cannot be sufficiently obtained.

On the other hand, by adding the back gate 32 and capacitively coupling to the body, the capacitance coupling ratio from the front gate 13 to the body can be reduced, whereby the data "0", “1”
Can be secured larger.

FIG. 27 shows an equivalent circuit of a memory cell array using such a memory cell MC with a back gate. The back gate terminal VB is commonly connected in the entire memory cell array. Alternatively, the back gate 32 may be patterned as a word line WL2 parallel to the word line WL1 formed by the front gate 13. In this case, the equivalent circuit is as shown in FIG. In this case, the word line WL1 connected to the front gate and the word line WL2 connected to the back gate can be driven in synchronization.

More specifically, the word line WL2 connected to the back gate is kept negative in the data holding state, and has a higher potential in synchronization with the word line WL1 in the data writing state. As a result, the selective write characteristics and data retention characteristics of data “1” and “0” in the memory cell array can be improved.

The memory cell M with such a back gate
When C is used, since the body potential can be controlled by the back gate, the initialization operation is also facilitated. For example, in the case of the initialization operation in which the same potential as the high potential at the time of writing “1” is applied to the word line and the bit line, which has been described as the fourth initialization mode, the body is raised by the back gate and the potential is increased. If this is the case, more reliable "1" data can be initialized. This is the following fifth initialization mode.

[Fifth Initialization Mode] FIG. 29 shows a high potential VWLH applied to the word line and a high potential VBLH applied to the bit line output from the potential generation circuit 29 in this case.
Further, a potential VBG applied to the back gate is shown. Word line high potential VWLH and bit line high potential VBL
H is constant. On the other hand, the potential VBG to be applied to the back gate is set for a certain time T after the power is turned on.
High potential VBG0 and then the potential V necessary for normal operation
Becomes BG1.

FIG. 30 shows the potentials of the word line WL, bit line BL and back gate BG after the initialization operation, and the body potential VB of the memory cell at that time. In the initialization operation, the same high potential VWLH is applied to the word line WL as in normal "1" writing, and the same potential VBLH is applied to the bit line BL as in normal "1" writing.
, But a potential VBG0 higher than the normal operation is applied to the back gate BG. As a result, the body potential can be increased, and the impact ionization can be effectively generated, so that "1" data is reliably written. Thereafter, the word line WL is set to the negative potential VWLL to hold the data state, and the back gate BG is also set to the potential VBG1 in the normal operation, and thereafter the normal operation is performed. In the figure, the operation waveform of “1” data writing is shown.

[Sixth Initialization Mode] In all of the initialization operations described so far, the memory cell is operated as a pentode to write "1" data by impact ionization. An initialization operation using the same is also possible. FIG. 31 shows a state in which a low potential VWLL in a data holding state is applied to a word line, a positive potential is applied to a bit line, and a GIDL current flows through a memory cell. The larger the difference between the drain potential Vd given from the bit line and the gate potential VWLL given from the word line, the larger the GIDL current.

In particular, when a memory cell with a back gate is used, since the body potential can be controlled, a larger GIDL current can flow, and by using this, an effective "1" data initialization can be performed. it can. FIG. 32 shows the high potential VWLH applied to the word line and the high potential VBLH applied to the bit line output from the potential generation circuit 29 in this case. The word line high potential VWLH is constant. The bit line high potential VBLH is set to the high potential VBLH0 for a predetermined time T after the power is turned on, and then to the potential VBLH1 necessary for normal operation.

FIG. 33 shows the potentials of the word line WL, bit line BL and back gate BG after the initialization operation, and the body potential VB of the memory cell at that time. That is, in the initialization operation, the word line WL is set to the low potential VWLL in the data holding state, the bit line BL is applied with the potential VBLH0 higher than the normal “1” write, and at the same time, the back gate BG is set to the higher potential VBG0 than the normal operation. give. As a result, a large GIDL current can flow, and "1" data is written. Thereafter, the word line WL is set to the negative potential VWLL to hold the data state, and the back gate BG is also set to the potential VBG1 in the normal operation, and thereafter the normal operation is performed. In the figure, the operation waveform of “1” data writing is shown.

[0059]

As described above, according to the present invention, one memory cell is formed by a simple MIS transistor having a floating semiconductor layer as a body region, and the cell size is reduced to 4F ^2. Can be. The source of the transistor is connected to a fixed potential line, and reading, rewriting and refreshing are controlled only by controlling the bit line connected to the drain and the word line connected to the gate electrode. That is, data can be rewritten in arbitrary bit units. Further, according to the present invention, by providing an initialization mode in which the first data state is forcibly written to all the memory cells of the memory cell array,
Subsequent normal operation can be guaranteed.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a memory cell structure of a DRAM according to the present invention.

FIG. 2 is an equivalent circuit of a memory cell of the DRAM.

FIG. 3 is a layout of a memory cell array of the DRAM.

FIG. 4 is a sectional view taken along line A-A 'and B-B' of FIG. 3;

FIG. 5 is a diagram showing a relationship between a word line potential and a bulk potential of the DRAM cell.

FIG. 6 is a diagram for explaining a reading method of the DRAM cell.

FIG. 7 is a diagram for explaining another reading method of the DRAM cell.

FIG. 8 is a diagram showing operation waveforms of “1” data read / refresh of the DRAM.

FIG. 9 is a diagram showing an operation waveform of “0” data read / refresh of the DRAM.

FIG. 10 shows “1” data read / “0” of the DRAM.
FIG. 6 is a diagram illustrating operation waveforms of data writing.

FIG. 11 shows “0” data read / “1” of the same DRAM.
FIG. 6 is a diagram illustrating operation waveforms of data writing.

FIG. 12 shows “1” by another reading method of the DRAM.
FIG. 4 is a diagram showing operation waveforms of data read / refresh.

FIG. 13 shows “0” by another reading method of the DRAM.
FIG. 4 is a diagram showing operation waveforms of data read / refresh.

FIG. 14 shows “1” by another reading method of the DRAM.
FIG. 9 is a diagram showing operation waveforms of data reading / data writing “0”.

FIG. 15 shows “0” by another reading method of the DRAM.
FIG. 9 is a diagram showing operation waveforms of data read / “1” data write.

FIG. 16 is a diagram showing a relationship between a drain current Id and a gate voltage Vg by a pentode operation of a MOS transistor using a body potential as a parameter.

FIG. 17 is a diagram showing an equivalent circuit of the DRAM according to the embodiment of the present invention.

FIG. 18 is a diagram showing an equivalent circuit of a cell array of the DRAM.

FIG. 19 is a diagram showing an output potential waveform of a potential generation circuit necessary for an initialization mode of the DRAM.

FIG. 20 is a waveform chart for explaining an initialization mode of the DRAM.

FIG. 21 is a diagram showing an output potential waveform of a potential generation circuit necessary for another initialization mode of the DRAM.

FIG. 22 is a waveform chart for explaining the initialization mode.

FIG. 23 is a diagram showing an output potential waveform of a potential generation circuit necessary for another initialization mode of the DRAM.

FIG. 24 is a waveform chart for explaining the initialization mode.

FIG. 25 is a diagram showing a structure of another DRAM cell.

FIG. 26 is an equivalent circuit diagram of the DRAM cell.

FIG. 27 is an equivalent circuit of a cell array using the same DRAM cell.

FIG. 28 is an equivalent circuit of another cell array using the same DRAM cell.

FIG. 29 is a diagram showing an output potential waveform of a potential generation circuit necessary for an initialization mode of the DRAM.

FIG. 30 is a waveform chart for describing an initialization mode of the DRAM.

FIG. 31 is a diagram showing GIDL current characteristics of a memory cell.

FIG. 32 is a diagram showing an output potential waveform of a potential generation circuit necessary for an initialization mode using a GIDL current.

FIG. 33 is a waveform chart for explaining the initialization mode.

[Explanation of symbols]

10 silicon substrate, 11 silicon oxide film, 12 silicon layer, 13 gate electrode, 14 drain diffusion layer,
15 Source diffusion layer, 16 Gate insulating film, 21 Memory cell array, 22 Column gate, 23 Sense amplifier, 24 Column decoder, 25 Row decoder / word line driver, 26 Address buffer, 27 I / O
Buffer 28 power on detection circuit 29 potential generating circuit 30 control circuit

Continued on the front page F term (reference) 5F083 AD69 HA02 LA12 LA16 5M024 AA58 AA70 AA99 BB02 BB08 BB09 BB32 BB35 BB36 CC20 CC22 CC70 CC92 HH01 HH11 PP03 PP04 PP05 PP07 PP10

Claims (10)

[Claims] 1. A plurality of memory cells are arranged using one MIS transistor formed in a floating semiconductor layer as a 1-bit memory cell, and gates of memory cells arranged in a first direction are connected to a word line. 2 has a memory cell array in which the drains of the memory cells are connected to bit lines, and the sources of all the memory cells are connected to a fixed potential line. Dynamically storing a first data state in which the layer is set to a first potential and a second data state in which a forward current is applied to the drain junction to set the semiconductor layer to a second potential. A semiconductor memory device having an initialization mode for writing all memory cells of the memory cell array to the first data state. 2. The first data state is written by causing the memory cell to perform pentode operation to cause impact ionization near a drain junction, and the second data state is written by capacitive coupling from the gate. 2. The semiconductor memory device according to claim 1, wherein data is written by applying a forward bias between said semiconductor layer to which a predetermined potential is applied and said drain. 3. In a data write mode, a first control potential higher than the reference potential is applied to a selected word line using the fixed potential line as a reference potential, and a second control potential lower than the reference potential to an unselected word line. A control potential is applied to the selected bit line, a third control potential higher than the reference potential and a fourth control potential lower than the reference potential are applied to the selected bit line in accordance with the first and second data states, respectively. 2. The semiconductor memory device according to claim 1, wherein in the activation mode, a control potential higher than the first control potential and the third control potential is applied to a word line and a bit line, respectively. 4. In a data write mode, a first control potential higher than the reference potential is applied to a selected word line using the fixed potential line as a reference potential, and a second control potential lower than the reference potential to an unselected word line. A control potential is applied to the selected bit line, a third control potential higher than the reference potential and a fourth control potential lower than the reference potential are applied to the selected bit line in accordance with the first and second data states, respectively. 2. The semiconductor memory device according to claim 1, wherein in the activation mode, a control potential higher than the first control potential is applied to a word line, and the third control potential is applied to a bit line. 3. 5. In a data write mode, a first control potential higher than the reference potential is applied to a selected word line using the fixed potential line as a reference potential, and a second control potential lower than the reference potential to an unselected word line. A control potential is applied to the selected bit line, a third control potential higher than the reference potential and a fourth control potential lower than the reference potential are applied to the selected bit line in accordance with the first and second data states, respectively. 2. The semiconductor memory device according to claim 1, wherein in the activation mode, the first control potential is applied to a word line, and a control potential higher than the third control potential is applied to a bit line. 3. 6. In a data write mode, a first control potential higher than the reference potential is applied to a selected word line using the fixed potential line as a reference potential, and a second control potential lower than the reference potential to an unselected word line. A control potential is applied to the selected bit line, a third control potential higher than the reference potential and a fourth control potential lower than the reference potential are applied to the selected bit line in accordance with the first and second data states, respectively. 2. The semiconductor memory device according to claim 1, wherein the first control potential is applied to a word line and the third control potential is applied to a bit line in the activation mode. 3. 7. In a data write mode, a first control potential higher than the reference potential is applied to a selected word line using the fixed potential line as a reference potential, and a second control potential lower than the reference potential to an unselected word line. A control potential is applied to the selected bit line, a third control potential higher than the reference potential and a fourth control potential lower than the reference potential are applied to the selected bit line in accordance with the first and second data states, respectively. In the normalization mode, the word line is supplied with the second control potential, the bit line is supplied with a control potential higher than the third control potential, and the data is written to the first data state by a leak current at the drain junction. The semiconductor memory device according to claim 1, wherein: 8. The semiconductor memory device according to claim 1, wherein said memory cell has an auxiliary gate for controlling a potential of said semiconductor layer by capacitive coupling, separately from said gate. 9. The semiconductor memory device according to claim 8, wherein a potential higher than a steady state is applied to said auxiliary gate in said initialization mode. 10. The semiconductor memory device according to claim 1, wherein the initialization mode is automatically executed upon detecting power-on inside the chip.