JP2002329795A - Semiconductor memory and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device using memory cells having a simple transistor structure. SOLUTION: While trenches 23a, 23b are formed spaced apart a predetermined distance in an element formation region divided by an element separating insulation film 21 on p-type silicon substrate, the sandwiched region between trench 23a and 23b is defined as an element region 22, and a gate insulation film 24 is formed on its side faces. Then gate electrodes 25a, 25b are buried in the trenches 23a, 23b. A drain diffusion layer 27 and a source diffusion layer 28 are formed individually on the upper face and on the bottom face of the element region 22 to configure a vertical MISFET. The gate electrodes 25a, 25b are individually connected to metal wirings 26a, 26b which are a word line WL and a back word line BWL. A bit line (BL) 31 is connected to the drain diffusion layer 27. The data is dynamically memorized based on the floating potential of the element region 22 in the MISFET.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device for dynamically storing data using a channel body of a MISFET as a storage node.

[0002]

2. Description of the Related Art In a conventional DRAM, a memory cell is constituted by a MOS transistor and a capacitor. DR
The miniaturization of AM has been greatly advanced by adopting a trench capacitor structure or a stacked capacitor structure. Current,
The size (cell size) of the unit memory cell is reduced to an area of 2F × 4F = 8F ² , where F is the minimum processing dimension. That is, when the minimum processing dimension F decreases with generation and the cell size is generally αF ² , the coefficient α also decreases with generation, and when F = 0.18 μm, α = 8
Has been realized.

[0003] In order to secure the same trend in cell size or chip size as in the past, F <0.
At 18 μm, α <8, and at F <0.13 μm, α
It is required to satisfy <6, and how to form the cell size in a small area together with the fine processing is a major issue. Therefore, various proposals have been made to make the memory cell of one transistor / one capacitor to have a size of 6F ² or 4F ² . However, there are technical difficulties such as the need to make the transistors vertical, problems such as increased electrical interference between adjacent memory cells, and difficulties in manufacturing techniques such as processing and film formation. Absent.

[0004] On the other hand, some DRAMs have been proposed as follows, in which one transistor is used as a memory cell without using a capacitor. JOHN E.LEISS et al, "dRAM Design Using the Taper-
Isolated Dynamic Cell "(IEEE JOURNAL OF SOLID-STATE
CIRCUITS, VOL.SC-17, NO.2, APRIL 1982, pp337-344) JP-A-3-171768 Marnix R. Tack et al, "The Multistable Charge-Cont
rolled Memory Effect in SOI MOS Transistors at Low
Temperatures "(IEEE TRANSACTIONS ON ELECTRONDEVICE
S, VOL. 37, MAY, 1990, pp1373-1382) Hsing-jen Wann et al, "A Capacitorless DRAM Cell
on SOI Substrate "(IEDM93, pp635-638)

[0005]

The memory cell of the present invention is constructed using MOS transistors having a buried channel structure. The surface inversion layer is charged and discharged by using a parasitic transistor formed in the tapered portion of the element isolation insulating film to perform binary storage. Memory cells use MOS transistors individually separated from each other in wells, and set a threshold value determined by the well potential of the MOS transistors to binary data.
Are constituted by MOS transistors on an SOI substrate. By applying a large negative voltage from the side of the SOI substrate and utilizing the accumulation of holes at the interface between the oxide film of the silicon layer and the interface, binary storage is performed by discharging and injecting the holes. Are constituted by MOS transistors on an SOI substrate. Although there is only one MOS transistor in structure, a reverse conductivity type layer is formed on the surface of the drain diffusion layer, and the structure is such that a writing PMOS transistor and a reading NMOS transistor are substantially combined integrally. Using the substrate region of the NMOS transistor as a floating node, binary data is stored according to the potential.

However, since the structure is complicated and a parasitic transistor is used, there is a problem in controllability of characteristics. Although the structure is simple, both the drain and the source of the transistor need to be connected to the signal line to control the potential. In addition, since the well is separated, the cell size is large, and rewriting for each bit cannot be performed. In such a case, the potential control from the SOI substrate side is required, so that it is not possible to rewrite for each bit, and there is a problem in controllability. Requires a special transistor structure, and a memory cell requires a word line, a write bit line, a read bit line, and a purge line, so that the number of signal lines increases.

An object of the present invention is to provide a semiconductor memory device capable of dynamic storage by a memory cell having a simple transistor structure and a method of manufacturing the same.

[0008]

In a semiconductor memory device according to the present invention, a 1-bit memory cell has a first data state in which a floating channel body is set to a first potential and a second data state in which a floating channel body is set to a second potential. The two MISFETs are configured to dynamically store two data states. The MISFET has a semiconductor substrate, an element region of the first conductivity type serving as the channel body partitioned by the semiconductor substrate, and the element region interposed therebetween. First and second gate electrodes buried in the two trenches formed in the above and opposed to the side surfaces of the element region, a second conductivity type drain diffusion layer formed on the surface of the element region, and a predetermined depth Vertical MIS having a source diffusion layer of a second conductivity type embedded at a position
It is an FET.

Specifically, in the present invention, the first data state is written by causing the MIS transistor to perform pentode operation to cause impact ionization near the drain junction, and the second data state is written by the first gate. The data is written by applying a forward bias between the drain and the semiconductor layer to which a predetermined potential is applied by capacitive coupling from the semiconductor device. Alternatively, as a method of writing the first data state, a gate-induced drain leak (GI
DL: Gate-Induced Drain Lea
kage) Current can also be used.

In the present invention, MISF
A plurality of ETs are divided by an element isolation insulating film while sharing a source diffusion layer, are arranged in a matrix, and a plurality of MISFETs arranged in a first direction have drain diffusion layers connected to bit lines and intersected with the first direction. The first gate electrodes of a plurality of MISFETs arranged in the second direction are connected to word lines, and the second gate electrodes are connected to back word lines, respectively, to form a memory cell array.

According to the present invention, one memory cell includes:
It is formed by a simple single vertical MISFET having a floating channel body, and the cell size can be reduced. The source of the MISFET is connected to a fixed potential, and reading and reading are performed only by controlling the bit line connected to the drain and the word line connected to the gate.
Rewriting and refresh control are performed. That is, data can be rewritten in arbitrary bit units. Also, M
The second gate electrode facing the body of the ISFET is capacitively coupled to the body by applying, for example, a potential lower than a reference potential applied to the source (fixed potential or a potential that changes in synchronization with the first gate electrode). By optimizing the capacitance coupling ratio of the first gate electrode to the body,
The difference between the threshold voltages of “0” and “1” data can be increased.

The memory cell array has one M.sub.M in each rectangular element formation region partitioned by an element isolation insulating film.
There are a method of forming an ISFET and a method of forming two MISFETs by sharing a second gate electrode. In the former case, one MISFET is formed by burying the first and second gate electrodes in trenches formed at both ends of the rectangular element formation region in the bit line direction.
In this case, the back word lines are driven in synchronization with the word lines forming a pair, and can control the potential of the channel body.

In the latter case, trenches are formed in the rectangular element formation region at both ends and the center in the bit line direction, and the second gate electrodes embedded in the center trenches are shared, and both ends are shared. Two MISFETs each having the first gate electrode embedded in the trench are formed. In this case, the second gate electrode and the back word line connected thereto are connected to two MISFEs adjacent in the bit line direction.
A fixed potential is provided that is shared by T and keeps the side face of the second gate electrode facing the majority carrier accumulation state.

According to the method of manufacturing a semiconductor memory device of the present invention, there is provided a step of forming a rectangular element formation region defined by an element isolation insulating film on a semiconductor substrate, and ion-implanting impurities into the semiconductor substrate to form an element. Forming a source diffusion layer across the bottom of the region; and
Forming at least two trenches at a predetermined distance; and forming a gate insulating film on a side surface of an element region sandwiched between the two trenches, and embedding first and second gate electrodes in the trenches. And forming a drain diffusion layer on the surface of the element region.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to the description of the embodiments of the present invention, the principle of the present invention will be described. FIG. 1 shows the principle structure of a DRAM cell according to the present invention using an SOI substrate. The memory cell MC is configured by an N-channel MISFET having an SOI structure. That is, an SOI substrate in which a silicon oxide film 11 is formed as an insulating film on a silicon substrate 10 and a p-type silicon layer 12 is formed on the silicon oxide film 11 is used. A gate electrode 13 is formed on the silicon layer 12 of the substrate via a gate oxide film 16 and is self-aligned with the gate electrode 13 to form an n.
Form source / drain diffusion layers 14 and 15 are formed.

The source and drain diffusion layers 14 and 15 are formed to a depth reaching the silicon oxide film 11 at the bottom. Therefore, if the channel body made of the p-type silicon layer 12 is separated by an oxide film in the channel width direction (the direction perpendicular to the plane of the drawing), the bottom surface and the side surfaces in the channel width direction are insulated and separated from each other. The channel length direction is in a floating state in which a pn junction is separated. When memory cells MC are arranged in a matrix, gate 13 is connected to word line WL, source 15 is connected to a fixed potential line (ground potential line), and drain 14 is connected to bit line BL.

The D composed of this n-channel type MISFET
The operation principle of the RAM cell utilizes the potential control of the floating channel body (the p-type silicon layer 12 that is isolated from the others). In other words, when the MISFET is operated in the pentode region, a large current flows from the drain diffusion layer 14 and impact ionization occurs near the drain junction. When the channel body holds the majority carrier hole, the first potential state is maintained. , And this state is assumed to be, for example, data “1”. Drain diffusion layer 14
A state in which the pn junction between the semiconductor device and the p-type silicon layer 12 is forward-biased to lower the potential of the p-type silicon layer 12 to data “0”. The source diffusion layer 15 is maintained at a fixed potential, for example, a ground potential.

The data "0" and "1" are stored as the difference between the potentials of the channel bodies, and thus as the difference between the threshold voltages of the MISFETs. That is, the threshold voltage Vth1 of the data “1” state where the potential of the body is high due to the accumulation of holes
Is lower than the threshold voltage Vth0 in the data “0” state. In order to maintain the "1" data state in which holes serving as majority carriers are accumulated in the body, it is necessary to apply a negative bias voltage to the word lines. This data holding state does not change even if a read operation is performed, unless a reverse data write operation (erase) is performed. That is,
Unlike a one-transistor / one-capacitor DRAM that uses the charge storage of a capacitor, nondestructive reading is possible.

There are several data reading methods. Word line potential VWL and channel body potential VB
Is as shown in FIG. 2 in relation to data "0" and "1". Therefore, for example, in the first method of reading data, a read potential that is intermediate between the threshold voltages Vth0 and Vth1 of the data “0” and “1” is applied to the word line WL. No current flows,
The fact that a current flows in a memory cell of "1" data is used. Specifically, for example, the bit line BL is set to a predetermined potential V
BL is precharged, and then the word line WL is driven. As a result, in the case of "0" data, the bit line precharge potential VBL does not change, and in the case of "1" data, the precharge potential VBL decreases.

In the second read method, a current is supplied to the bit line BL after the word line WL is activated,
The fact that the rising speed of the bit line potential varies depending on the degree of conduction of “0” and “1” is used. Briefly, the bit line BL is precharged to 0 V, the word line WL is started, and the bit line current is supplied. At this time, data difference can be determined by detecting a difference in potential rise of the bit line by using a dummy cell.

In the present invention, in order to selectively write "0" data, a hole is formed only from the body of the memory cell selected by the potential of the word line WL and bit line BL selected in the memory cell array. In order to emit the light, the capacitive coupling between the word line WL and the body becomes essentially. In the state where holes are accumulated in the body by data "1", the word line is sufficiently biased in the negative direction, and the gate-substrate capacitance of the memory cell becomes the gate oxide film capacitance (that is, a depletion layer is formed on the surface). (It is not formed).

FIG. 1 shows a MISFET having a floating channel body utilizing an SOI structure. In the present invention, an MISFET having a floating channel body is used without using an SOI substrate.
Construct an FET. The configuration of the basic unit memory cell MC is shown in FIGS. 3 and 4A to 4C. FIG. 3 is a plan view, and FIGS. 4A, 4B, and 4C respectively show A-
It is A ', BB', and CC 'sectional drawing.

That is, in the present invention, the memory cell MC is constituted by a vertical MISFET. p-type silicon substrate 2
The element isolation insulating film 21 is buried in 0 by, for example, an STI (Shallow Trench Isolation) method, thereby defining a rectangular element formation region. A trench 23 deeper than the element isolation insulating film 21 is formed at one end of the element forming region, a gate insulating film 24 is formed on a side surface of the element region 22 serving as a channel body exposed to the trench 23, and a gate electrode is formed in the trench 23. 25 is embedded. An n-type drain diffusion layer 27 is formed on the surface of the element region 22, and an n-type source diffusion layer 28 is formed at a predetermined depth so as to cross the element region 22.

As described above, the vertical MISFET having the channel body which is separated from the other by the source diffusion layer 28 and the element isolation insulating film 21 and becomes floating is formed in the memory cell M
C. When a memory cell array is configured by arranging the memory cells MC in a matrix, the source diffusion layer 28 is formed continuously as an object common to a plurality of MISFETs. The gate electrodes 25 of the MISFETs arranged in the first direction are commonly connected to a metal wiring 26 serving as a word line WL. The drain diffusion layers 27 of the MISFETs arranged in a second direction crossing the first direction are
It is connected to a bit line (BL) 31 disposed on the 0.

In the basic DRAM cell described so far,
From the operating principle, it is important how much the threshold voltage difference between data "0" and "1" can be increased.
As is clear from the above operation principle, the data writing and holding characteristics are determined by controlling the body potential by the capacitive coupling from the gate. However, since the threshold voltage is applied to the body potential with a substantially square root, It is not easy to realize a large threshold voltage difference between “0” and “1” data. In addition, in the above-described write operation, the memory cell of "0" write operates as a triode, and when a channel is formed, the gate and the body are not capacitively coupled, and the body potential cannot be increased.

Therefore, in the present invention, FIGS.
With respect to the basic DRAM cell structure described in FIGS.
In addition to a main gate electrode (first gate electrode) used for forming a channel, an auxiliary gate electrode (second gate electrode) for capacitively coupling to a channel body of the MISFET and controlling a body potential is provided. The second gate electrode is driven, for example, in synchronization with the first gate electrode. As a result, reliable writing can be performed, and the difference between the threshold voltages of “0” and “1” data can be increased. Alternatively, by keeping the second gate electrode at a fixed potential lower than the source potential, for example, and keeping the second gate electrode side in a majority carrier accumulation state, the data threshold voltage difference between the “0” and “1” data is similarly reduced. Can be bigger.

Hereinafter, embodiments of the present invention will be described.
FIG. 5 shows a vertical MI which is a DRAM cell according to the embodiment.
FIG. 6A is a plan view of the SFET, and FIGS. 6A, 6B, and 6C are cross-sectional views taken along AA ′, BB ′, and CC ′ in FIG. 5, respectively.

An element isolation insulating film 21 is buried in the p-type silicon substrate 20 by the STI method, thereby defining a rectangular element formation region as shown by a dashed line in FIG. The trenches 23a and 23 are formed at both ends in the longitudinal direction of the element forming region.
b is formed deeper than the bottom of the element isolation insulating film 21, and a region 22 sandwiched between the trenches 23a and 23b is an element region serving as a channel body. Gate insulating films 24 are formed on the opposing side surfaces of the element region 22 exposed in the trenches 23a and 23b, respectively.
Gate electrodes 25a and 25b are buried in 3a and 23b.

Trench formation and gate electrodes 25a, 25b
By performing ion implantation before the embedding process of
At the bottom of the element region 22, an n-type source diffusion layer 28 is formed. A gate electrode 25 is formed on the surface of the element region 22.
After burying the a and 25b, ion implantation is performed to form an n-type drain diffusion layer 27. In this way, the vertical MISFE in which the two gate electrodes 25a and 25b are embedded is provided.
T constitutes a memory cell MC.

The gate electrodes 25a and 25b are connected to metal wirings 26a and 26b to be word lines WL and back word lines BWL, respectively. The upper and side surfaces of these word lines WL and back word lines BWL are covered with a silicon nitride film 29. In the actual manufacturing process, as will be described later, a polycrystalline silicon film serving as the gate electrodes 25a and 25b is deposited and formed so as to fill the trenches 23a and 23b to be flat, and further, a metal wiring layer and a silicon nitride film are formed. After continuous deposition, these stacked films are patterned to form word lines WL and back word lines BWL.

An interlayer insulating film 30 is formed on the MISFET thus formed, and a bit line (BL) 3
1 is provided. The bit line 31 is connected to the drain diffusion layer 27 of the MISFET.

The configuration of the memory cell array in which the MISFETs described above are arranged in a matrix is as shown in FIGS. 7 and 8A to 8C. FIG. 7 is a plan view, and FIGS. 8A, 8B and 8C are AA ', BB' and C-
It is C 'sectional drawing. The structure is shown in FIG. 5 and FIGS.
Since it is the same as that described in C, detailed description will be omitted. The bit line 31 is connected to a bit line contact formed in the interlayer insulating film 30 by a contact plug 4 made of polycrystalline silicon.
1 is buried and formed by metal wiring so as to connect the contact plug 41.

In this memory cell array, trenches 23a, 23a are formed at both ends of the rectangular element formation region in the bit line direction.
b is formed, and two gate electrodes 25a, 25b
Are embedded to form one MISFET. In this case, as shown in FIG. 7, the bit line BL and the word line W
Assuming that the line and space of L and the back word line BWL are formed with the minimum processing size F, the unit DRAM cell has an area of 8F ² as shown by the broken line in FIG.

In this memory cell array configuration, a pair of word lines WL and back word lines BWL are provided for a plurality of memory cells arranged in the bit line direction. Therefore, the back word line BWL is driven in synchronization with the drive of the word line WL, and the potential of the channel body of each MISFET can be optimally controlled. That is, when the word line WL is set to the negative potential and the "1" data is held, the holding state of the "1" data can be favorably maintained by applying the negative potential to the back word line BWL forming a pair. . When data writing is performed by raising the potential of the word line WL, the channel body potential can be raised by capacitive coupling by raising the back word line BWL, thereby enabling reliable data writing.
In the case of "0" data writing, even if a channel is formed on the word line WL side, the channel body potential can be increased by the back word line BWL, so that "0" data writing can be performed reliably. As described above, "0" and "1" data having a large threshold voltage difference can be stored.

A negative potential is applied to an unselected word line WL to hold data. At this time, the back word line BWL forming a pair is also set to a negative potential to control the channel body potential low. Therefore, when writing “0” data in another memory cell along the same bit line,
Data destruction in non-selected cells holding "1" data is also reliably prevented.

In the above embodiment, one MISFET is formed in one element formation region partitioned by the element isolation insulating film. However, one MISFET is formed in one element formation region partitioned by the element isolation insulation film. Two MISFETs can be formed by sharing the connected gate electrodes.
The configuration of the memory cell array in this case is shown in FIGS.
Shown in FIG. 9 is a plan view, and FIG. 10 is a sectional view taken along the line AA ′. The cross sections BB ′ and CC ′ of FIG. 9 are the same as FIG. 8B and FIG. 8C, respectively.

In the case of this embodiment, the element isolation insulating film 2
A trench 23a is formed at both ends in the longitudinal direction (bit line direction) of the rectangular element formation region defined by 1, and a trench 23b is also formed at the center. The region sandwiched by these three trenches 23a and 23b is two M
This becomes the element region 22 of the ISFET. Central trench 2
A gate electrode 25b shared by two MISFETs is buried in 3b, and respective gate electrodes 23a of two MISFETs are buried in trenches 23a at both ends. The gate electrode 25b is formed of two MISFs.
ET are connected to a common back word line BWL, and the gate electrodes 25a are connected to independent word lines WL.
Other configurations are the same as those of the above embodiment, and the same reference numerals are given to the portions corresponding to the above embodiment, and the detailed description is omitted.

In this embodiment, two word lines W
Since the common back word line BWL is arranged between L, if the back word line BWL is driven in synchronization with the selected word line WL, it causes data destruction of the memory cells along the non-selected word line. . Therefore, in the case of this embodiment, the back word line BWL is set and operated, for example, at a negative fixed potential. Thereby, the potential control of the channel body by the word line WL is performed while the back word line BWL side of the channel body of the MISFET is maintained in a majority carrier accumulation state (accumulation state) where no inversion layer is formed. Can be.

In the case of this embodiment, as shown in FIG. 9, if the line / space of the bit line BL, word line WL and back word line BWL is formed with the minimum processing size F, the unit DRAM cell is , as shown by the broken line in FIG. 9, the area of 6F ^2.

Next, the manufacturing process of the memory cell array according to the present invention will be described with reference to the embodiment of FIGS. 9 and 10. 11A, 11B to 17A, 17
B is a cross section taken along line AA ′ of FIG. 9 (corresponding to FIG. 10) and B
9B shows a manufacturing process in a section taken along the line −B ′ (corresponding to FIG. 8B).

As shown in FIGS. 11A and 11B, a buffer oxide film 51 and a silicon nitride film 52 are deposited on a p-type silicon substrate 20, and are patterned by a lithography process and an RIE process to form a mask covering an element formation region. Form. Using this mask, the silicon substrate 20 is
Etching is performed by E to form an element isolation groove 53 so as to partition a rectangular element formation region.

Next, as shown in FIGS. 12A and 12B, an element isolation insulating film 21 such as a silicon oxide film is buried in the element isolation groove 53. Next, ion implantation with high acceleration energy is performed to form an n-type source diffusion layer 28 that passes under the element isolation insulating film 21 and is continuous over the entire cell array region, as shown in FIGS. 13A and 13B. In addition, ion implantation for controlling a threshold value is performed as necessary in a region serving as a channel body above the source diffusion layer 28.

Next, as shown in FIGS. 14A and 14B, a mask made of a silicon nitride film 54 is formed, and the silicon substrate 20 is etched by RIE, so that trenches 23a and 23a are formed at both ends and the center of one element formation region. 23b is formed. The depth of the trenches 23a and 23b is set to at least the depth reaching the source diffusion layer 28. In the case of the drawing, the trenches 23a and 23b are set to have a depth deeper than the bottom surface of the element isolation insulating film 21 and to stop in the source diffusion layer 28. Thus, two rectangular element regions 22 are formed in one element formation region. Both surfaces of the element region 22 in the word line WL direction are in contact with the element isolation insulating film 21 as shown in FIG. 14B, and side surfaces in the bit line BL direction are exposed to the trenches 23a and 23b.

Next, the silicon nitride film 54 is removed, and FIG.
5A and FIG. 15B, the trenches 23a and 23
The gate insulating film 24 is formed on the side surface of the element region 22 exposed to the gate electrode b. Then, a polycrystalline silicon film 25 serving as a gate electrode is deposited so as to fill the trenches 23a and 23b so as to be flattened, a metal wiring layer 26 such as WSi is further deposited, and a silicon nitride film 55 is deposited thereon. These silicon nitride film 29a, metal wiring layer 26 and polycrystalline silicon film 25 are patterned to form polycrystalline silicon gate electrodes 25a and 25b embedded in trenches 23a and 23b, as shown in FIGS. 16A and 16B. ,
Metal interconnections 26a and 26b are formed to commonly connect them as a word line WL and a back word line BWL. The silicon nitride film 29a on the metal wires 26a and 26b is left as a part of the silicon nitride film 29 covering the word lines WL and the back word lines BWL shown in FIG.

Next, as shown in FIGS. 17A and 17B, a silicon nitride film 29b is deposited and etched by RIE to form a word line WL and a back word line B.
Leave on the side wall of WL. Then, ion implantation is performed to form an n-type drain diffusion layer 27 on the surface of each element region 22. Thereafter, although not shown in the manufacturing process, an interlayer insulating film 30 is deposited as shown in FIG. 10, a bit line contact hole is formed, a polycrystalline silicon plug 41 is buried, and a bit line 3 is formed.
1 is formed.

In the above, the manufacturing process has been described for the cell array in which the back word line BWL is shared by the adjacent cells. In the case of the system in which the back word line BWL is provided for each cell shown in FIGS. 7 and 8A to 8C. Also, the same manufacturing process can be applied.

In the above-described embodiments, the widths of the trenches 23a and 23b buried with the gate electrodes and the element region 22 sandwiched by the trenches 23a and 23b are the same. In this case, if the miniaturization is further advanced, there is a possibility that the width of the element region 22 cannot be sufficiently secured. The bit line contact is formed by self-aligning the word line WL and the back word line BWL by covering the periphery of the word line WL and the back word line BWL with the silicon nitride film 29.
If there is a misalignment in the lithography process of the word line WL and the back word line BWL, the bit line contact position shifts, causing a short circuit between the bit line 31 and the gate electrodes 25a and 25b.

To solve this problem, the trenches 23a, 2
It is effective to make the width of 3b narrower than the width of the element region 22. For example, with respect to the cross section of FIG.
FIG. 18 shows a cross section in the case where the width W1 of the bit lines a and 23b in the bit line BL direction is reduced. As a result, the width W2 of the element region 22 is reduced to the width W1 of the trenches 23a and 23b.
It can be secured much larger. Further, the bit line 31 and the gate electrodes 25a, 25b caused by misalignment
Short circuit accident can be prevented.

The same structure is also effective when the back word line BWL is shared by adjacent cells. The structure is shown in FIG. 19 corresponding to the cross section of FIG. The width W2 of the element region 22 is sufficiently larger than the width W1 of the trenches 23a and 23b.

In the above embodiments, the word line WL
Although the gate insulating films 24 on the side and the back word line BWL have the same thickness, the gate insulating films for both sides can be formed separately to have the optimum thickness. For example, FIG. 20 is different from FIG. 10 in that the gate insulating film 24b on the back word line BWL side is replaced with the gate insulating film 2 on the word line WL side.
4A shows an example formed thicker than 4a. The gate insulating film 24b on the back word line BWL side is selected so as to optimize the magnitude of capacitive coupling to the channel body.

The present invention is not limited to the above embodiment. For example, in the embodiment, an n-channel MISFET is used.
It is possible to configure an AM. In the embodiment, the source diffusion layer is formed by ion implantation. However, for example, if an epitaxial substrate having a p-type epitaxial growth layer formed on an n-type diffusion layer is used, the step of ion-implanting the source diffusion layer becomes unnecessary.

[0052]

As described above, according to the present invention, there is provided a semiconductor memory device capable of dynamic storage using a vertical MISFET in which a gate electrode is buried in a trench so that a channel body becomes floating as a unit cell. can do.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a principle structure of a DRAM cell of the present invention using an SOI substrate.

FIG. 2 is a characteristic diagram for explaining the operation principle of the DRAM cell.

FIG. 3 is a plan view illustrating the principle structure of the DRAM cell of the present invention without using an SOI substrate.

FIG. 4A is a sectional view taken along the line A-A 'of FIG. 3;

FIG. 4B is a sectional view taken along line B-B 'of FIG.

FIG. 4C is a sectional view taken along line C-C 'of FIG.

FIG. 5 is a plan view showing a configuration of a DRAM cell according to an embodiment of the present invention.

FIG. 6A is a sectional view taken along line A-A ′ of FIG. 5;

FIG. 6B is a sectional view taken along line B-B 'of FIG.

FIG. 6C is a sectional view taken along the line C-C 'of FIG.

FIG. 7 is a plan view showing a configuration of a DRAM cell array according to an embodiment of the present invention.

FIG. 8A is a sectional view taken along line A-A 'of FIG. 7;

8B is a sectional view taken along line B-B 'of FIG.

8C is a sectional view taken along the line C-C 'of FIG.

FIG. 9 is a plan view showing a configuration of a DRAM cell array according to another embodiment of the present invention.

FIG. 10 is a sectional view taken along line A-A 'of FIG.

11A is a view showing a step of forming an element isolation groove in an AA ′ section of FIG. 8;

FIG. 11B is a view showing a step of forming element isolation grooves in a section taken along line BB ′ of FIG. 8;

FIG. 12A is a view showing a step of embedding an element isolation insulating film in an AA ′ section of FIG. 8;

FIG. 12B is a view showing a step of embedding an element isolation insulating film in a section taken along line BB ′ of FIG. 8;

FIG. 13A is a view showing a source diffusion layer forming step in the AA ′ section of FIG. 8;

FIG. 13B is a view showing a source diffusion layer forming step in a section taken along line BB ′ of FIG. 8;

14A is a view showing a step of forming a trench for burying a gate in the AA ′ section of FIG. 8;

FIG. 14B is a view showing a step of forming a trench for burying a gate in a section taken along line BB ′ of FIG. 8;

FIG. 15A is a view showing a gate embedding step in the AA ′ section of FIG. 8;

FIG. 15B is a view showing a gate embedding step in the BB ′ section of FIG. 8;

FIG. 16A is a diagram showing a word line and back word line patterning process in the AA ′ section of FIG. 8;

FIG. 16B is a diagram showing a word line and back word line patterning process in the BB ′ section of FIG. 8;

17A is a view showing a step of forming a sidewall insulating film and forming a drain diffusion layer of a word line and a back word line in the AA ′ section of FIG. 8;

FIG. 17B is a view showing the step of forming the side wall insulating film and the drain diffusion layer of the word line and the back word line in the section BB ′ of FIG. 8;

FIG. 18 is a sectional view corresponding to FIG. 8A according to another embodiment.

FIG. 19 is a sectional view corresponding to FIG. 10 according to another embodiment.

FIG. 20 is a sectional view corresponding to FIG. 10 according to another embodiment.

[Explanation of symbols]

20 ... p-type silicon substrate, 21 ... element isolation insulating film, 22
... Element region (channel body), 23, 23a, 23b
... Trench, 24, 24a, 24b ... Gate insulating film, 2
5a, 25b gate electrode, 26, 26a, 26b metal wiring (word line WL, back word line BWL), 2
7 ... n-type drain diffusion layer, 28 ... n-type source diffusion layer, 2
9: silicon nitride film, 30: interlayer insulating film, 31: bit line (BL), 41: polycrystalline silicon plug.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Kazumasa Sunouchi 8, Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside the Toshiba Yokohama Office (72) Inventor Takashi Osawa 1 Address F-term in Toshiba Microelectronics Center Co., Ltd. (reference) 5F083 AD02 AD04 HA01 JA35 JA39 JA53 KA01 LA16 MA03 MA06 MA20 NA01 PR25 PR36

Claims (10)

[Claims] 1. A one-bit memory cell includes one MISFET that dynamically stores a first data state in which a floating channel body is set to a first potential and a second data state in which the floating channel body is set to a second potential. Wherein the MISFET is embedded in a semiconductor substrate, a first conductivity type element region serving as the channel body partitioned by the semiconductor substrate, and two trenches formed to sandwich the element region. First and second gate electrodes opposing side surfaces of the region, a second conductivity type drain diffusion layer formed on the surface of the element region, and a second conductivity type source diffusion layer embedded at a predetermined depth position Vertical MI with
A semiconductor memory device, which is an SFET. 2. The method according to claim 1, wherein the first data state is the MISFE.
The write operation is performed by causing T to operate as a pentode to cause impact ionization near the drain junction. The second data state is defined by a channel body provided with a predetermined potential by the capacitive coupling from the first gate electrode and a drain diffusion. 2. The semiconductor memory device according to claim 1, wherein data is written by applying a forward bias between the layers. 3. A plurality of MISFETs are divided by an element isolation insulating film and share a source diffusion layer, are arranged in a matrix, and drain diffusion layers of a plurality of MISFETs arranged in a first direction are connected to bit lines. First memory electrodes of a plurality of MISFETs arranged in a second direction intersecting the first direction are connected to a word line, and the second gate electrode is connected to a back word line to form a memory cell array. 2. The semiconductor memory device according to claim 1, wherein: 4. One MISFET in which first and second gate electrodes are buried in trenches formed at both ends in the bit line direction in each rectangular element formation region partitioned by the element isolation insulating film. 4. The semiconductor memory device according to claim 3, wherein said semiconductor memory device is formed. 5. The semiconductor memory device according to claim 4, wherein said back word line is driven in synchronization with a word line forming a pair to control a potential of a channel body. 6. A second gate buried in each of the rectangular element forming regions defined by the element isolation insulating film at both ends and a central portion in the bit line direction, and embedded in the central trench. Two MIs in which the first gate electrode is buried in the trenches at both ends sharing the same electrode, respectively.
4. The semiconductor memory device according to claim 3, wherein an SFET is formed. 7. The second gate electrode and a back word line connected to the second gate electrode are shared by two MISFETs adjacent in the bit line direction, and the side face of the second gate electrode faces majority carriers. 7. The semiconductor memory device according to claim 6, wherein a fixed potential maintained in an accumulation state is applied. 8. A step of forming a rectangular element formation region defined by an element isolation insulating film in a semiconductor substrate; and ion-implanting impurities into the semiconductor substrate to form a source diffusion layer crossing a bottom of the element formation region. Forming at least two trenches at a predetermined distance in the element formation region; forming a gate insulating film on a side surface of the element region sandwiched between the two trenches; And a step of forming a drain diffusion layer on the surface of the element region. 9. Two trenches located at both ends in the longitudinal direction are formed in the element formation region, and one MISFET having first and second gate electrodes embedded in these trenches is formed. 9. The method for manufacturing a semiconductor memory device according to claim 8, wherein: 10. In the element formation region, three trenches are formed at both ends and a central portion in a longitudinal direction thereof,
9. The semiconductor device according to claim 8, wherein two MISFETs are formed, sharing the second gate electrode embedded in the central trench and having the first gate electrodes embedded in the trenches at both ends. A method for manufacturing a memory device.