JP4104836B2 - Semiconductor memory device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device that dynamically stores data using a channel body of a MISFET as a storage node and a manufacturing method thereof.
[0002]
[Prior art]
In a conventional DRAM, a memory cell is composed of a MISFET and a capacitor. The miniaturization of DRAM is greatly advanced by adopting a trench capacitor structure or a stacked capacitor structure. Currently, the size (cell size) of a unit memory cell is reduced to an area of 2F × 4F = 8F ² where F is the minimum processing dimension. That is, when the minimum processing dimension F is reduced with generation and the cell size is generally αF ² , the coefficient α is also decreased with generation, and α = 8 is currently realized at F = 0.18 μm.
[0003]
In order to secure the same cell size or chip size trend as before, it is required to satisfy α <8 when F <0.18 μm, and α <6 when F <0.13 μm. How to form a cell size in a small area along with processing becomes a big problem. For this reason, various proposals have been made to make the memory cell of one transistor / one capacitor as large as 6F ² or 4F ² . However, there are technical difficulties such as having to make the transistor vertical, problems such as increased electrical interference between adjacent memory cells, and difficulties in manufacturing technology such as processing and film generation, and practical application is not easy. Absent.
[0004]
On the other hand, a semiconductor memory that forms a 1-bit memory cell using a channel body of one MISFET as a storage node without using a capacitor has been proposed in 1979 (PKChatterjee, et.al. "Circuit Optimization of the taper isolated dynamic gain RAM cell for VLSI memories," ISSCC Tech. Dig. Pp.22-23, Feb. 1979). The MISFET structure has a p-type channel body separated from the substrate by an n-type buried layer on a p-type substrate. The principle of the storage operation is to control the injection and emission of holes from the substrate to the channel body by controlling the barrier height with respect to the holes of the n-type buried layer by capacitive coupling from the gate electrode.
[0005]
That is, at the time of data writing, the potential of the n-type buried layer is lowered by capacitive coupling from the gate to inject holes from the substrate to the channel body. Therefore, the hole accumulation state and the hole emission state of the channel body are stored as binary data. In the data holding state, the potential of the n-type buried layer is raised by capacitive coupling from the gate so that holes in the channel body are not emitted.
[0006]
In this method, in order to control the potential of the n-type buried layer from the gate, the n-type buried layer must not be depleted, and the presence of electrons that are majority carriers is essential. Therefore, the n-type drain and source diffusion layers are short-circuited by the n-type buried layer. When the channel length is as large as several μm, the influence of the short-circuit resistance due to the n-type buried layer can be made relatively small compared to the resistance change due to the on / off of the channel. When applied to a MISFET having a sub-μm channel length, the short-circuit resistance between the source and drain due to the n-type buried layer cannot be ignored and the operation becomes impossible.
[0007]
[Problems to be solved by the invention]
Various other methods for forming a 1-bit memory cell with one MISFET have been proposed, but have problems such as complicated transistor structure and complicated control.
[0008]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of dynamic storage by a memory cell having a simple transistor structure and a manufacturing method thereof.
[0009]
[Means for Solving the Problems]
In the semiconductor memory device according to the present invention, a 1-bit memory cell is composed of one MISFET having a floating channel body, and the MISFET has a first data state in which the channel body is set to a first potential and a second data state. The second data state set at the potential is dynamically stored, and the MISFET is in contact with the first semiconductor layer of the first conductivity type serving as a channel body and the bottom surface of the first semiconductor layer. A second conductivity type second semiconductor layer depleted by a built-in potential, a first conductivity type third semiconductor layer in contact with the bottom surface of the second semiconductor layer, and a gate on the upper surface of the first semiconductor layer a gate electrode formed through an insulating film, the first semiconductor layer source and drain diffusion layer from the top being formed to a depth reaching the second semiconductor layer and Wherein the semiconductor layer immediately below the gate electrode is buried in a state surrounded by the insulating film, and having an auxiliary gate electrode upper end opposite to the first semiconductor layer through the insulating film.
[0010]
Specifically, in the present invention, the first data state is written by causing impact ionization in the vicinity of the drain junction by operating the MIS transistor in a pentode operation, and the second data state is the capacitance from the first gate. Writing is performed by applying a forward bias between the semiconductor layer to which a predetermined potential is applied by coupling and the drain. Therefore, data is written and read at the source of the MISFET with a fixed potential such as the ground potential.
Alternatively, a gate-induced drain leakage (GIDL) current induced by the gate can be used as a writing method of the first data state.
[0011]
According to the present invention, one memory cell is formed by a simple MISFET. The MISFET has a pnp (or npn) structure under a gate electrode, and has a channel body that floats when its intermediate layer is depleted by a built-in potential. The MISFET stores data according to the potential state of its channel body, but the data junction can use the reverse bias and forward bias of the drain junction with the source as a fixed potential regardless of carrier injection from the substrate. . Therefore, reading, rewriting, and refreshing can be controlled only by controlling the bit line connected to the drain and the word line connected to the gate. Unlike the conventional method using carrier injection and emission from the substrate to the channel body, data can be rewritten in arbitrary bit units.
[0012]
In the present invention, preferably, the auxiliary gate electrode is buried between the source and drain diffusion layers so that the pn junctions of the first semiconductor layer and the second semiconductor layer remain on both sides. The lower end of the auxiliary gate electrode may be located in the second semiconductor layer or may have a depth reaching the third semiconductor layer.
[0014]
The present invention is also a method of manufacturing a semiconductor memory device as described above, the step of forming a trench in a semiconductor substrate of the first conductivity type, and after forming an insulating film on the inner wall of the trench, A step of embedding the auxiliary gate electrode to a depth, and after forming a first gate insulating film on the upper surface of the auxiliary gate electrode, a heat treatment in hydrogen gas is performed with the sidewalls of the trench exposed, and A step of covering an upper portion with the flow of the semiconductor substrate material, a step of introducing an impurity into a surface portion of the semiconductor substrate to form a first semiconductor layer of a first conductivity type serving as a channel body, by ion implantation of an impurity immediately below the first semiconductor layer, forming a second semiconductor layer of a second conductivity type depleted by a built-in potential, the trench A step of forming a gate electrode on the surface of the first semiconductor layer via a second gate insulating film; and ion implantation of impurities into the semiconductor substrate to a depth reaching the second semiconductor layer. And a step of forming a two-conductivity type source and drain diffusion layer.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[Embodiment 1]
FIG. 1 shows the structure of a DRAM cell according to a basic embodiment. The memory cell MC is composed of an n-channel MISFET. The p-type silicon substrate 10 has a structure in which an n-type layer 11 and a p-type layer 12 are laminated. A gate electrode 14 is formed on the p-type layer 12 as a channel body via a gate insulating film 13. ing. N-type drain and source diffusion layers 15 and 16 are formed in self-alignment with the gate electrode 14.
[0016]
In the pnp structure constituted by the p-type layer 12, the n-type layer 11, and the p-type substrate 10, the impurity concentration and thickness are adjusted so that the n-type layer 11 is completely depleted by the built-in potential. Specifically, in order to form this structure only by ion implantation, the p-type silicon substrate 10 is required to have a relatively low concentration, and a p-type impurity such as boron is ion-implanted into the surface portion to form a channel body. A p-type layer 12 having an appropriate concentration is obtained to obtain a suitable threshold value. Further, an n-type impurity such as arsenic is ion-implanted immediately below the p-type layer 12 to form the n-type layer 11. It does not matter before and after these ion implantation steps.
[0017]
Then, the n-type layer 11 is completely depleted by the built-in potential by optimizing the impurity concentration of the p-type layer 12 and the n-type layer 11 and the thickness of the n-type layer 11. The drain and source diffusion layers 15 and 16 are formed to a depth reaching the n-type layer 11 from the surface. At this time, a portion of the n-type layer 11 under the source / drain diffusion layers 15 and 16 forms a pn junction only with the substrate 10, and this portion is also built-in between the substrate 10. It is preferable to deplete with potential. As for the channel width direction (that is, the direction perpendicular to the drawing sheet), the p-type layer 12 includes the depleted n-type layer 12, the drain, the source, and the element isolation insulating film. The diffusion layers 15 and 16 and the element isolation insulating film are in a floating state electrically isolated from others.
[0018]
When the memory cells MC are arranged in a matrix, the gate electrode 14 is connected to the word line WL, the source diffusion layer 16 is connected to the fixed potential line SL (ground potential line), and the drain diffusion layer 15 is connected to the bit line BL. The An equivalent circuit of the unit cell of the cell array configured in this way is as shown in FIG.
[0019]
The operation principle of the DRAM cell composed of this n-channel type MISFET utilizes the potential control of the floating channel body (p-type layer 12 separated from others). That is, when the MISFET is operated in the pentode region and a large current flows from the drain diffusion layer 15 to cause impact ionization in the vicinity of the drain junction, the first potential state in which the channel body holds holes that are majority carriers. Can be set to This state is, for example, data “1”. The second potential state in which the p-type layer 12 is set to a lower potential is obtained by forward biasing the pn junction between the drain diffusion layer 15 and the p-type layer 12 and releasing the holes of the p-type layer 12. Set to “0”. During this time, the source diffusion layer 16 is held at a fixed potential, for example, a ground potential.
[0020]
Data “0” and “1” are stored as a difference in channel body potential, and hence as a difference in threshold voltage of the MISFET. That is, the threshold voltage Vth1 in the data “1” state in which the body potential is high due to hole accumulation is lower than the threshold voltage Vth0 in the data “0” state. In order to maintain the “1” data state in which holes that are majority carriers are accumulated in the body, a negative bias voltage is applied to the word line. This data holding state does not change even if a read operation is performed unless a reverse data write operation (erase) is performed. That is, unlike a one-transistor / one-capacitor DRAM that uses capacitor charge storage, non-destructive readout is possible.
[0021]
There are several possible methods for reading data. The relationship between the word line potential VWL and the channel body potential VB is as shown in FIG. 3 in relation to the data “0” and “1”. Therefore, for example, in the first method of reading data, a read potential that is intermediate between the threshold voltages Vth0 and Vth1 of data “0” and “1” is applied to the word line WL, and a memory cell of “0” data is used. The fact that no current flows and the current flows in the memory cell of “1” data is utilized. Specifically, for example, the bit line BL is precharged to a predetermined potential VBL, and then the word line WL is driven. Thereby, in the case of “0” data, the bit line precharge potential VBL does not change, and in the case of “1” data, the precharge potential VBL decreases.
[0022]
The second read method utilizes the fact that the rising speed of the bit line potential varies depending on the conductivity of “0” and “1” by supplying current to the bit line BL after the word line WL is raised. To do. In brief, the bit line BL is precharged to 0V, the word line WL is raised, and the bit line current is supplied. At this time, it is possible to discriminate data by detecting the difference in potential rise of the bit line using the dummy cell.
[0023]
In the present invention, in order to selectively write "0" data, that is, holes are emitted only from the body of the memory cell selected by the potential of the word line WL and bit line BL selected in the memory cell array. In this case, capacitive coupling between the word line WL and the body becomes essential. In the state where holes are accumulated in the body with data “1”, the word line is sufficiently biased in the negative direction, and the gate-substrate capacitance of the memory cell becomes the gate oxide film capacitance (ie, the surface has a depletion layer). It is necessary to hold it in a state where it is not formed.
[0024]
As described above, according to this embodiment. A DRAM cell is constituted by a MISFET having a simple structure. The buried n-type layer 11 does not need to be controlled in potential for carrier injection from the substrate as in the method described in the prior art, and is in a depleted state with a built-in potential. Therefore, even in a short channel MISFET, the short-circuit resistance between the source and the drain due to the n-type layer 11 does not become a problem and can be miniaturized.
Further, if the n-type layer 11 portion immediately below the drain and source diffusion layers 15 and 16 is also depleted, the junction capacitance of the drain and source diffusion layers 15 and 16 is reduced, and is the same as when using an SOI substrate. The characteristics are improved.
[0025]
[Embodiment 2]
FIG. 4 shows a cross-sectional structure of two bits aligned in the bit line direction for the cell array of a more specific embodiment. However, the same reference numerals as those in FIG. 1 are assigned to portions corresponding to those in FIG. In the p-type silicon substrate 10, for example, a range of 2 bits (two MISFETs) is partitioned as an island-shaped element formation region by the element isolation insulating film 21. The n-type layer 11 is formed by ion implantation in the substrate 10 as described in the first embodiment, and the p-type layer 12 serving as a channel body is formed thereon. The conditions for depleting n-type layer 11 are the same as in the first embodiment.
[0026]
The gate electrode 14 is continuously patterned in a direction perpendicular to the paper surface with the upper surface and side surfaces covered with the silicon nitride film 22 to form word lines. The drain diffusion layer 15 and the source diffusion layer 16 are high-concentration (n ⁺ ) diffusion layers 15 a and 16 a having a depth reaching the n-type layer 11, and an extension region having a lower concentration and shallower (not reaching the n-type layer 11). 15b and 16b. Specifically, the extension regions 15 b and 16 b are formed by ion implantation before forming the silicon nitride film on the side surface of the gate electrode 14, and the high concentration diffusion layers 15 a and 16 a are formed on the side surface of the gate electrode 14. Is formed by performing ion implantation.
[0027]
In this example, the source diffusion layer 16 is shared by two MISFETs. For example, the source diffusion layer 16 may be continuously formed in a direction perpendicular to the drawing sheet as a fixed potential line, or may be separately connected to a fixed potential line provided above. . The substrate on which the element is formed is covered with an interlayer insulating film 23, and a bit line 24 is disposed thereon. The bit line 24 is connected to the drain diffusion layer 15 through a contact hole opened in the interlayer insulating film 23.
[0028]
[Embodiment 3]
In the DRAM cell described so far, an important point is how much the threshold voltage difference between the data “0” and “1” can be increased on the principle of operation. As is clear from the above operating principle, the data writing and holding characteristics are determined by controlling the body potential by capacitive coupling from the gate. However, the threshold voltage works with a square root with respect to the body potential. It is not easy to realize a large threshold voltage difference between “0” and “1” data. In addition, in the above-described write operation, the memory cell in which “0” is written performs a triode operation. When the channel is formed, the gate electrode and the body are not capacitively coupled, and the body potential cannot be controlled.
[0029]
Therefore, in the present invention, preferably, an auxiliary gate electrode for controlling the body potential by capacitive coupling to the channel body of the MISFET is provided separately from the main gate electrode used for channel formation. 5 and 6 show the cell structure of such an embodiment corresponding to FIG.
[0030]
As shown in the figure, an auxiliary gate electrode 31 is buried in the p-type layer 12 immediately below the gate electrode 14. The periphery of the auxiliary gate electrode 31 is surrounded by an insulating film 32. The width of the auxiliary gate electrode 31 (the width in the bit line direction) is smaller than that of the main gate electrode 14, and the pn junction between the p-type layer 12 and the n-type layer 11 remains on both sides thereof. As a result, the n-type layer 11 is depleted by the built-in potential between the n-type layer 11 and the p-type layer 12.
[0031]
The upper end of the auxiliary gate electrode 31 faces the p-type layer 12 through the insulating film 32, and the potential of the p-type layer 12 can be controlled by capacitive coupling. The portion of the insulating film 32 (gate insulating film) where the auxiliary gate electrode 31 faces the p-type layer 12 may have the same thickness as the gate insulating film 13 on the main gate electrode 14 side, but the auxiliary gate electrode of the p-type layer 12 The thickness of the insulating film 32 on the 31 side is determined so as to optimize the magnitude of capacitive coupling to the p-type layer 12. Therefore, for example, it is made thicker than the gate insulating film 13 on the main gate electrode 14 side.
[0032]
In the case of FIG. 5, the bottom surface of the auxiliary gate electrode 31 has a depth reaching the p-type substrate 10, and in the case of FIG. 6, the bottom surface of the auxiliary gate electrode 31 is located in the n-type layer 11. With the structure shown in FIG. 5, the auxiliary gate electrode 31 can be operated without degrading the isolation characteristics of the p-type layer 12 by the n-type buried layer 11. In the structure shown in FIG. 6, the n-type buried layer 11 is divided by the auxiliary gate electrode 31, so that the drain / source isolation characteristics are improved.
[0033]
For example, the auxiliary gate electrode 31 can be continuously formed as an auxiliary word line parallel to the word line formed by the main gate electrode 14. For example, the auxiliary gate electrode 31 is driven in synchronization with the gate electrode 14. As a result, reliable writing is possible and the threshold voltage difference between “0” and “1” data can be increased. Alternatively, the auxiliary gate electrode 31 is set to a fixed potential lower than the source potential, for example, and the auxiliary gate electrode 31 side of the channel body is maintained in the majority carrier accumulation state, thereby similarly causing a difference in data threshold voltage between “0” and “1”. Can be increased.
[0034]
More specifically, when the word line WL is held at a negative potential and “1” data is held, a negative potential is also applied to the auxiliary word line that makes a pair, so that the holding state of “1” data is good. Can be kept in. When data writing is performed by raising the potential of the word line WL, the channel body potential can be raised by capacitive coupling by raising the auxiliary word line, thereby enabling reliable data writing. In the case of “0” data writing, even if a channel is formed on the word line WL side, the channel body potential can be increased by the auxiliary word line, so that reliable “0” data writing can be performed. As described above, data “0” and “1” having a large threshold voltage difference can be stored.
[0035]
In addition, a negative potential is applied to the unselected word line WL to hold data. At this time, the channel word potential is controlled to be low by setting the paired auxiliary word lines to a negative potential. When “0” data is written in another memory cell along the line, data destruction in a non-selected cell that holds “1” data is reliably prevented.
[0036]
[Embodiment 4]
Next, taking the cell structure of FIG. 5 as an example, a specific manufacturing process will be described with reference to FIGS. 7A to 7F. As shown in FIG. 7A, a mask (not shown) such as a silicon oxide film pad is formed on the p-type silicon substrate 10, and the p-type silicon substrate 10 is etched by RIE to form a trench 41 for burying the auxiliary gate. Form. Subsequently, after an insulating film 32a is formed on the sidewall of the trench 41, polycrystalline silicon is deposited and etched back to bury the auxiliary gate electrode 31 partway through the trench. Instead of polycrystalline silicon, other conductor layers such as a refractory metal can be used.
[0037]
Thereafter, an insulating film 32b to be a gate insulating film is formed on the upper surface of the buried auxiliary gate electrode 31. The insulating film 32a is formed thicker than the surrounding insulating film 32a by, for example, low-temperature wet oxidation or HDP-CVD. Then, after removing the thin insulating film on the trench sidewall above the auxiliary gate electrode 31, heat treatment is performed in a hydrogen atmosphere at 800 ° C. to 1000 ° C. As a result, silicon flows from the upper side wall of the trench 41, and as shown in FIG. 7D, the upper portion of the trench 41 is covered with the same p-type single crystal silicon layer 42 as that of the substrate 10, and the whole is flat. Obtainable.
[0038]
Such a technique for covering the upper part of the groove by hydrogen heat treatment has been previously proposed by the present applicant as a technique for confining a cavity inside a silicon substrate (Japanese Patent Laid-Open No. 2000-12858). However, the same structure can be obtained by closing the upper portion of the trench 41 by crystal growth in the lateral direction from the side wall of the trench 41 using an epitaxial growth technique.
[0039]
Thereafter, an element isolation insulating film (not shown) is formed by STI (Shallow Trench Isolation) technology, and then arsenic (or phosphorus) is ion-implanted as shown in FIG. Layer 11 is formed embedded. The upper p-type layer 12 separated from the substrate 10 by the n-type layer 11 (particularly, the portion of the p-type layer 42 covering the upper portion of the trench 41) is used as a channel body, but the n-type layer 11 is depleted with a built-in potential and In order to obtain necessary threshold characteristics, boron ions are implanted into the p-type layer 12 to adjust the impurity concentration. Thereby, the impurity concentration distribution is as shown in FIG. In order to form the n-type layer 11 with a relatively low dose, it is preferable that the p-type silicon substrate 10 has a low concentration. Then, boron ions are implanted into the upper portion of the n-type layer 11 so that the channel body has a required p-type concentration, whereby the n-type layer 10 can be depleted with a built-in potential.
[0040]
Thereafter, as shown in FIG. 7F, a MISFET is formed. Specifically, the gate insulating film 13 is formed, the gate electrode material and the silicon nitride film 22a are stacked thereon, and the stacked film is patterned to form the gate electrode. In this state, ion implantation is performed to form drain and source n ⁺ -type layers 15a and 16a. Further, a silicon nitride film 22b covering the side wall of the gate electrode 14 is formed, and ion implantation is performed in this state to form shallow extended regions 15b and 16b. Thereafter, although not shown in the process diagram, an interlayer insulating film is deposited, contact holes are formed, and bit lines are formed.
[0041]
In the above, the manufacturing process of the DRAM cell provided with the buried auxiliary gate electrode 31 has been described. However, the same structure is applied to the cell structure without the auxiliary gate electrode shown in FIG. A process can be applied.
[0042]
[Embodiment 5]
4 to 6 show a structure in which elements are separated in units of 2 bits in the bit line direction. However, if not only the source diffusion layer but also the drain diffusion layer is shared by adjacent cells, the bit line direction is improved. No element separation is required. In this case, the unit cell area of the cell array can be made smaller.
[0043]
FIG. 9 is a layout of the cell array of such an embodiment, and FIGS. 10A and 10B are cross-sectional views taken along lines AA ′ and BB ′ of FIG. The MISFET structure is basically the same as the structure of FIG. 4 without the auxiliary gate electrode. However, the drain and source diffusion layers 15 and 16 are single layers. As shown in FIG. 9, the element isolation insulating film 21 is embedded in a matrix array with a rectangular pattern having a size of 1F × 3F, where F is the minimum processing dimension. Then, the gate electrode 14 is patterned so as to continue across both ends of each rectangular element isolation insulating film, thereby forming a word line WL having a line / space of 1F / 1F.
[0044]
If the drain and source diffusion layers 15 and 16 are formed by ion implantation after forming the word line WL in this way, the source diffusion layer 16 becomes a common source line SL continuously in parallel with the word line WL, and a bit. In the line direction, it is shared by adjacent cells. The drain diffusion layer 15 is separated from adjacent cells by the element isolation insulating film 21 in the word line WL direction, and is formed so as to be shared by the adjacent cells in the bit line BL direction. In the figure, the bit line 24 is also shown in the case where the line / space is formed with 1F / 1F. As shown in FIG. 10A, a contact plug 51 is embedded in the bit line contact hole.
[0045]
With such a cell array configuration, as indicated by the broken line in FIG. 9, the unit cell area is 4F ² , and a high-density DRAM cell array can be obtained. An equivalent circuit of the cell array is as shown in FIG.
[0046]
The present invention is not limited to the above embodiment. For example, FIG. 12 shows an example in which the wiring 25 for commonly connecting the source diffusion layers 16 is formed based on the structure of FIG. A similar structure can be applied to the cells shown in FIGS.
In the above embodiment, an n-channel MISFET is used, but a p-channel MISFET can also be used. In the embodiment, as a method for obtaining a floating channel body, a pnp structure is formed by ion implantation. However, a similar structure can be obtained by using epitaxial growth.
[0047]
【The invention's effect】
As described above, according to the present invention, it is possible to obtain a highly integrated semiconductor memory device in which a MISFET having a simple structure is used as a memory cell and data is dynamically stored according to the potential state of the channel body. it can.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a structure of a DRAM cell according to an embodiment of the present invention.
FIG. 2 is an equivalent circuit of the DRAM cell.
FIG. 3 is a characteristic diagram for explaining a memory operation of the DRAM cell;
FIG. 4 is a cross-sectional view showing a structure of a DRAM cell according to another embodiment.
FIG. 5 is a cross-sectional view showing a structure of a DRAM cell according to another embodiment.
FIG. 6 is a cross-sectional view showing a structure of a DRAM cell according to another embodiment.
FIG. 7A is a cross-sectional view showing a step of forming an auxiliary gate electrode embedding trench in the manufacturing process of the embodiment;
FIG. 7B is a cross-sectional view showing an auxiliary gate electrode embedding step in the manufacturing step.
FIG. 7C is a cross-sectional view showing a gate insulating film forming step of the auxiliary gate in the manufacturing step.
FIG. 7D is a cross-sectional view showing a trench filling step in the same manufacturing step.
FIG. 7E is a cross-sectional view showing an n-type layer ion implantation step in the same manufacturing step.
FIG. 7F is a cross-sectional view showing a MISFET formation step in the same manufacturing step.
FIG. 8 is a diagram showing an impurity concentration distribution in a channel body region in the same manufacturing process.
FIG. 9 is a diagram showing a layout of a DRAM cell array according to another embodiment.
10A is a cross-sectional view taken along line AA ′ of FIG. 9. FIG.
10B is a cross-sectional view taken along the line BB ′ of FIG.
FIG. 11 is an equivalent circuit of the DRAM cell array.
FIG. 12 is a diagram showing a structure of a DRAM cell according to another embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... p-type silicon substrate, 11 ... n-type layer, 12 ... p-type layer (channel body), 13 ... Gate insulating film, 14 ... Gate electrode, 15 (15a, 15b) ... Drain diffused layer, 16 (16a, 16b) ) ... Source diffusion layer, 21 ... Element isolation insulating film, 22 ... Silicon nitride film, 23 ... Interlayer insulating film, 24 ... Bit line, 31 ... Auxiliary gate electrode, 32 ... Insulating film.

Claims (6)

A 1-bit memory cell is composed of one MISFET having a floating channel body, and the MISFET has a first data state in which the channel body is set to a first potential and a second data state in which the channel body is set to a second potential. Is dynamically memorized,
The MISFET includes a first semiconductor layer of a first conductivity type serving as a channel body;
A second semiconductor layer of a second conductivity type in contact with the bottom surface of the first semiconductor layer and depleted by a built-in potential;
A third semiconductor layer of the first conductivity type in contact with the bottom surface of the second semiconductor layer;
A gate electrode formed on the upper surface of the first semiconductor layer via a gate insulating film;
A source and drain diffusion layer formed to a depth reaching the second semiconductor layer from the upper surface of the first semiconductor layer ;
A semiconductor memory having an auxiliary gate electrode buried in a semiconductor layer immediately below the gate electrode in a state surrounded by an insulating film and having an upper end opposed to the first semiconductor layer through the insulating film apparatus. The first data state is written by causing impact ionization in the vicinity of the drain junction by causing the MISFET to operate as a pentode.
The second data state is written by applying a forward bias between a channel body to which a predetermined potential is applied by capacitive coupling from the first gate electrode and a drain diffusion layer. The semiconductor memory device described. The auxiliary gate electrode, between the source and drain diffusion layers, a semiconductor according to claim 1, wherein the pn junction of the first semiconductor layer and the second semiconductor layer, characterized in that the embedded to remain on both sides Memory device. The auxiliary gate electrode, a semiconductor memory device according to claim 1, wherein the lower end is embedded so as to be positioned in the second semiconductor layer. The auxiliary gate electrode, a semiconductor memory device according to claim 1, wherein the lower end is embedded to reach the third semiconductor layer. A 1-bit memory cell is composed of one MISFET having a floating channel body, and the MISFET has a first data state in which the channel body is set to a first potential and a second data state in which the channel body is set to a second potential. A method of manufacturing a semiconductor memory device that dynamically stores
Forming a trench in a first conductivity type semiconductor substrate;
After forming an insulating film on the inner wall of the trench, burying an auxiliary gate electrode to a midway depth in the trench;
After forming the first gate insulating film on the upper surface of the auxiliary gate electrode, heat treatment in hydrogen gas is performed with the sidewalls of the trench exposed, and the upper portion of the trench is covered with the flow of the semiconductor substrate material. Process,
Introducing impurities into a surface portion of the semiconductor substrate to form a first semiconductor layer of a first conductivity type serving as a channel body;
Performing ion implantation of impurities immediately below the first semiconductor layer of the semiconductor substrate to form a second semiconductor layer of a second conductivity type that is depleted by a built-in potential;
Forming a gate electrode on the surface of the first semiconductor layer covering the trench via a second gate insulating film;
Forming a second conductivity type source and drain diffusion layer at a depth reaching the second semiconductor layer by implanting impurities into the semiconductor substrate. Method.

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