JP4282401B2 - Flash memory control circuit, and memory controller and flash memory system provided with the control circuit - Google Patents

Description

  The present invention relates to a flash memory control circuit, a memory controller including the control circuit, and a flash memory system, and more particularly to a flash memory control circuit having a USB interface or similar interface, and the control circuit. The present invention relates to a memory controller and a flash memory system.

  In recent years, a flash memory is often used as a semiconductor memory used in a memory system such as a memory card or a silicon disk. This flash memory is a kind of non-volatile memory, and is required to retain data regardless of whether power is turned on.

  By the way, the NAND flash memory that is often used in the above-described devices is used when a memory cell is changed from an erased state (logical value “1”) to a written state (logical value “0”). Can be performed in units of memory cells. However, when a memory cell is changed from a written state (logical value “0”) to an erased state (logical value “1”), it must be performed in memory cells. This can only be done with a predetermined erase unit (block) consisting of a plurality of memory cells. Such a batch erase operation is generally called “block erase”.

  A block which is an erasing processing unit is composed of pages which are processing units for reading and writing (for example, one block is composed of 32 pages). This page is usually composed of a 512-byte data area, and read and write processing for the page is performed in units of 512 bytes. Therefore, such read and write processing for the flash memory is performed via a 512-byte buffer circuit (for example, an SRAM having a 512-byte data area) (hereinafter referred to as flash memory). A buffer circuit used for reading and writing is called a page buffer.) In other words, in a memory system having flash memory (hereinafter, a memory system having flash memory is referred to as a flash memory system), data written from the host system side is temporarily held in the page buffer and then held in the page buffer. The written data is written to the flash memory. On the other hand, data read from the flash memory is once held in the page buffer, and the data held in the page buffer is transferred to the host system side.

  In recent years, a device in which the above memory system is connected to a USB (Universal Serial Bus) interface (for example, a device compliant with USB Mass Storage Class) is also provided. In a device connected to the USB, data transmitted / received via the USB interface is once held in a buffer called an endpoint. That is, when data transmitted from the host system side is received via the USB interface, the received data is held at the reception endpoint, and when data is transmitted to the host system side via the USB interface, Data held in the transmission endpoint is transmitted to the host system side.

  Therefore, in a flash memory system having a USB interface, data written to the flash memory from the host system side is transferred from the receiving endpoint to the page buffer, and the data transferred to the page buffer is written to the flash memory. . The data read from the flash memory to the host system side is transferred from the page buffer to the transmission endpoint, and the data transferred to the transmission endpoint is transmitted to the host system side via the USB interface.

  In the flash memory system having the USB interface as described above, a buffer circuit (end point) for the USB interface and a buffer circuit (page buffer) used for reading and writing to the flash memory are provided. There was a problem that the circuit scale became large. In addition, when data read / write processing is performed from the host system side, transfer processing between the endpoint and the page buffer occurs, so read / write processing efficiency is not good.

  Accordingly, an object of the present invention is to provide a flash memory control circuit that suppresses an increase in circuit scale and a reduction in processing efficiency due to the provision of a USB interface, and a memory controller and a flash memory system including the control circuit. To do.

An object of the present invention is to transmit / receive data via a USB interface;
Received data holding means for holding data received via the USB interface;
Write processing control means for writing data held in the received data holding means to a flash memory;
Transmission data holding means for holding data to be transmitted via the USB interface;
Read processing control means for reading data stored in the flash memory to the transmission data holding means,
Control of the flash memory, wherein the write processing control means starts a write process to the flash memory after data for one page of the flash memory is held in the received data holding means Achieved by the circuit. Further, this can be achieved by a memory controller having the flash memory control circuit or a flash memory system having the flash memory control circuit and the flash memory.

An object of the present invention is to transmit / receive data via a USB interface;
Received data holding means for holding data received via the USB interface;
Write processing control means for writing data held in the received data holding means to a flash memory;
Transmission data holding means for holding data to be transmitted via the USB interface;
Read processing control means for reading data stored in the flash memory to the transmission data holding means,
Control of the flash memory, wherein the transmission / reception means starts transmission after data for one page of the flash memory is read to the transmission data holding means by the read processing control means Achieved by the circuit. Further, this can be achieved by a memory controller having the flash memory control circuit or a flash memory system having the flash memory control circuit and the flash memory.

An object of the present invention is to transmit / receive data via a USB interface;
Received data holding means for holding data received via the USB interface;
Write processing control means for writing data held in the received data holding means to a flash memory;
Transmission data holding means for holding data to be transmitted via the USB interface;
Read processing control means for reading data stored in the flash memory to the transmission data holding means,
After the data for one page of the flash memory is held in the received data holding means, the write processing control means starts the writing process to the flash memory,
Control of the flash memory, wherein the transmission / reception means starts transmission after data for one page of the flash memory is read to the transmission data holding means by the read processing control means Achieved by the circuit. Further, this can be achieved by a memory controller having the flash memory control circuit or a flash memory system having the flash memory control circuit and the flash memory.

Further, according to the present invention, when the USB interface is operating in the high speed mode, the write processing control means sends data to the flash memory after the received data holding means holds data for one packet. When the writing process is started and the USB interface is operating in the full speed mode, the writing process control unit performs the writing process to the flash memory after the received data holding unit holds data for 8 packets. It is preferably configured to start.

  According to the present invention, it is preferable that the capacity of the received data holding means is the same as the data capacity of one page of the flash memory.

  According to the present invention, it is preferable that the capacity of the received data holding means is 512 bytes.

According to the present invention, when the USB interface is operating in the high speed mode, the data held in the transmission data holding means is transmitted in a packet including 512-byte data,
When the USB interface is operating in the full speed mode, the data held in the transmission data holding unit may be divided into packets including 64-byte data and transmitted. preferable.

  According to the present invention, it is preferable that the capacity of the transmission data holding means is the same as the data capacity of one page of the flash memory.

  According to the present invention, it is preferable that the capacity of the transmission data holding means is 512 bytes.

  In a flash memory control circuit according to the present invention, and a memory controller and flash memory system including the control circuit, a buffer circuit (endpoint) for a USB interface is used as a buffer for reading and writing to the flash memory. Since it can be used as a circuit (page buffer), an increase in circuit scale can be minimized.

  Furthermore, the data transfer between the buffer circuit and the flash memory is based on the page size of the flash memory (data capacity for one page) regardless of the size of the packet transmitted / received via the USB interface (data capacity included in the packet). Since processing is performed, a decrease in processing efficiency due to a difference in packet size (difference in transmission speed) can be suppressed.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention, and shows a flash memory system 1 including a flash memory 9 and a memory controller 2.
[Description of flash memory]
The flash memory 9 shown in FIG. 1 is a nonvolatile memory that performs reading or writing in units of pages and erasing in units of blocks. A state where data is written in a memory cell constituting the flash memory 9 and a state where data is not written will be described with reference to FIGS.

  FIG. 2 is a cross-sectional view schematically showing the structure of the memory cell 16 constituting the flash memory. As shown in the figure, the memory cell 16 includes an N-type source diffusion region 18 and a drain diffusion region 19 formed in the P-type semiconductor substrate 17, and a P between the source diffusion region 18 and the drain diffusion region 19. Tunnel oxide film 20 formed to cover type semiconductor substrate 17, floating gate electrode 21 formed on tunnel oxide film 20, insulating film 22 formed on floating gate electrode 21, and insulating film 22 The control gate electrode 23 is formed on the top. A plurality of memory cells 16 having such a configuration are connected in series in the flash memory.

  The memory cell 16 has either an “erased state (a state where no electrons are accumulated)” or a “written state (a state where electrons are accumulated)” depending on whether electrons are injected into the floating gate electrode 21 or not. Is shown. Here, one memory cell 16 corresponds to 1-bit data, the “erased state” of the memory cell 16 corresponds to data of “1” of the logical value, and the “written state” of the memory cell 16 corresponds to the logical value. Corresponds to “0” data.

  In the “erased state”, since electrons are not accumulated in the floating gate electrode 21, when no read voltage is applied to the control gate electrode 23, a P-type region between the source diffusion region 18 and the drain diffusion region 19 is used. A channel is not formed on the surface of the semiconductor substrate 17, and the source diffusion region 18 and the drain diffusion region 19 are electrically insulated. On the other hand, when a read voltage is applied to the control gate electrode 23, a channel (not shown) is formed on the surface of the P-type semiconductor substrate 17 between the source diffusion region 18 and the drain diffusion region 19. And the drain diffusion region 19 are electrically connected by this channel.

  That is, in the “erased state”, when no read voltage is applied to the control gate electrode 23, the source diffusion region 18 and the drain diffusion region 19 are electrically insulated, and the read voltage is applied to the control gate electrode 23. In this state, the source diffusion region 18 and the drain diffusion region 19 are electrically connected.

  FIG. 3 is a cross-sectional view schematically showing the memory cell 16 in the “written state”. As shown in the figure, the “written state” refers to a state in which electrons are accumulated in the floating gate electrode 21. Since the floating gate electrode 21 is sandwiched between the tunnel oxide film 20 and the insulating film 22, the electrons once injected into the floating gate electrode 21 stay in the floating gate electrode 21 for a very long time. In this “write state”, since electrons are accumulated in the floating gate electrode 21, the source diffusion region 18, the drain diffusion region 19, and the like regardless of whether or not the read voltage is applied to the control gate electrode 23. A channel 24 is formed on the surface of the P-type semiconductor substrate 17 between. Therefore, in the “write state”, the source diffusion region 18 and the drain diffusion region 19 are always electrically connected by the channel 24 regardless of whether or not the read voltage is applied to the control gate electrode 23. Become.

  Whether the memory cell 16 is in the erased state or the written state can be read as follows. A plurality of memory cells 16 are connected in series in the flash memory. A low level voltage is applied to the memory cell 16 selected in the series body, and a high level voltage is applied to the control gate electrode 23 of the other memory cells 16. In this state, it is detected whether or not the serial body of the memory cells 16 is in a conductive state. As a result, if the serial body is in a conductive state, it is determined that the selected memory cell 16 is in a written state, and if it is in an isolated state, it is determined that the selected flash memory cell 16 is in an erased state. The In this way, it is possible to read out whether the data held in any memory cell 16 included in the serial body is “0” or “1”.

  When the memory cell 16 in the erased state is changed to the written state, a high voltage is applied so that the control gate electrode 23 is on the high potential side, and electrons are injected into the floating gate electrode 21 through the tunnel oxide film 20. To do. At this time, an FN (Fowler-Nordheim) tunnel current flows and electrons are injected into the floating gate electrode 21. On the other hand, when the flash memory cell 16 in the written state is changed to the erased state, a high voltage that causes the control gate electrode 23 to be on the low potential side is applied and accumulated in the floating gate electrode 21 via the tunnel oxide film 20. Discharge electrons.

  Next, the memory structure of the flash memory 9 shown in FIG. 1 will be described. FIG. 4 schematically shows a memory structure of the flash memory. As shown in FIG. 4, the flash memory includes “pages” that are processing units for reading and writing data and “blocks” that are data erasing units.

  The “page” is composed of a data area 25 of 512 bytes and a redundant area 26 of 16 bytes. The data area 25 is an area for storing user data supplied from the host system side, and the redundant area 26 is an area for storing additional information such as an error correction code. The error correction code is additional information for correcting an error included in the data stored in the corresponding data area 25. If the error included in the data stored in the data area 25 is equal to or less than a predetermined number, It is used to correct this and obtain correct data.

  The redundant area 26 stores “corresponding logical block address” in addition to the error correction code. The “corresponding logical block address” indicates which logical block address the block corresponds to when data is stored in the block. If no data is stored in the block, the “corresponding logical block address” is also not stored, so that the block is an erased block depending on whether the “corresponding logical block address” is stored. It can be determined whether or not. That is, if the “corresponding logical block address” is not stored, it is determined that the block is an erased block.

  The “block” is composed of 32 “pages”. Here, since the flash memory cannot overwrite data, even if only the data of one “page” is rewritten, the data of other “pages” of the “block” that includes the “page” is also included. , You must rewrite to the erased "block".

  In addition, when data is rewritten as described above, since the data after rewriting is written in a “block” different from the “block” before rewriting, a block address based on the host address given by the host system (hereinafter referred to as “host”). A block address based on the address is referred to as a logical block address.) And a block address in the flash memory corresponding to the logical block address (hereinafter, the block address in the flash memory is referred to as a physical block address). The relationship changes dynamically every time data is rewritten.

For this reason, an address conversion table in which the correspondence between the logical block address and the physical block address is written is required. This “address conversion table” is a table showing a correspondence relationship between “logical block address” and “physical block address”, and every time the data written in the flash memory is rewritten for the reasons described above. , The correspondence of the part related to the rewriting is updated.
[Description of memory controller]
The memory controller 2 in FIG. 1 includes a USB interface unit 3, an end point control unit 4, a control end point 5, a reception end point 6, a transmission end point 7, and a flash memory control unit 8. Is done. The memory controller 2 constituted by these circuits is integrated on one semiconductor chip.

  Here, the USB interface unit 3 converts the serial signal data transmitted from the host system 10 side into a parallel signal, passes it to the end point control unit 4 side, and receives the parallel signal received from the end point control unit 4. This is a circuit that converts it into a serial signal and transmits it to the host system 10 side.

  The endpoint control unit 4 is a circuit that controls transmission / reception of data held in the control endpoint 5, the reception endpoint 6, and the transmission endpoint 7. The endpoint control unit 4 includes an interface circuit with the USB interface unit 3 and the flash memory control unit 8, and exchanges data and information with the USB interface unit 3 and the flash memory control unit 8 via the interface circuit. Is done.

  The control end point 5 is a buffer circuit that holds initial setting data and the like at the time of activation, and the reception end point 6 is a buffer circuit that holds reception data transmitted from the host system 10 side. The trusted endpoint 7 is a buffer circuit that holds transmission data to be transmitted to the host system 10 side.

The flash memory control unit 8 is composed of the following circuits.
(1) A circuit for controlling the operation of each circuit constituting the flash memory control unit 8.
(2) A register in which information necessary for executing an internal command (an internal command given to the flash memory 9) is set, and a circuit for setting information in the register.
(3) A work area (consisting of a plurality of SRAM cells) in which data necessary for controlling the flash memory 9 is temporarily stored.
(4) A circuit that exchanges data, address information, status information, and internal command information with the flash memory 9.
(5) A circuit for generating an error correction code to be added to data to be written in the flash memory 9 and detecting and correcting an error contained in the read data based on the error correction code added to the read data .
(6) A circuit that exchanges information and data with the endpoint control unit 4, the reception endpoint 6, and the transmission endpoint 7.
[Description of writing to flash memory]
Hereinafter, a process of writing data to the flash memory based on a request from the host system will be described with reference to the drawings. Data transmission via the USB interface includes a high speed mode and a full speed mode. The maximum packet size in the high speed mode is 512 bytes, and the maximum packet size in the full speed mode is 64 bytes. Therefore, when the packet size is the maximum, in the high speed mode, one packet of data corresponds to one page of data that is a processing unit of reading and writing of the flash memory. The data for the packet corresponds to the data for one page, which is the processing unit for reading and writing the flash memory. Because of these differences, different processing is performed in the high speed mode and the full speed mode.

  First, processing in the high speed mode will be described with reference to FIGS. FIG. 5 shows a CBW (Command Block Wrapper) and an A packet (hereinafter referred to as a packet in the high speed mode) transmitted from the host system side and data held in the reception endpoint. Showing the relationship. Here, the CBW includes command information, and a write request from the host system side is transmitted to the flash memory system side by the CBW. That is, at the time of a write request, information on the write command is included in the CBW. The A packet includes 512 bytes of data to be written to the flash memory. The reception endpoint is set to 512 bytes in order to hold one page of data in the flash memory. The capacity of the reception endpoint is preferably set as appropriate in consideration of the page capacity of the flash memory, the packet size (data capacity), and the like. For example, it is conceivable to set the capacity of the reception endpoint to a capacity corresponding to a common multiple of the page capacity and packet size (data capacity) of the flash memory.

  The CBW shown in FIG. 5 is converted into a parallel signal by the USB interface unit and held in the reception end point 6 under the control of the end point control unit. At this time, the endpoint control unit detects that the received data is CBW based on a flag or the like included in the CBW, and notifies the flash memory control unit that the CBW has been received. Subsequently, the flash memory control unit reads the CBW held in the reception endpoint 6 and recognizes that the command information included in the CBW is a write command.

  The A packet sent after receiving the CBW is converted into a parallel signal by the USB interface unit and held in the reception endpoint 6 under the control of the endpoint control unit. At this time, the write data (write data to the flash memory) included in the A packet is also held in the portion where the CBW was held. Therefore, only the write data to the flash memory is held in the reception endpoint 6. The reception endpoint 6 is a 512-byte buffer circuit, and the A packet contains 512 bytes of write data, so the reception endpoint 6 corresponds to data for one page of the flash memory. Data to be retained.

  When data corresponding to one page of data in the flash memory is stored in the reception endpoint, the end point control unit notifies the flash memory control unit of the fact, and the data from the reception end point to the flash memory is notified. The writing process is started. FIG. 6 shows the relationship between the reception end point 6 in which the data of the A packet is held and the page of the flash memory 9 to which the data is written. Here, the data held in the reception endpoint 6 is written to the page in the erased block under the control of the flash memory control unit. When several pages of data are sequentially sent in the A packet, the data are sequentially written from page 0 of the erased block. (The first data is sequentially written to page 0 and the next data is sequentially written to page 1).

Next, this writing process will be described. When the write process is performed, the following write process is set in the register in the flash memory control unit.
1) An internal write command is set as an internal command in a predetermined register in the flash memory control unit.
2) The page address of the write destination is set in a predetermined register in the flash memory control unit.
Subsequently, an internal command is executed based on the setting of the writing process. When this internal command is executed, information for executing the internal command is supplied to the flash memory. As a result, the data held in the reception endpoint 6 is stored in the data area of the page address specified by the setting of the writing process.

  Next, processing in the full speed mode will be described with reference to FIGS. FIG. 7 shows a CBW (Command Block Wrapper) and B packets 0 to 7 (hereinafter referred to as a packet in the full speed mode) transmitted from the host system side and a reception endpoint. This shows the relationship of data. Here, the CBW includes write command information as in the high-speed mode. The B packets 0 to 7 include 64 bytes of data to be written to the flash memory. Further, the reception endpoint is set to 512 bytes as described above.

  The CBW shown in FIG. 7 is converted into a parallel signal by the USB interface unit and held in the reception end point 6 under the control of the end point control unit. At this time, the endpoint control unit detects that the received data is CBW based on a flag or the like included in the CBW, and notifies the flash memory control unit that the CBW has been received. Subsequently, the flash memory control unit reads the CBW held in the reception endpoint 6 and recognizes that the command information included in the CBW is a read command.

  Here, in the full speed mode, since the capacity of data included in each packet of B packets 0 to 7 is 64 bytes, the endpoint controller does not notify the flash memory controller every time each packet is received. Instead, the end point control unit is set to notify the flash memory control unit when 512 bytes of write data is held in the receiving end point 6. In other words, when the capacity of the data included in each of the B packets 0 to 7 is 64 bytes, the flash memory control is performed from the endpoint controller when the data for 8 packets is held in the reception endpoint 6. The setting is made so that the end point control unit notifies the flash memory control unit when data for 8 packets is held (hereinafter referred to as a reception data accumulation mode). Regardless of the high speed mode or the full speed mode, the data included in the packet is continuously accumulated in the reception endpoint 6 until the data for one page of the flash memory is always held in the reception endpoint 6. The circuit may be designed so that after the data for one page of the flash memory is held in the reception end point 6, the end point control unit notifies the flash memory control unit.

  Under the reception data accumulation mode, the B packets 0 to 7 are converted into parallel signals by the USB interface unit, and are sequentially accumulated in the reception end point 6 under the control of the end point control unit. At this time, the write data (write data to the flash memory) included in the B packets 0 to 7 is also held in the portion where the CBW was held.

  When data for 8 packets of B packets 0 to 7 is held in the reception endpoint 6 (that is, data corresponding to data for one page of the flash memory is held), the endpoint control unit This is notified to the flash memory control unit, and data writing processing from the reception endpoint to the flash memory is started. FIG. 8 shows the relationship between the reception end point 6 in which the data of the B packets 0 to 7 are held and the page of the flash memory 9 to which the data is written. Here, the data held in the reception end point 6 is written to the page of the erased block under the control of the flash memory control unit as in the high speed mode.

In the write process in the full speed mode, the following write process is set in the register in the flash memory control unit as in the high speed mode.
1) An internal write command is set as an internal command in a predetermined register in the flash memory control unit.
2) The page address of the write destination is set in a predetermined register in the flash memory control unit.
Subsequently, an internal command is executed based on the setting of the writing process. When this internal command is executed, information for executing the internal command is supplied to the flash memory 9. As a result, the data held in the reception endpoint 6 is stored in the data area of the page address specified by the setting of the writing process.

  Next, a process for notifying the host system side of the processing result (information regarding whether or not the process has been completed normally) when the data writing process from the reception endpoint to the flash memory is completed will be described. In this process, the flash memory control unit receives status information related to the write process from the flash memory after the write process is completed, and creates a CSW (Command Status Wrapper) based on the status information.

The flash memory control unit writes the created CSW to the transmission end point 7 as shown in FIG. 9, and notifies the end point control unit to that effect. Thereafter, the endpoint control unit transmits the CSW written in the transmission endpoint 7 to the host system side via the USB interface unit (converted into a serial signal by the USB interface unit). Since this CSW includes information related to the write processing result, the host system can confirm the write processing result based on the information.
[Description of reading from flash memory]
The read request from the host system side is also transmitted to the flash memory system side by the CBW, as in the case of the write request. That is, at the time of a read request, a CBW including read command information is transmitted from the host system side. The CBW is held in the reception endpoint under the control of the endpoint controller. Hereinafter, similarly to the case of the write request, the endpoint control unit detects that the received data is CBW based on a flag or the like included in the CBW, and notifies the flash memory control unit that the CBW has been received. Subsequently, the flash memory control unit reads the CBW held in the reception endpoint, and recognizes that the command information included in the CBW is a read command.

  Next, processing for reading data from the flash memory based on a read request transmitted from the host system side to the flash memory system side by the CBW will be described with reference to the drawings. FIG. 10 shows the relationship between the flash memory 9 in which the data requested to be read from the host system side is stored and the transmission end point 7 holding the data to be transmitted to the host system side.

  In this reading process, one page of data in the flash memory 9 is read from the flash memory 9 to the transmission endpoint 7 under the control of the flash memory control unit. At this time, the physical address of the page read from the flash memory 9 (the address in the flash memory 9) can be obtained from the logical address supplied from the host system side and the address conversion table.

When this reading process is performed, the following reading process is set in the register in the flash memory control unit.
1) An internal read command is set in a predetermined register in the flash memory control unit as an internal command.
2) The page address (address in the flash memory 9) of the page to be read to the transmission endpoint 7 is set in a predetermined register in the flash memory control unit.
Subsequently, an internal command is executed based on the setting of the reading process. When this internal command is executed, information for executing the internal command is supplied to the flash memory 9. As a result, the data stored in the data area of the page address designated by the setting of the writing process is read out to the transmission end point 7.

  Here, in the case of the full speed mode, the capacity of data included in a packet transmitted from the transmission endpoint 7 to the host system side is 64 bytes, but the data for one page of the flash memory is the transmission endpoint 7. Is set so that transmission from the transmission end point 7 to the host system side is not started until it is held in (the setting sent from the endpoint control unit to the host system when data for 8 packets is held below) (Referred to as transmission data accumulation mode). Regardless of the high-speed mode and the full-speed mode, transmission from the transmission endpoint 7 to the host system side is not always started until data for one page in the flash memory is held in the transmission endpoint 7. The circuit may be designed as follows.

  In both the high-speed mode and the full-speed mode, after the error correction code has been normally generated and corrected for the data read to the transmission endpoint 7, the transmission endpoint 7 sends the error to the host system. It is preferable to start transmission to.

  The transmission end point 7 is set to 512 bytes in order to hold one page of data in the flash memory. The capacity of the transmission endpoint 7 is preferably set as appropriate in consideration of the page capacity of the flash memory, the packet size (data capacity), and the like. For example, it is conceivable to set the capacity of the transmission end point to a capacity corresponding to a common multiple of the page capacity and packet size (data capacity) of the flash memory.

  Next, transmission processing from the transmission endpoint to the host system will be described. FIG. 11 shows a packet transmitted from the transmission end point 7 to the host system side in the high speed mode. In the case of the high speed mode, data held in the transmission endpoint 7 is transmitted to the host system side in one packet (A packet). That is, the 512-byte data held in the transmission end point 7 is transmitted as an A packet including 512-byte data.

  FIG. 12 shows a packet transmitted from the transmission end point 7 to the host system side in the transmission data accumulation mode in the full speed mode. In the case of the full speed mode, data held in the transmission end point 7 is transmitted to the host system side in eight packets (B packets 0 to 7). That is, 512-byte data held in the transmission end point 7 is transmitted as B packets 0 to 7 including 64-byte data.

  In the transmission process to the host system side, the data held in the transmission endpoint 7 is converted into a serial signal by the USB interface unit and transmitted under the control of the endpoint control unit.

  Further, after the transmission processing from the transmission endpoint to the host system side is completed, the CSW is transmitted to notify the host system side of the read processing result (information regarding whether or not the processing has been normally completed). In this process, as in the case of the write process (see FIG. 9), the flash memory control unit writes the created CSW to the transmission endpoint 7, and the CSW written to the transmission endpoint 7 is the USB interface. Sent to the host system side via This CSW includes information regarding whether or not all the data instructed by the read request from the host system side can be normally read. Therefore, the host system side can confirm the write processing result based on this information.

  In the flash memory system described above, the interface on the host system side is the USB interface. However, the flash memory control circuit according to the present invention, and the memory controller and the flash memory system including the control circuit are compatible with the USB interface. It can also be applied to those having similar interfaces. For example, the present invention can be applied to a device having a buffer similar to a USB reception endpoint and a transmission endpoint.

FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention. FIG. 2 is a cross-sectional view schematically showing the structure of the memory cell 16 constituting the flash memory 2. FIG. 3 is a cross-sectional view schematically showing the memory cell 16 in the written state. FIG. 4 is a diagram schematically showing the structure of the address space of the flash memory 2. FIG. 5 is a diagram showing the relationship between the CBW and packet transmitted from the host system side and the data held in the reception endpoint 6. FIG. 6 is a diagram showing the relationship between the reception end point 6 and the page of the flash memory 9 to which data is written. FIG. 7 is a diagram showing the relationship between the CBW and packet transmitted from the host system side and the data held in the reception endpoint 6. FIG. 8 is a diagram showing the relationship between the reception end point 6 and the page of the flash memory 9 to which data is written. FIG. 9 is a diagram showing the relationship between the transmission end point 7 and the CSW transmitted to the host system side. FIG. 10 is a diagram showing the relationship between the transmission end point 7 and the page of the flash memory 9 in which data read to the transmission end point is stored. FIG. 11 is a diagram showing a relationship between a packet transmitted to the host system side and data held in the transmission endpoint 7. FIG. 12 is a diagram illustrating a relationship between a packet transmitted to the host system side and data held in the transmission endpoint 7.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Flash memory system 2 Memory controller 3 USB interface part 4 Endpoint control part 5 Control endpoint 6 Reception endpoint 7 Transmission endpoint 8 Flash memory control part 9 Flash memory 10 Host system 16 Memory cell 17 P type semiconductor substrate 18 Source diffusion region 19 Drain diffusion region 20 Tunnel oxide film 21 Floating gate electrode 22 Insulating film 23 Control gate electrode 24 Channel 25 Data region 26 Redundant region

Claims (5)

A transmission / reception means for transmitting / receiving data via a USB interface;
Received data holding means for holding data received via the USB interface;
Received data storage means for storing in the received data holding means data received by the transmitting / receiving means, including CBW (Command Block Wrapper) including a command and user data written in a flash memory;
And write processing control unit write the user data held in the received data holding unit in the flash memory,
Transmission data holding means for holding data to be transmitted via the USB interface;
It reads the user data stored in the flash memory, and a read-out processing control means for storing the read user data to the transmission data holding unit,
The reception data storage means has a function of determining whether the data received by the transmission / reception means is CBW or user data, and when the CBW and user data are received in this order, the reception data storage means CBW and user data are stored in the received data holding means so that user data received later is overwritten on the received CBW,
The write processing control unit, after one page of user data in the flash memory is held in the received data holding unit, the flash memory control circuit, wherein the benzalkonium initiates a write operation to the flash memory. CSW storage means for storing a CSW (Command Status Wrapper) indicating a result of processing executed based on the CBW in the transmission data holding means ;
Said receiving means, said after the user data of one page of the flash memory is stored in by Ri the transmission data holding unit to the read processing controller, or CSW is stored in the transmission data holding unit by the CSW storing means the control circuit of a flash memory according to claim 1, start to characterized and Turkey the transmission process after. 3. The flash memory control circuit according to claim 1, wherein the capacity of the received data holding means is the same as the data capacity of one page of the flash memory. Memory controller having a control circuit of one of the flash memory according to claim 1 to 3, wherein. Flash memory system including a control circuit and a flash memory of any of the flash memory according to claim 1 to 3, wherein.