JP4059002B2 - Memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory device using a volatile memory and a nonvolatile memory, and relates to the construction of a high-speed and inexpensive memory system.
[0002]
[Prior art]
In a memory system using a volatile memory and a non-volatile memory, as described in JP-A-2001-5723, the contents of the non-volatile memory are copied to the volatile memory when the power is turned on, and the volatile memory is transferred from the host. There are ways to access and use. In that case, when the power is shut off, the contents of the volatile memory are copied to the non-volatile memory, the processing result is notified to the host using a dedicated line, and the power is shut off safely. Hold.
[0003]
[Problems to be solved by the invention]
In the above prior art, data transfer between the volatile memory (DRAM) and the non-volatile memory (flash memory) is performed only at power-on or power-off, so the memory system is used after power-on. No consideration is given to performing the data transfer during the process. Further, since the data transfer is intended for the entire nonvolatile memory, it takes time to transfer a large-capacity memory, and it takes time to prepare for use as a memory system. Further, since the dedicated line is used for notifying the host that the copy process has been completed when the power is turned off, it cannot be controlled only by the existing volatile memory interface. Furthermore, it is not considered to access the nonvolatile memory from the host. Further, the difference between the data transfer rate of the volatile memory and the data transfer rate of the nonvolatile memory is not considered.
[0004]
An object of the present invention is to provide a memory device that can control data transfer between a volatile memory and a nonvolatile memory from a host and has improved controllability from the host.
[0005]
Alternatively, it is an object of the present invention to provide a memory device that can access a nonvolatile memory from a host and has improved controllability from the host.
[0006]
[Means for Solving the Problems]
In the present invention, the control circuit receives and interprets a command from the host, and starts data transfer between the volatile memory and the non-volatile memory in response to the interpreted command.
[0007]
Alternatively, according to the present invention, the control circuit is configured to switch between the volatile memory and the nonvolatile memory in response to an access command (including data read and data write) to a predetermined address on the volatile memory from the host. Data transfer in between.
[0008]
Alternatively, according to the present invention, the first interface located between the host and the control circuit is connected between the host and the control circuit, and the first interface for inputting / outputting data to be read / written to / from the volatile memory. The positioned second interface inputs / outputs data to be read / written from / to the nonvolatile memory.
[0009]
Alternatively, according to the present invention, an interface located between the host and the control circuit inputs / outputs data to be read / written to / from the volatile memory and inputs / outputs data to / from the nonvolatile memory to / from the nonvolatile memory.
[0010]
Alternatively, in the present invention, the holding circuit holds transfer data between the volatile memory and the nonvolatile memory.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
The memory device 4000 shown in FIG. 24 is mounted on an information terminal such as a mobile phone, a PDA (Personal Digital Assistant), a music playback device, a digital camera, a digital video camera, a set top box, a personal computer, a car navigation system, and the like. This is a memory device 4000 capable of
[0012]
The memory device 4000 has a function of writing data designated by the host 4040 to an address designated by the host 4040, a function of holding the written data for at least a certain period when power is supplied, and a host A memory device 4000 having a function of outputting data held at an address designated by 4040 to a host 4040, and holding part or all of written data even when power supply is stopped. The host 4040 of the memory device 4000 is capable of at least SDRAM for specifying an address to the memory device 4000, writing data to the memory device 4000, and reading data from the memory device 4000. (Synchronous dynamic random access memory) A memory device 4000 having a function that can be performed by interface 4001.
[0013]
The host 4040 here is an information processing apparatus such as a CPU or an ASIC built in the information terminal, for example. The memory device 4000 can store an operation program for the host 4040 to execute various information processing, for example.
[0014]
The operation program is, for example, various applications such as an OS (operation system), a driver, a JAVA virtual machine, a JAVA applet, etc. (“JAVA” is a registered trademark of Sun Microsystems). Further, the information processing here is, for example, operation control of each hardware constituting the information terminal, or processing such as data calculation, recording and reproduction of moving images and sounds. The host 4040 can operate based on an operation program stored in the memory device 4000 using the memory device 4000 as a main memory. The memory device 4000 can also store various data for processing by an operation program, for example. The data referred to here includes, for example, various data such as text, images, sounds, and moving images, program operation parameters, setting files, and the like. Other data can also be stored.
[0015]
The memory device 4000 includes an SDRAM 4010 that is a volatile memory but can be randomly accessed, a flash memory 4020 that is a nonvolatile memory, and an SDRAM compatible interface 4001 for the host 4040 to access the memory device 4000. The memory device 4000 is connected to the host 4040 via the SDRAM compatible interface 4001. Since the memory device 4000 operates as an SDRAM compatible memory, the host 4040 can control the memory device 4000 using the SDRAM interface. The memory device 4000 can store part or all of the data of the SDRAM 4010 in the flash memory 4020. The memory device 4000 can read part or all of the data in the flash memory 4020 to the SDRAM 4010. For example, if the data of the SDRAM 4010 is stored in the flash memory 4020 before the power supply to the memory device 4000 is stopped, the data loss of the SDRAM 4010 due to the power supply stop can be prevented. Further, for example, after starting the power supply to the memory device 4000 and before the host 4040 accesses the memory device 4000, if the data in the flash memory 4020 is read into the SDRAM 4010, the host 4040 makes the memory device 4000 non-volatile. Can be used as an SDRAM compatible memory. The memory device 4000 has a function that allows the host 4040 to arbitrarily specify data transfer between the SDRAM 4010 and the flash memory 4020. The memory device 4000 has an instruction receiving function for receiving an operation instruction of the memory device 4000 from the host 4040, and a state notification function for notifying the host 4040 of the state of the memory device 4000.
[0016]
The instruction reception function and the status notification function are performed by the host 4040 reading and writing data in a predetermined format with respect to a predetermined address of the memory device 4000. Therefore, the host 4040 can use the instruction reception function and the state notification function without newly adding a dedicated pin for instructing the memory device 4000 to the SDRAM interface. The existing SDRAM 4010 and the memory device 4000 can be easily replaced. The host 4040 of the memory device 4000 can instruct the memory device 4000 to transfer the data of the SDRAM 4010 to the flash memory 4020 and to transfer the data of the flash memory 4020 to the SDRAM 4010 at any time by the instruction receiving function.
[0017]
Here, since the memory device 4000 includes a nonvolatile data storage area, it is highly convenient. Further, since it has a transfer speed equivalent to that of a normal SDRAM 4010, the transfer time can be shortened as compared with the case of directly accessing the flash memory. Further, since the memory device 4000 has the SDRAM compatible interface 4001, the host 4040 having the SDRAM interface can use the memory device 4000 without newly designing or adding hardware.
[0018]
Next, examples of functions of the memory device 4000 will be described.
[0019]
The memory device 4000 has a function of through-passing the SDRAM compatible interface 4001 signal of the memory device 4000 to the SDRAM interface 4001 signal of the SDRAM 4010. Through the through-pass function of the SDRAM compatible interface 4001 signal, the host 4040 can use the memory device 4000 as the SDRAM compatible memory device 4000. For example, the host 4040 can issue a read command, a write command, a refresh command, etc. to the memory device 4000 in the same procedure as the SDRAM 4010. The memory device 4000 has a store function for transferring data held in a predetermined area of the SDRAM 4010 to a predetermined area of the flash memory 4020. The data transferred to the flash memory 4020 by the store function can be retained on the flash memory 4020 even if the data is lost from the SDRAM 4010 due to the stop of power supply to the memory device 4000.
[0020]
The store function is executed when the operation state of the memory device 4000 satisfies a predetermined store execution condition. One of the store execution conditions is, for example, that power supply is stopped. One of the store execution conditions is that a store execution instruction is issued from the host 4040, for example. One of the store execution conditions is, for example, that a predetermined register of the memory device 4000 takes a value in a predetermined range. The predetermined register is a counter register that counts the number of accesses from the host 4040 to the memory device 4000, for example.
[0021]
The memory device 4000 has store execution condition information that defines store execution conditions. The memory device 4000 has a function of changing store execution condition information.
The memory device 4000 has a function that allows the host 4040 to specify the change of the store execution condition information. The memory device 4000 has a function of storing store execution condition information in the flash memory 4020. The memory device 4000 has a function of reading store execution condition information from the flash memory 4020. The memory device 4000 has a load function of transferring data held in a predetermined area of the flash memory 4020 to a predetermined area of the SDRAM 4010.
[0022]
The load function is executed when the operation state of the memory device 4000 satisfies a predetermined load execution condition. One of the load execution conditions is, for example, that power supply is started. One of the load execution conditions is that a load execution instruction is issued from the host 4040, for example. One of the load execution conditions is, for example, that a predetermined register of the memory device 4000 takes a value in a predetermined range.
[0023]
The memory device 4000 has load execution condition information that defines the load execution condition. The memory device 4000 has a function of changing the load execution condition information. The memory device 4000 has a function that allows the host 4040 to specify the change of the load execution condition information. The memory device 4000 has a function of storing the load execution condition information in the flash memory 4020. The memory device 4000 has a function of reading load execution condition information from the flash memory 4020. The memory device 4000 has a function of associating the address of the SDRAM 4010 and the address of the flash memory 4020 according to a predetermined procedure.
[0024]
Data transfer in the store function and load function is performed between addresses associated by the address association function. The address association function is performed based on the address association information. In addition, there may be a defective area in the flash memory 4020 where data cannot be read / written normally. Therefore, the memory area of the flash memory 4020 needs not to use a defective area existing on the flash memory 4020. Therefore, the address association information associates the address of the SDRAM 4010 with the address of the flash memory 4020 so that no data access occurs to the defective area.
[0025]
The memory device 4000 includes an address association information storage register for storing address association information. The memory device 4000 has a function of changing the address association information stored in the address association information storage register. The memory device 4000 has a function that allows the host 4040 to specify change of the address association information. The memory device 4000 has a function of storing address association information in the flash memory 4020. The memory device 4000 has a function of reading address association information from the flash memory 4020. The memory device 4000 has a function of monitoring a power supply state to the memory device 4000.
[0026]
Next, the configuration of the memory device 4000 will be described in more detail.
The memory device 4000 includes at least an SDRAM compatible interface 4001, an SDRAM 4010, a flash memory 4020, and a control device 4030. The SDRAM 4010 and the control device 4030 are connected by the SDRAM interface 4002.
[0027]
The control device 4030 and the flash memory 4020 are connected by a flash memory interface 4003. An SDRAM compatible interface 4001 for connecting the memory device 4040 and the host 4040 is connected to the control device 4030.
[0028]
In the memory device 4000, for example, the SDRAM 4010, the flash memory 4020, and the control device 4030 are configured on different silicon chips, and the terminals of each silicon chip are connected by, for example, wire bonding or the like. It can be set as the multichip package sealed in. Here, the package refers to an LSI package form such as TSOP (Thin Small Outline Package) or BGA (Ball Grid Array).
[0029]
The SDRAM compatible interface 4001 is, for example, a terminal group for inputting / outputting electric signals to / from a chip and the role of the terminal group, and is an interface whose electrical characteristics are compatible with the terminal group of the SDRAM. For example, the memory device 4000 is compatible with SDRAM in terms of characteristics such as setup time, hold time, and CAS latency of each signal.
[0030]
An SDRAM compatible interface 4001 for connecting the host 4040 and the control device 4030 is, for example, JE DEC Not only the standard SDRAM and the electrical characteristics of the terminal group, but also the package size of the memory device 4000, the size of the terminal group such as pins and solder balls arranged in the package of the memory device 4000, and the layout of the terminal group are compatible. It is desirable to have sex.
[0031]
With the configuration, the host 4040 provided with the SDRAM compatible interface 4001 can easily use the SDRAM and the memory device 4000 by replacing them.
[0032]
The SDRAM compatible interface 4001 is an interface in which, for example, an addressable memory area is expanded by an amount corresponding to a control register with respect to the SDRAM interface 4002. The SDRAM 4010 has a function of writing data designated by the host 4040 to an address designated by the host 4040, a function of holding the written data for at least a predetermined period when power is supplied, and a specification designated by the host 4040. The memory device 4000 has a function of reading out data stored at the designated address and outputting it to the host 4040. This is a memory device 4000 in which the data transfer speed is improved by executing the input / output of signals in synchronization with the clock, compared to a DRAM that is not synchronized. The SDRAM 4010 has an SDRAM interface 4002. The SDRAM interface 4002 is a terminal group for an external device (not shown) that uses the SDRAM 4010 to specify an address and data for the SDRAM 4010.
[0033]
The flash memory 4020 has a function of writing data designated by the host 4040 at an address designated by the host 4040, a non-volatile property that retains the written data for at least a certain period even when power supply is stopped, and the host 4040 The memory device 4000 has a function of reading out data stored at an address designated in FIG. The flash memory 4020 has a flash memory interface 4003. The flash memory interface 4003 is a terminal group for an external device (not shown) that uses the flash memory 4020 to specify an address and data for the flash memory 4020.
[0034]
The control device 4030 is a control device 4030 having a function of comprehensively controlling the operation of each unit of the memory device 4000. The control device 4030 has a function of performing overall control of operations of each unit of the memory device 4000 and realizing each function of the memory device 4000. The control device 4030 has a function of connecting the SDRAM compatible interface 4001 and the SDRAM interface 4002 and relaying data transfer between the host 4040 and the SDRAM 4010. The control device 4030 has a store function for transferring data held in a predetermined area of the SDRAM 4010 to a predetermined area of the flash memory 4020. The control device 4030 has a load function for transferring data held in a predetermined area of the flash memory 4020 to a predetermined area of the SDRAM 4010. The control device 4030 has an address association function that associates the address of the SDRAM 4010 with the address of the flash memory 4020 in accordance with a predetermined procedure. The control device 4030 includes a control register 4031. The control register 4031 is a register for storing various kinds of information necessary when the control device 4030 operates.
[0035]
Part or all of the control register 4031 can be rewritten by the host 4040. A part or all of the control register 4031 can be read by the host 4040.
[0036]
When the host 4040 rewrites the control register 4031, the host 4040 writes data in a predetermined format to a predetermined address of the control register 4031 by the SDRAM compatible interface 4001. When the host 4040 reads the control register 4031, the host 4040 reads predetermined data from a predetermined address of the control register 4031 by the SDRAM compatible interface 4001.
[0037]
The control device 4030 can access any control register 4031. Alternatively, a predetermined register can be prohibited from being rewritten or read out.
[0038]
The designation of the address of the control register 4031 can be performed in the same procedure as the address designation of the SDRAM. The control register 4031 has an area for the host 4040 to issue various operation instructions to the memory device 4000, for example. The control register 4031 has an area for storing information for the host 4040 to know the operation state of the memory device 4000, for example. The control register 4031 has an area for storing store execution condition information, for example. The control register 4031 has an area for storing, for example, load execution condition information. The control register 4031 has an area for storing address association condition information, for example.
[0039]
The control device 4030 includes a voltage detection device 4032. The voltage detection device 4032 is a device that monitors a power supply voltage supplied to the memory device 4000 from an external device. The voltage detection device 4032 has a function of detecting that the supply voltage to the memory device 4000 has reached a value in a predetermined range or that the supply voltage is in a predetermined range. For example, when the power to the memory device 4000 is turned on, it is detected that the power supply voltage has become larger than a predetermined value. The predetermined value is, for example, a voltage value at which the control device 4030 can operate normally, a voltage value at which the SDRAM 4010 can operate normally, a voltage value at which the flash memory 4020 can operate normally, or the like. Further, for example, it is detected that the power supply voltage of the memory device 4000 has become smaller than a predetermined value. The predetermined value is, for example, a voltage value at which the control device 4030 can operate normally, a voltage value at which the SDRAM 4010 can operate normally, a voltage value at which the flash memory 4020 can operate normally, or the like.
[0040]
The control device 4030 uses the voltage detection device 4032 to load data in a predetermined area of the flash memory 4020 into a predetermined area of the SDRAM 4010 when the power supply becomes equal to or higher than a predetermined value, for example, and the power supply becomes lower than a predetermined value. Then, a process of storing data in a predetermined area of the SDRAM 4010 in a predetermined area of the SDRAM 4010 can be performed.
[0041]
Next, a configuration example of the memory area of the memory device 4000 will be described.
[0042]
The memory device 4000 includes at least one nonvolatile area 4011 in the memory area of the SDRAM 4010.
[0043]
The nonvolatile area 4011 is an area where mirroring 4063 using the flash memory 4020 is performed.
[0044]
Of the memory area of the SDRAM 4010, an area that is not the nonvolatile area 4011 is a volatile area 4012.
[0045]
Here, the data stored in the mirror area 4021 of the flash memory 4020 is matched with the data stored in the nonvolatile area 4011 of the SDRAM 4010, or a copy of the data stored in the nonvolatile area 4011 of the SDRAM 4010 is flashed. The storage in the mirror area 4021 of the memory 4020 is referred to as mirroring 4063. However, the mirror area 4021 of the flash memory 4020 is managed by a logical address excluding the defective area of the flash memory 4020.
[0046]
The memory device 4000 includes at least a mirror area 4021 for mirroring 4063 of the SDRAM 4010 and a control register storage area 4022 for storing the control register 4031 in the memory area of the flash memory 4020. . The mirror area 4021 has a memory area that can store at least all data stored in the nonvolatile area 4011 of the SDRAM 4010.
[0047]
Since the SDRAM 4010 is a volatile memory, data written to the SDRAM 4010 is lost when power supply to the memory device 4000 is stopped. However, since the data stored in the nonvolatile area 4011 can be mirrored in the mirror area 4021 of the flash memory 4020, it can be retained even after the power is shut off. Data stored in the volatile area 4012 is lost when the power is turned off. The host 4040 can access the nonvolatile area 4011 of the SDRAM 4010, the volatile area 4012 of the SDRAM 4010, and the control register 4031 by designating a predetermined address using the SDRAM compatible interface 4001.
[0048]
Next, an example of a data transmission path in the memory device 4000 will be described.
[0049]
The data access 4051 is a path for the host 4040 to access the SDRAM 4010 using the SDRAM compatible interface 4001. At this time, the host 4040 can freely access both the nonvolatile area 4011 and the volatile area 4012.
[0050]
The register read 4052 is a path for the host 4040 to read various information stored in the control register 4031 using the SDRAM compatible interface 4001. The register write 4053 is a path for the host 4040 to write various information to the control register 4031 using the SDRAM compatible interface 4001. The power supply start 4061 is a path for loading data from the mirror area 4021 to the nonvolatile area 4010 when the power supply to the memory device 4000 is started. A load 4062 is a path for loading data from the mirror area 4021 to the nonvolatile area 4010 when a load execution instruction is issued from the host 4040 to the memory device 4000. The store 4062 is a path for storing data from the nonvolatile area 4010 to the mirror area 4021 when a store execution instruction is issued from the host 4040 to the memory device 4000. The power supply stop 4061 is a path for storing data from the nonvolatile area 4010 to the mirror area 4021 when the power supply to the memory device 4000 is stopped.
[0051]
Next, an example of the operation of the memory device 4000 configured as described above will be described.
[0052]
FIG. 25 is a flowchart showing an example of the operation of the memory device 4000 from the start of power supply to the stop of power supply. First, the host 4040 starts supplying power to the memory device 4000 (4101). When the power supply is started, the memory device 4000 loads the data in the mirror area 4021 of the flash memory 4020 into the nonvolatile area 4011 of the SDRAM 4010.
[0053]
Next, an example of the flow of load processing will be described. When the supply voltage rises to a value at which the voltage detection device 4032 can operate, the memory device 4000 sets a busy signal in the control register 4031 (4102). The busy signal is stored in a predetermined format at a predetermined address in the control register 4031. The host 4040 can know the internal state of the memory device 4000 by polling the data at the address of the control register 4031. During the load process, the SDRAM compatible interface 4001 and the SDRAM interface 4002 are electrically separated.
[0054]
With the above processing, access from the host 4040 using the SDRAM compatible interface 4001 to the control register 4031 and load processing from the flash memory 4020 using the SDRAM interface 4002 to the SDRAM 4010 can be executed in parallel. The memory device 4000 monitors the power supply state using the voltage detection device 4032 and waits until the supply voltage reaches a predetermined value (4103). Here, the predetermined value is a voltage value at which both the SDRAM 4010 and the flash memory 4020 can operate normally.
[0055]
Next, various control information is read from the control register storage area 4022 of the flash memory 4020 and stored in the control register 4031 (4104). here , Reading part or all of the contents of the control register 4031 storage area of the flash memory 4020 to the control register 4031 of the control device 4030 is referred to as register restoration.
[0056]
Next, based on the address association information in the read control register 4031, the data in the mirror area 4021 of the flash memory 4020 is loaded into the nonvolatile area 4011 of the SDRAM 4010 (4105). When the loading is completed, the busy signal of the control register 4031 is canceled (4106).
[0057]
When the load process is completed, the memory device 4000 thereafter operates as an SDRAM compatible memory until a shutdown instruction is received from the host 4040 (4107) (4108). The shutdown instruction is an instruction for notifying the memory device 4000 that power supply is stopped from the host 4040, and the host 4040 writes data in a predetermined format to a predetermined address of the control register 4031. Realize with. When the memory device 4000 receives a shutdown instruction from the host 4040, the memory device 4000 mirrors the data in the nonvolatile area 4011 of the SDRAM 4010 to the mirror area 4021 of the flash memory 4020.
[0058]
Next, an example of the flow of store processing will be described. When receiving the shutdown instruction from the host 4040, the memory device 4000 sets a busy signal in the control register 4031 (4109). The busy signal is stored in a predetermined format at a predetermined address in the control register 4031. The host 4040 can know the internal state of the memory device 4000 by polling the data at the address of the control register 4031. During execution of the store process, the SDRAM compatible interface 4001 and the SDRAM interface 4002 are electrically separated. With the above processing, access from the host 4040 using the SDRAM compatible interface 4001 to the control register 4031 and store processing from the SDRAM 4010 using the SDRAM interface 4002 to the flash memory 4020 can be executed in parallel.
[0059]
Next, the data in the nonvolatile area 4011 of the SDRAM 4010 is stored in the mirror area 4021 of the flash memory 4020 based on the address association information in the read control register 4031 (4110).
[0060]
Next, various control signals stored in the control register 4031 are written into the control register storage area 4022 of the flash memory 4020 (4111). here , Writing a part or all of the contents of the control register 4031 of the control device 4030 to the storage area of the control register 4031 of the flash memory 4020 is referred to as register saving 4071. When the register saving is completed, the busy signal of the control register 4031 is canceled (4112). When the host detects that the busy state is released by polling the control register 4031, the host stops the power supply to the memory device 4000.
[0061]
When the above-described procedure is executed, the data held in the SDRAM 4010 in the memory device 4000 is lost due to the stop of power supply to the memory device 4000, but a copy of a part or all of the data is stored in the flash memory 4020. The data stored in the flash memory 4020 can be used when power supply to the memory device 4000 is started next time.
[0062]
Next, the operation when the memory device 4000 is used as an SDRAM compatible memory (4108) will be described in more detail.
[0063]
FIG. 26 is a diagram showing an example of a processing flow when the memory device 4000 operates as an SDRAM compatible memory. The memory device 4000 receives various SDRAM operation instructions such as read, write, and refresh from the host 4040 via the SDRAM interface 4001 (4201).
[0064]
Next, the process branches according to the received operation instruction. If the received operation instruction is read or write, the memory address designated by the host 4040 is determined (4202). If the received operation instruction is other than read or write, or if the designated memory address designates a memory area of the SDRAM, the SDRAM compatible interface 4001 signal is passed through to the SDRAM interface 4002 ( 4203). With this process, the memory device 4000 can operate as an SDRAM compatible memory.
[0065]
If the received operation instruction is read or write and the specified memory address specifies the control register 4031, the process branches depending on whether the instruction is a read instruction or a write instruction (4204). . If the received operation instruction is write, the designated data is written to the designated address of the control register 4031 (4205). If the received operation instruction is read, the data stored in the designated address of the control register 4031 is output to the host 4040 via the SDRAM compatible interface 4001 in a predetermined format (4207). With this processing, the memory device 4000 can accept an operation instruction from the host 4040 without adding a signal pin to the SDRAM interface, and can notify the host 4040 of various information such as the operation state of the memory device 4000. It becomes possible.
[0066]
Next, when an operation instruction is issued from the host 4040 by accessing the control register 4031, the designated operation is started (4206). Here, the operation includes, for example, a load process, a store process, and an address association process. During the execution of the operation, in order to prevent contention for access to the SDRAM 4020, for example, the SDRAM access of the host 4040 is prohibited or the access is ignored. Alternatively, for example, a configuration in which a plurality of SDRAMs 4020 are provided, or a configuration in which the SDRAMs 4020 can be accessed independently from a plurality of banks, for example, and a plurality of processes can be executed in parallel may be employed. For example, the processing from 4201 to 4203 or 4201 to 4206 is repeated until a shutdown instruction is issued from the host as indicated by 4107 and 4108 in FIG. That is, the host 4040 can use the memory device 4000 as an SDRAM compatible memory.
[0067]
Although an example in which the SDRAM is used in the memory device 4000 has been described here, another memory such as a DDR-SDRAM (double data rate SDRAM) may be used. Although an example in which the SDRAM compatible interface 4001 is used as an interface for connecting the memory device 4000 and the host 4040 has been described here, another interface, for example, a DDR-SDRAM interface may be used. . Although an example in which the flash memory 4020 is used as the nonvolatile memory has been described here, other nonvolatile memories can be used.
[0068]
Next, a more detailed embodiment of the memory device 4000 to which the present invention is applied will be described.
[0069]
FIG. 1 shows an example of the internal configuration of an embodiment of a memory device 101 to which the present invention is applied. The memory device 101 includes a flash memory 102 that is a nonvolatile memory, an SDRAM (synchronous DRAM) 103 that is a volatile memory, and a memory control unit 104 that controls these memories. The memory control unit 104 controls data transfer between the host 111 and the memory device 101 and between the flash memory 102 and the SDRAM 103 in response to a request from the host 111. Normally, the host 111 directly accesses the SDRAM 103 via the SDRAM interface 112. However, by writing to a specific address, the memory device 101 can transfer data between the flash memory 102 and the SDRAM 103, format the flash memory 102, and the like. The internal processing can be instructed. The host 111 corresponds to, for example, a mobile phone, a personal digital assistant (PDA), a personal computer, a music playback (and recording) device, a camera, a video camera, a set top box terminal, and the like.
[0070]
The memory control unit 104 includes a data transfer control unit 105, a flash memory interface control unit 106, an SDRAM interface control circuit 107, and a data buffer 108. When the host 111 directly accesses the SDRAM 103, the data transfer control unit 105 and the SDRAM interface control circuit 107 are through-passed. Data transfer between the flash memory 102 and the SDRAM 103 is performed via the data buffer 108 in order to absorb the transfer speed difference between the two devices. When transferring data from the flash memory 102 to the data buffer 108 (reading from the flash memory 102), the ECC control circuit 109 in the flash memory interface control unit 106 has an error in the data read from the flash memory 102. If there is an error, correct the data. At this time, if the sector to be read is a defective sector, the alternative sector control circuit 110 detects an alternative sector for the defective sector, and data is read from the detected alternative sector. When transferring data from the data buffer 108 to the flash memory 102 (writing to the flash memory 102), the read data is transferred from the data buffer 108 to the flash memory interface control unit 106 via the data transfer control unit 105. Transferred. The flash memory interface control unit 106 generates an ECC for the transfer data. The generated ECC is written in the flash memory 102 together with the transfer data. At this time, if the sector to be written is a defective sector, the alternative sector control circuit 110 detects an alternative sector for the defective sector, and data is written to the detected alternative sector.
[0071]
FIG. 2 is a diagram showing an example of the address space and usage method of the SDRAM 103 and the flash memory 102. The address space of the SDRAM 103 includes a system work area 201, a command / status holding area 202, a volatile area 203, and a nonvolatile area 204. Information necessary for the host 111 to manage the system is stored in the system work area 201 (however, it may be stored in the volatile area 203 described later). The command / status holding area 202 is an area provided for instructing the memory device 101 to perform internal processing. The volatile area 203 is an area for storing information necessary for the host 111 to process an application. The contents of the volatile area 203 are erased when the memory device 101 is powered off. The nonvolatile area 204 stores information that needs to be retained even after the power is shut off. Since the SRDAM 103 is a volatile memory, information stored in the non-volatile area 204 on the SDRAM 103 is copied to the flash memory 102 and held on the flash memory 102 before power-off.
[0072]
The following processing can be performed using the address space on the SDRAM 103 described above. After the power is turned on, the program data on the flash memory 102 is copied to the volatile area 203 of the SDRAM 102, and the host 111 can use the program by accessing the volatile area 203 on the SDRAM 103. In this case, the program data stored in the volatile area 203 when the power is turned off is discarded, but there is no problem because the program data is stored in the flash memory 102. Further, after the power is turned on, the user data on the flash memory 102 is copied to the nonvolatile area 204 of the SDRAM 103, and the host 111 can use the user data by accessing the nonvolatile area 204 on the SDRAM 102. When user data has been changed or added, the user data is copied to the flash memory 102 and held on the flash memory 102 before the power is turned off.
[0073]
FIG. 3 is a diagram illustrating an example of processing contents, that is, commands instructed by the host 111 to the memory device 101. The address of the command is mapped to the command / status holding area 202 described above, and is arranged at the address obtained by adding the offset address 301 from the head address A209 of the command / status holding area 202. Address 0 specifies the start address (ADRsdB210) of the volatile area 203, and address 1 specifies the size (y) of the volatile area 203. Address 2 designates the top address (ADRsdC211) of the nonvolatile area 204, and address 3 designates the size (z) of the nonvolatile area 204. As a result, the volatile area 203 and the nonvolatile area 204 can be mapped to an arbitrary address space on the SDRAM 103. In this example, the command / status holding area 202 has a predetermined fixed value, but can be mapped to an arbitrary space by applying the same rules as described above. In this case, the head address (ADRsdA209) of the command / status holding area 202 for the host to access first is stored in advance in a register in the memory device 101 or the flash memory 102. Address 4 indicates the format of the flash memory 102. The address 5 designates a start sector address (Dtx 213) at the time of data transfer or erasure to the flash memory 102. The address 6 designates a data transfer start address (Ctx 212) for the SDRAM 103. The address 7 specifies the data transfer size between the flash memory 102 and the SDRAM 103 or the data erase size of the flash memory 102. Address 8 activates data transfer between flash memory 102 and SDRAM 103. Address 9 specifies the power saving mode. When the command corresponding to the address 9 is issued, the power to the flash memory 102 and the circuit for controlling the memory 102 is shut off.
[0074]
The memory device 101 stores status / error information 314 at address n + 1 in order to notify the host 111 of the processing status of the command issued by the host 111. After issuing a command, the host 111 can know the processing result of the issued command by accessing the storage area indicated by the address n + 1.
[0075]
FIG. 4 is a diagram showing an example of the status and error contents. Bit0 indicates that command processing is in progress (401). Bit1 indicates that the process has been completed normally (402). Bit 2 indicates that the above-described ECC correction was performed and correction was possible (403). Bit 3 indicates that ECC correction was performed but correction was impossible (404). Bit4 indicates that command processing could not be executed (405).
[0076]
FIG. 5 is a flowchart showing a processing procedure of the system when the command is issued. The host 111 issues a command to the memory device 101 by writing data to the above address (501). The memory device 101 that has received the command decodes the command (508), and executes internal processing for the issued command based on the decoding result (509). After the processing is completed, the memory device 101 writes the result to the address n + 1 where the status / error information is stored (510). The host 111 reads the address (502) and determines whether or not the processing designated by the command has been completed normally (503). If not completed normally (505), the process designated by the command is retried or abnormally terminated (507).
[0077]
In the present invention, the memory control unit 104 shown in FIG. 1 has a function for executing the above-described processing. Hereinafter, the data transfer control unit 105 that forms the core of the memory control unit 104 will be described in detail.
[0078]
FIG. 6 is a diagram illustrating an internal configuration of the data transfer control unit 105. The data transfer control unit 105 includes a command decoder 601, a sequencer 602, an address mapping table 603, a flash address (ADRfl) generation circuit 604, a sector counter 605, a flash-buffer transfer circuit 606, an SDRAM-buffer transfer circuit 607, an SDRAM address (ADRsd). ) Generation circuit 608, MUX / DEMUX0 (609), buffer address (ADRbu) generation circuit 610, and MUX / DEMUX1 (611). The command decoder 601 interprets the content of the command issued by the host 111. The sequencer 602 manages the overall processing of the data transfer control unit 105.
[0079]
FIG. 7 is a diagram illustrating an example of state transition of the sequencer 602. After power is turned on to the memory device 101, the sequencer 602 shifts to the SDRAM mode 702 and the memory device 101 operates as the SDRAM 103. Thereafter, the state of the sequencer 602 is changed by a command issued by the host 111. When the command CMDtx 706 (address 8 shown in FIG. 3) for starting data transfer of the flash memory 102 is issued from the host 11, the sequencer 602 transitions to the flash transfer mode 703. At the time of writing STtx 707 (write to address n + 1 in FIG. 3) in which the data transfer process is completed and the status information is written, the sequencer 602 transitions to the SDRAM mode 702 again. When the command CMDfm 708 (address 4 in FIG. 3) for formatting the flash memory 102 is issued, the sequencer 602 transitions to the flash format mode 704, and after the processing is completed, transition to the SDRAM mode 702 after the status writing STfm 709 is executed. . When a command CMDer 710 (address 10 in FIG. 3) for erasing data on the flash memory 102 is issued, the sequencer 602 shifts to the flash data erasing mode 705, and after the processing is completed, the SDRAM mode 702 is executed after the status writing STer 711 is executed. Transition to.
[0080]
Returning to FIG. 6, the description will be continued. The address mapping table 603 assigns the nonvolatile area 204 in the address space in the SDRAM 103 to the logical sector address 205 of the flash memory 102. The ADRfl generation circuit 604 generates a logical sector address on the flash memory 102. The sector counter 605 manages the number of data transfer sectors in the flash memory 102 based on the transfer size designated by the host 111. The flash-buffer transfer circuit 606 executes data transfer between the flash memory 102 and the data buffer 108. Similarly, the SDRAM-buffer transfer circuit 607 executes data transfer between the SDRAM 103 and the data buffer 108. The ADRsd generation circuit 608 generates an address for accessing the SDRAM 103. The MUX / DEMUX0 (609) selects either the SDRAM interface 112 bus connected to the host 111 or the SDRAM interface bus 112 generated by the data transfer control unit 105 at the time of writing, and the SDRAM interface control circuit 107. Send to. At the time of reading, the SDRAM 103 data sent from the SDRAM interface control circuit 107 is sent to the data bus of the SDRAM interface 112 connected to the host 111 or the SDRAM-buffer transfer circuit 607. The ADRbu generation circuit 610 generates an address of the data buffer 108. The MUX / DEMUX 1 (611) sends the output data bus of the flash-buffer transfer circuit 606 or the SDRAM-buffer transfer circuit 607 to the data buffer 108 when writing to the data buffer 108. When data is read from the data buffer 108, the data is sent to the flash-buffer transfer circuit 606 or the SDRAM-buffer transfer circuit 607.
[0081]
Hereinafter, the operation of each circuit will be described by taking as an example data transfer processing from the flash memory 102 to the SDRAM 103.
[0082]
The host 111 designates a transfer start logical sector address (Dtx 213) on the flash memory 102 side before starting data transfer (address 5 in FIG. 3). As an address designation method, in addition to designating Dtx 213, there is a method of designating an address (Ctx 212) on the SDRAM 103. In that case, Ctx 212 is converted to Dtx 213 based on the address mapping table 603. Dtx 213 is held by the ADRfl generation circuit 604 and sent to the flash memory interface control unit 106. The host 111 sets the transfer size using a command (address 7 in FIG. 3) for setting the data transfer size. The set transfer size is held in the sector counter 605. Here, if the transfer size is designated in bytes, the transfer size information is converted into sectors in the counter 605 and sent to the flash memory interface control unit 106. Further, the host 111 issues a command (address 6 in FIG. 3) for setting the transfer start address Ctx 212 of the SDRAM 103. Ctx 212 is held in the ADRsd generation circuit 608.
[0083]
When a command CMDtx 706 for starting data transfer is issued, the command decoder 601 interprets the command content. The sequencer 602 makes a transition to the flash transfer mode 703 and instructs to send the outputs of the ADRsd generation circuit 608 and the SDRAM-buffer transfer circuit 607 to the SDRAM interface control circuit 107 via MUX / DEMUX0 (609). In addition, the flash memory interface control unit 106 is instructed to read data from the flash memory 102 for the number of transfer sectors specified from the logical sector address Dtx 213. The read sector data (SCTn) is transferred to the data buffer 108 via the flash-buffer transfer circuit 606 and MUX / DEMUX1 (611). Thereafter, the data is transferred from the data buffer 108 to the SDRAM interface control circuit 107 via the SDRAM-buffer transfer circuit 607 and MUX / DEMUX0 (609), and is written in the SDRAM 103.
[0084]
FIG. 8 is a diagram illustrating an example of data transfer timing. When one sector (SCTO (802)) is transferred from the flash memory 102 to the data buffer 108, data transfer from the data buffer 108 to the SDRAM 103 is started (804), and at the same time, data from the flash memory 102 to the data buffer 108 is started. Data transfer continues (transfer of SCT1). Note that data transfer from the SDRAM 103 to the flash memory 102 is performed through a path opposite to the transfer path described above.
[0085]
As described above, by executing data transfer from the flash memory 102 to the SDRAM 103 in advance according to a command from the host 111, the host 111 can access data on the SDRAM 103 at high speed. Further, by transferring the data on the SDRAM 103 to the flash memory 102, the data can be held even after the power is shut off.
[0086]
FIG. 9 is a diagram showing a second embodiment of the memory device 901 to which the present invention is applied. In addition to the SDRAM interface 112 shown in FIG. 1, the memory device 901 has a MultiMediaCard (MultiMediaCard is a registered trademark of Infineon Technologies AG; hereinafter abbreviated as “MMC”) as a connection interface with the host 906. . The MMC is a memory card that uses the flash memory 102 as a storage medium, and the host 906 reads and writes data in the flash memory 102 by issuing an MMC command. That is, the memory device 901 has a function as an MMC in addition to the above-described functions such as transfer between memories. Therefore, the MMC interface 907 in the memory device 901 conforms to the MMC specification.
[0087]
As shown in FIG. 10, the MMC interface 907 includes a chip select terminal (CS) 1001, a command terminal (CMD) 1002, two ground terminals (GND1) 1003 and 1006, and a power supply terminal (VCC1) from the host 906. The terminal is composed of seven terminals 1004, a clock terminal (CLK 1) 1005, and data (DAT) 1007. The CS 1001 is an input terminal used in the MMC SPI mode operation, and becomes active at a low level. The CMD 1002 is an input / output terminal used by the host 906 to transmit a memory card command conforming to the MMC specification to the memory device 901 and receive a memory card response conforming to the same specification from the memory device 901. The DAT 1007 is an input / output used by the host 906 to transmit input data in a format compliant with the memory card interface specification to the memory device 901 and receive output data in a format compliant with the specification from the memory device 901. Terminal. CLK1 (1005) is a terminal to which a clock signal supplied from the host 906 is input. When the host 906 sends and receives memory card commands and memory card responses through the CMD 1002 and sends and receives host data through the DAT 1007, a clock signal is input to the CLK1 (1005). When the transfer speed of the MMC interface 907 becomes a bottleneck in the system, the specification of the MMC interface 907 is changed to increase the clock frequency of CLK1 (1005), or the data is parallelized using a plurality of DAT1007. You may forward to.
[0088]
Compared to the internal configuration of the memory device 101 shown in FIG. 1, the internal configuration of the memory device 901 includes an MMC interface control unit 903, and the MMC interface control unit 903 is connected to the data transfer control unit 905. Is different. Here, in the above-described embodiment, an example in which command issuance from the host 111 is executed via the SDRAM interface 112 has been described. However, in the configuration of this embodiment, it can be executed via the MMC interface 907. Is possible. That is, the command shown in FIG. 3 can be issued from the host 906 to the memory device 901 as an MMC command. The command control circuit 904 interprets the issued command in the MMC interface control unit 903. This is the same function as the command decoder 601 shown in FIG.
[0089]
Further, as an embodiment for realizing the same function as described above, an internal configuration as shown in FIG. 13 may be taken. This is composed of an MMC control unit 1302 and a flash memory 102 having a function necessary for realizing a function as an MMC, a memory overall control unit 1304, and an SDRAM 103. The memory overall control unit 1304 includes an interface conversion control circuit 1305 having a function of converting the MMC interface 907 and the SDRAM interface 112 and the SDRAM interface control circuit 107. In the case of this configuration, the same functions as in the second embodiment are provided to the host 1306 without the MMC interface 907 (via the SDRAM interface 112) by diverting the control LSI for MMC as it is. can do.
[0090]
The present invention is not limited to the MMC interface 907 and can be applied to various interfaces. 11 and 12 respectively show that the present invention is an SD card (a small memory card having a width of 24 millimeters, a length of 32 millimeters, a thickness of 2.1 millimeters, having nine external terminals and mounted with a flash memory) and a memory stick. It is a figure which shows the outline of the internal structure of the memory devices 1101 and 1201 applied to the interface of (Memory Stick is a registered trademark of Sony Corporation).
[0091]
The SD card external terminal is composed of nine terminals, and these positions are, from the end, Data2 terminal 1104, Data3 terminal 1105, Com terminal 1106, Vss terminal 1107, Vdd terminal 1108, Clock terminal 1109, Vss terminal 1110, Data0 terminal 1111, Data 1 terminals 1112 are arranged in this order. The Vdd terminal 1108 is a power supply terminal, the Vss terminal 1107 is a ground terminal, the Data 0 terminal 1111, the Data 1 terminal 1112, the Data 2 terminal 1104 and the Data 3 terminal 1105 are data input / output terminals, the Com terminal 1106 is a command input / output terminal, and the Clock terminal 1109 is a clock. Input terminal. In this case, although the interface specification with the SD card host 1114 connected to the outside is different from that of the MMC, it has an external terminal very similar to the MMC external terminal, and issues a command from the outside in the same way as the MMC. The present invention can be applied because of its operating characteristics.
[0092]
On the other hand, the Memory Stick external terminal is composed of 10 terminals, and the positions thereof are GND terminal 1204, BS terminal 1205, Vcc terminal 1206, and reserved terminal Rsv by skipping one from the end, DIO terminal 1207, INS terminal 1208, reserved terminal. One Rsv is skipped and the SCK terminal 1209, the Vcc terminal 1210, and the Gnd terminal 1211 are arranged in this order. The Vcc terminal 1206 is a power supply terminal, the Gnd terminal 1204 is a ground terminal, the DIO terminal 1207 is a command / data input / output terminal, and the SCK terminal 1209 is a clock input terminal. Although the memory stick is different from the MMC in the interface specification with the memory stick compatible host 1213 connected to the outside, the memory stick has a feature that operates by issuing a command from the outside in the same manner as the MMC, so that the present invention can be applied. it can.
[0093]
As described above, the host 906 having the MMC interface 907 and the SDRAM interface 112 can use the memory device 901 not only as a high-speed volatile and non-volatile memory but also as an MMC.
[0094]
FIG. 14 is a diagram showing a third embodiment of a memory device 1401 to which the present invention is applied. The memory device 1401 has an MMC interface 1407 as an interface with the host 1408. Note that the memory device 1401 of the present embodiment has a card shape, but the shape is not limited to the shape of the card, and can be handled as a memory device as in the above-described embodiment. Compared with the internal configuration of the memory device 901 shown in FIG. 9, the internal configuration of the memory device 1401 in FIG. 14 is that a command ripper circuit 1405 is added in the MMC interface control unit 1403, and the output thereof is data transfer control. The difference is that it is connected to the unit 1406. Further, the difference is that the SDRAM interface 112 is not connected to the host 1408 but only the MMC interface 1407. Other configurations are the same as in FIG.
[0095]
In the above-described embodiment, an example in which the access to the SDRAM 103 from the hosts 111 and 906 is performed via the SDRAM interface 112, but in the configuration of the present embodiment, the access to the SDRAM 103 is also performed via the MMC interface 1407. Done. That is, the memory device 1401 issues a command for instructing data transfer between the flash memory 102 and the SDRAM 103 via the MMC interface 1407 in addition to the function as the MMC, and accesses the SDRAM 103 from the MMC interface 1407. Can be done. As an example for realizing the above-described access, for example, it is conceivable to encapsulate a data write or read command to the SDRAM 103 in the command data area using a newly defined MMC command and issue it to the MMC 1401. In this case, a command requesting access to the SDRAM 103 is detected by the command control circuit 1404 of the MMC interface control unit 1403, access request information is extracted by the command ripper circuit 1405, and the command decoder 601 ( As shown in FIG. 6, the memory control unit 1402 can access the SDRAM 103 as in the above-described embodiment.
[0096]
As described above, by using only the MMC interface 1407, not only functions as an MMC but also high-speed volatile and non-volatile memory can be used.
[0097]
Note that the memory device 101, 901, 1301, or 1401 described in the present invention can be applied to any shape. For example, an LSI in which each memory chip and control chip are housed in one package may be used, or all functions may be housed in one semiconductor chip. Further, it may be stored in the shape of a memory card such as the MMC described above. Furthermore, the types of the nonvolatile memory and the volatile memory shown in the present invention are not limited to the flash memory 102 and the SDRAM 103, respectively. For example, in the case of a nonvolatile memory, a ferroelectric memory, an MRAM (magnetic memory), etc. Similar processing is possible.
[0098]
Next, details of the non-volatile area management method on the SDRAM 103 of the present invention will be described. FIG. 15 is a diagram illustrating a configuration of the nonvolatile area of the SDRAM 103 and a correspondence relationship between the nonvolatile area of the SDRAM 103 and the storage area of the flash memory 102.
[0099]
As shown in the figure, the non-volatile area of the SDRAM 103 is managed by being divided into an area SA1501, an area SB1502, an area SC1503, an area SD1504, and an area SE1505 according to use. Each area is associated with an area FA1510, an area FB1511, an area FC1512, an area FD1513, an area FE1 (1514), and an area FE2 (1515) on the flash memory 102. The area on the SDRAM 103 and the area on the flash memory 102 do not have to be one-to-one, and the area SE1505 may be associated with the area FE1 (1514) and the area FE2 (1515). Note that the area may be further divided and managed.
[0100]
Area management is performed by preparing the area management table 1601 in the address mapping table 603 and managing the data transfer control unit 105 based on the information. Note that the area management table 1601 may be prepared on another recording apparatus. FIG. 16 is a diagram showing a specific example of the area management table 1601. The area management table 1601 manages attribute information of each area when areas are sequentially allocated from the head of the flash memory 102. For example, if the nonvolatile area of the SDRAM has an area configuration as shown in FIG. 15, the attributes of each area are assigned to the area management table 1601 as shown in FIG. By setting an attribute in each area, it is possible to set characteristics such as an access method according to the usage conditions of the host 111.
[0101]
In FIG. 16, the value p of OFFSET ADDRESS is set to the maximum number of areas that can be allocated. Each area in which area information in the area management table 1601 is not saved is managed by the data transfer control unit 105 to be used as a spare area 1607 at the next area allocation.
[0102]
FIG. 17 is an example of the region attribute information described in FIG.
[0103]
The start address 1702 of the SDRAM area designates the start address of the SDRAM area. The start address 1703 of the flash area designates the start address of the flash memory area corresponding to the start address 1702 of the SDRAM area. The SDRAM area size 1704 specifies the size of the SDRAM area. The update count 1705 records how many times the data on the SDRAM 103 has been updated by the host 111 after the data is transferred from the flash memory 102 to the SDRAM 103. When data is written from the SDRAM 103 to the flash memory 102, it is cleared to zero. When the update count threshold 1706 is designated as 0, data is written to the flash memory 102 every time the SDRAM area is updated. When a value of 1 or more is designated, data is not written to the flash memory 102 until the SDRAM area is updated the designated number of times. In the play race 1707, when 0 is designated, even if the SDRAM 103 is updated, the data in the corresponding flash memory area is not deleted. When 1 is specified, the data on the corresponding flash memory area is deleted. When 0 is specified as the data replication number 1708, data on the SDRAM 103 is not replicated. When 1 or more is designated, the designated number of data on the SDRAM 103 is duplicated and the data is written to the flash memory 102. The wear leveling number 1709 is a parameter that controls a process called wear leveling that changes the writing position each time data is written from the SDRAM 103 to the flash memory 102. When 0 is specified, wear leveling is not performed when data is written from the SDRAM 103 to the flash memory 102. When a value of 1 or more is specified, a specified number of wear levels are performed when data is written from the SDRAM 103 to the flash memory 102. For example, when 1 is designated, twice the SDRAM area is prepared in the flash memory 102 as in the area SE and the areas FE1 (1514) and FE2 (1515) in FIG. When data is written to 102, data is alternately written to the area FE1 (1514) and the area FE2 (1515). The wear leveling value 1710 is a wear leveling value necessary for calculating a position to be written next when wear leveling is valid. When the value becomes equal to the wear leveling number 1709, it is cleared to zero. The user-defined attribute 1711 is a user-defined attribute value for each area that can be set by the host 111.
[0104]
FIG. 18 is a flowchart showing a procedure of area setting data setting processing and initialization processing when the memory device 101 is activated. When the memory device 101 is activated, the memory control unit 104, the SDRAM 103, and the flash memory 102 are initialized (1801). When the initialization is completed, the memory control unit 104 issues an area setting data read instruction to the flash memory 102 (1802). The flash memory 102 transmits the area setting data to the memory control unit 104 (1804). The memory control unit 104 stores the area setting data in the data buffer 108 (1803). Next, the memory control unit 104 instructs the initial data to be transferred from the flash memory 102 to the SDRAM 103 based on the area setting information, and the data is transferred (1805). Details of the data read process will be described later. The decryption memory device 101 repeats the data read process until all necessary data is read (1806). When the data transfer ends, the memory device 101 reports the end of initialization of the device itself to the host 111 (1807). Thereafter, the host 111 and the memory device 101 start normal operation (1808).
[0105]
FIG. 19 is a flowchart showing a procedure when the host 111 updates the area data. The host 111 writes the area setting data to the memory device 101 (1901). The memory control unit 104 writes this data into the data buffer 108 and updates the data (1902). Thereafter, the memory control unit 104 writes the area setting data in the area setting data recording area of the flash memory 102 (1903, 1904).
[0106]
FIG. 20 is a flowchart showing a processing procedure when the host 111 writes data to the memory device 101.
[0107]
The host 111 writes data to the memory device 101 (2001). At this time, the memory control unit 104 detects the access address of the host 111 (2002). The data written by the host 111 is recorded in the SDRAM 103 (2003). The memory control unit 104 checks the access area of the host 111 from the detected access address, and refers to the area attribute on the area management table 1601 (2004). Thereafter, the memory control unit 104 adds 1 to the region attribute update count value 1705 (2005). When the update count value 1705 is equal to or greater than the update count threshold 1706, the memory control unit 104 instructs execution of data write processing (2007) from the SDRAM 103 to the flash memory 102, and then clears the update count value 1705 (2008). If the update count 1705 does not satisfy the update count threshold 1706, the memory control unit 104 determines the validity of the play race 1707 (2009). If the play race 1707 is valid, the memory control unit 104 instructs the flash memory 102 about an area to be erased (2010). The flash memory 102 erases the designated area (2011). If the play race 1707 is invalid, the memory control unit 104 ends the process.
[0108]
FIG. 21 is a flowchart showing detailed processing of the data write processing 2007.
[0109]
The memory control unit 104 determines whether wear leveling is valid (2101). If valid, the memory control unit 104 adds 1 to the wear leveling value (2102). When the wear leveling value 1710 is equal to or greater than the wear leveling number 1709, the memory control unit 104 clears the wear leveling value 1710 (2103, 2104). Next, the memory control unit 104 instructs data transfer from the SDRAM 103 to the flash memory 102 to the area indicated by the wear leveling value (2105), and ends the processing after the data transfer ends (2110). If the wear leveling is invalid, the memory control unit 104 determines the number of data replication (2106). If the number of replicas is 1 or more, the memory control unit 104 instructs the designated number of replicated data transfers from the SDRAM 103 to the flash memory 102 (2108), and the SDRAM 103 and the flash memory 102 perform data transfer from the SDRAM 103 to the flash memory 102 ( 2107). Next, the memory control unit 104 instructs the SDRAM 103 and the flash memory 102 to write data (2109), and the SDRAM 103 and the flash memory 102 perform normal data write (2110).
[0110]
FIG. 22 is a flowchart showing processing when the operation of the memory device 101 is finished.
[0111]
The host 111 issues a memory operation stop instruction (2201). The memory device 101 writes all data to be saved among unsaved data on the SDRAM 103 to the flash memory 102 (2007). When writing to the flash memory 102 of all areas to be stored on the SDRAM 103 is completed (2202), the memory device 101 issues a data storage completion report 2203 to the host 111. Thereafter, the host 111 performs a memory stop process (2204).
[0112]
FIG. 23 is a flowchart showing detailed processing at the time of data transfer from the flash memory 102 to the SDRAM 103.
[0113]
The memory control unit 104 determines wear leveling validity of the area where the data read is executed (2300). If wear leveling is valid, the memory control unit 104 instructs to transfer data from the flash memory area indicated by the wear leveling value 1710 to the SDRAM 103, and data transfer is performed (2301, 2303). If wear leveling is invalid, the memory control unit 104 instructs execution of normal data read, and normal data read is performed (2302 and 2303). Note that the ECC control circuit 109 may automatically correct the ECC error of the read data during data transfer. After completion of these processes, the memory control unit 104 performs error determination (2304) of the data read onto the SDRAM 103, and ends the process if no error has occurred. If an error has occurred, the memory control unit 104 determines whether the data replication area is valid (2305). If valid, the memory control unit 104 instructs the SDRAM 103 and the flash memory 102 to read data from the replication area (2306, 2308). Thereafter, the memory control unit 104 performs error determination again (2304), and ends the process if no error has occurred. If an error has occurred, it is determined again whether duplicate data exists (2305). The memory control unit 104 executes this process until there is no duplicate data. If the error does not disappear even if there is no duplicate data, an error process is executed (2307). As an example of error processing, it is conceivable that the alternative sector circuit 110 processes the area as a defective sector, prepares an alternative sector, and notifies the host 111 that an error has occurred.
[0114]
【The invention's effect】
According to the present invention, in a memory device composed of a volatile memory and a nonvolatile memory, a high-speed and nonvolatile memory system can be freely constructed according to the host. That is, a non-volatile area can be freely mapped to a volatile area accessible by the host. Further, it is possible to execute data transfer between the volatile memory and the nonvolatile memory at an arbitrary timing with respect to an arbitrary address range. Furthermore, since the volatile memory and the non-volatile memory can be accessed only in combination with a card interface such as MMC or only with the card interface, the usability can be improved.
[Brief description of the drawings]
FIG. 1 is a diagram showing an internal configuration of a memory device to which the present invention is applied.
FIG. 2 is a diagram showing an address space of an SDRAM and a flash memory to which the present invention is applied.
FIG. 3 is a diagram illustrating an example of a command group to which the present invention is applied.
FIG. 4 is a diagram showing an example of status / error information to which the present invention is applied.
FIG. 5 is a diagram showing a processing flowchart of a host and a memory device to which the present invention is applied.
FIG. 6 is a diagram showing an internal configuration of a data transfer control unit to which the present invention is applied.
FIG. 7 is a diagram showing a state transition of a sequencer to which the present invention is applied.
FIG. 8 is a timing chart of data transfer to which the present invention is applied.
FIG. 9 is a diagram showing an internal configuration of another memory device to which the present invention is applied.
FIG. 10 is a diagram showing a terminal configuration of an MMC interface to which the present invention is applied.
FIG. 11 is a diagram showing a terminal configuration of an SD card interface to which the present invention is applied.
FIG. 12 is a diagram showing a terminal configuration of a memory stick interface to which the present invention is applied.
FIG. 13 is a diagram showing an internal configuration of still another memory device to which the present invention is applied.
FIG. 14 is a diagram showing an internal configuration of still another memory device to which the present invention is applied.
FIG. 15 is a diagram showing an address space of an SDRAM and a flash memory to which the present invention is applied.
FIG. 16 is a diagram showing an address space management table of SDRAM and flash memory to which the present invention is applied;
FIG. 17 is a diagram showing details of an address space management table to which the present invention is applied.
FIG. 18 is a diagram showing a processing flowchart when starting up a host and a memory device to which the present invention is applied;
FIG. 19 is a diagram showing a processing flowchart when updating the address space management table of the host and the memory device to which the present invention is applied;
FIG. 20 is a diagram showing a processing flowchart at the time of host data write of a host and a memory device to which the present invention is applied.
FIG. 21 is a view showing a processing flowchart at the time of flash memory data write in the memory device to which the present invention is applied;
FIG. 22 is a diagram showing a processing flowchart at the end of the operation of the host and the memory device to which the present invention is applied;
FIG. 23 is a view showing a processing flowchart at the time of reading flash data in the memory device to which the present invention is applied;
FIG. 24 is a diagram showing a configuration example of a memory device to which the present invention is applied.
FIG. 25 is a diagram showing an example of a processing flow from the start of power supply to the stop of power supply of the memory device to which the present invention is applied;
FIG. 26 is a diagram showing an example of a processing flow of an SDRAM compatible memory operation of the memory device to which the present invention is applied.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 101, 4000 ... Memory device, 102, 4020 ... Flash memory, 103, 4010 ... SDRAM, 105 ... Data transfer control part, 106 ... Flash memory interface control part, 112, 4001 ... SDRAM interface, 601 ... Command decoder, 602 ... Sequencer, 606 ... Flash-buffer transfer circuit, 607 ... SDRAM-buffer transfer circuit, 903 ... MMC interface control unit, 907 ... MMC interface, 1302 ... MMC control unit, 1304 ... Memory overall control unit, 1305 ... interface Conversion control circuit, 1401... Composite memory card, 1405.

Claims (14)

In a memory device including a DRAM, a flash memory, and a control circuit that controls reading / writing of data from / to the DRAM and reading / writing of data from / to the flash memory from a host,
Means for storing control information used by the control circuit;
The flash memory includes a mirror area in which a part of the storage area in the DRAM is mirrored, and a control storage area for storing the control information set in the means for storing control information used by the control circuit Have
The control circuit is connected to the host by a DRAM compatible interface having electrical characteristics compatible with a terminal group of the DRAM interface, receives a command from the host, and receives the command according to a destination address designated from the host. Is stored in the means for storing the control information used by the control circuit, the content of the command is interpreted by the storage address of the command in the means for storing the control information used by the control circuit, and the command is loaded. Data is transferred from the mirror area in the flash memory to the DRAM when the command is a command indicating, and data is transferred from the DRAM to the mirror area in the flash memory when the command is a command indicating a store. ,
Whether the control circuit is in the middle of processing according to the busy signal indicating whether the memory device is busy and a command from the host, or whether processing according to the command from the host has been completed normally The status information indicating whether or not the processing according to the command from the host could not be executed is stored in the means for storing the control information used by the control circuit, and further the control information used by the control circuit is stored. A memory device for notifying the host of the busy signal or the status information stored in the means.   When the power supply from the host is started, the control circuit transfers the data stored in the mirror area in the flash memory to the DRAM, and the power supply from the host is stopped. The memory device according to claim 1, wherein the data stored in the DRAM is transferred to the mirror area in the flash memory.   When the power supply from the host is started, the control circuit uses the busy signal while the data stored in the mirror area in the flash memory is transferred to the DRAM. The busy signal is set during the transfer of the data stored in the DRAM to the mirror area in the flash memory when power supply from the host is stopped when the control information is stored in the means. 3. The memory device according to claim 2, wherein the memory device is set in a means for storing control information used by the control circuit. Address correspondence information for associating the address of the DRAM and the address of the flash memory,
The memory device according to claim 1, wherein the control circuit changes a correspondence between the address of the DRAM and the address of the flash memory in the address correspondence information.   The control circuit changes the correspondence between the address of the DRAM and the address of the flash memory in the address correspondence information according to the number of times of erasure of the data in the flash memory or the deterioration of the storage area of the data. The memory device according to claim 4. When the power supply from the host is started and the data transferred from the flash memory to the DRAM is a program, the control circuit is configured to store the power in the DRAM when the power supply from the host is stopped. When the data transferred from the flash memory to the DRAM is user data when the power supply from the host is started and the power supply from the host is started, the power supply from the host is stopped. Transferring the user data in the DRAM to the flash memory;
The memory device according to claim 2, wherein the program in the DRAM includes a program that can be used by the host.   The memory device according to claim 1, wherein the control circuit starts data transfer between the DRAM and the flash memory in response to an access command to a predetermined destination address on the DRAM from the host. . The DRAM compatible interface is located between the host and the control circuit, and is a first interface for inputting / outputting commands and data to / from the DRAM.
2. The memory device according to claim 1, further comprising a second interface that is positioned between the host and the control circuit and that inputs and outputs commands and data that are read from and written to the flash memory.   The memory device according to claim 8, wherein the control circuit starts data transfer between the DRAM and the flash memory in response to a command input through the second interface.   The memory device according to claim 1, wherein means for storing control information used by the control circuit is arranged in the control circuit.   2. The memory device according to claim 1, wherein means for storing control information used by the control circuit is allocated in a storage area of the DRAM.   The memory device according to claim 1, further comprising a holding circuit that holds transfer data between the DRAM and the flash memory. The flash memory includes a defective sector area, an alternate sector area for replacing a defective sector region that may occur future,
Wherein the control circuit, the when read and write target data to the flash memory is the defective sector area, the memory device according to claim 1 having a means for accessing said alternate sector area instead. The control circuit is connected to the DRAM by a DRAM interface, and when the command from the host is a command other than data read / write, or when the destination address designated by the host indicates the DRAM A command to pass through the DRAM interface to the DRAM interface, the command from the host is a command indicating data read / write, and a destination address designated by the host stores control information used by the control circuit; The data from the host is written to the means for storing the control information used by the control circuit, or the busy signal or the status information in the means for storing the control information used by the control circuit is sent to the host. The memory device according to claim 1, which is notified.

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