JP3912395B2 - Semiconductor integrated circuit, inspection apparatus, and semiconductor integrated circuit inspection method - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit, an inspection apparatus, and an inspection method for a semiconductor integrated circuit, and is particularly suitable for application to an ASIC (Application Specific Integrated Circuit) inspection method.

  As a conventional method for inspecting a semiconductor integrated circuit, there is a method of testing an IC chip mounted on a circuit board by using a JTAG (Joint Test Action Group) test port. This JTAG standard is defined by IEEE 1149.1, “IEEE Standard Test Access Port and Boundary-Scan Architecture”. This JTAG test port has a function of outputting information of internal registers and input / output buses to the outside.

Further, for example, in Patent Document 1, in order to perform inspection without supplying driving power to a circuit or a substrate, an inspection circuit is incorporated in an integrated circuit, and electromagnetic waves emitted from a power feeding / transmitting / receiving antenna of the inspection apparatus are detected. A method for receiving drive power at a power reception unit and generating drive power for an inspection circuit is disclosed. Similarly, the inspection control procedure from the inspection apparatus is received in a non-contact manner, and the control logic controls the analog SW, the D / A circuit, and the A / D circuit according to the received control procedure to control the circuit via the inspection wiring. It is also possible to perform inspection and transmit the inspection result to the inspection apparatus via the encoder and the transmission unit.
JP 2003-57300 A

However, in the JTAG test port, information is exchanged by serial communication of about 10 Mbps. For this reason, the JTAG standard has a problem that a sufficient amount of information cannot be handled to monitor information of registers and buses connected to a CPU that is performing multi-bit processing.
Further, if a pin for outputting the internal bus signal to the outside of the IC package is provided in order to monitor the signal of the internal bus of the ASIC, there is a problem that the package size increases. Furthermore, there is a problem that noise is added to the signal of the internal bus, which may cause malfunction.

Further, in the method disclosed in Patent Document 1, the inspection procedure is received from the outside, the state of the circuit is inspected, and the inspection result is transmitted to the outside, so that inspections other than the predetermined procedure cannot be performed. There was a problem.
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor integrated circuit, an inspection apparatus, and a semiconductor integrated circuit inspection method capable of increasing the amount of information that can be monitored at the time of inspection while allowing an inspection procedure to be specified. It is.

In order to solve the above-described problem, according to a semiconductor integrated circuit according to an aspect of the present invention, a circuit function unit, a bus connected to the circuit function unit, and an information capture register that captures data flowing on the bus And a wireless communication circuit that wirelessly transmits data captured in the information capture register, and a wired communication circuit that transmits additional information associated with wireless communication performed by the wireless communication circuit by wire. And
Thus, the authentication information at the time of wireless communication can be sent by wire while enabling the data flowing on the bus to be taken into the information take-in register and then transmitted to the outside wirelessly. This makes it possible to monitor a large amount of information in real time while ensuring security during wireless communication, and to perform a function test of an ASIC in which circuits having a plurality of functions including a CPU are integrated. At the same time, it is not necessary to provide pins for outputting the signal of the internal bus of the ASIC to the outside of the IC package, and an increase in the package size can be suppressed.

In addition, according to the semiconductor integrated circuit of one embodiment of the present invention, the CPU, the information capture register that captures data stored in the internal register of the CPU, and the data captured in the information capture register are transmitted wirelessly. And a wired communication circuit for transmitting additional information accompanying the wireless communication performed by the wireless communication circuit by wire.
As a result, it is possible to send the authentication information at the time of wireless communication by wire while allowing the internal data of the CPU to be taken into the information take-in register. Therefore, it is possible to monitor the internal data of the CPU while ensuring security during wireless communication.

In addition, according to the semiconductor integrated circuit of one aspect of the present invention, a circuit function unit, a data latch unit provided in the circuit function unit, an information capturing register that captures data latched in the data latch unit, The wireless communication circuit includes: a wireless communication circuit that wirelessly transmits data captured in the information capture register; and a wired communication circuit that transmits additional information associated with wireless communication performed by the wireless communication circuit by wire. .
As a result, the authentication information at the time of wireless communication can be sent by wire while allowing the data of a specific circuit function unit to be directly taken into the information take-in register. For this reason, it is possible to continuously monitor the operation of a specific circuit function unit while ensuring security during wireless communication.

In addition, according to the semiconductor integrated circuit of one aspect of the present invention, the wireless communication circuit includes a control information receiving unit that receives control information that instructs the information capturing register to capture data.
As a result, by designating the data to be monitored from the outside, it becomes possible to fetch only the designated data into the information fetch register, and it is possible to efficiently perform the function test of the ASIC in which circuits having a plurality of functions including the CPU are integrated. It can be done well.

Further, according to the semiconductor integrated circuit of one aspect of the present invention, the additional information is an encryption key, and the wireless communication circuit encrypts the data captured in the information capture register with the encryption key. It transmits by radio | wireless.
Thereby, the encryption key can be transmitted to the outside by wired communication while the data captured in the information capturing register can be transmitted to the outside wirelessly. For this reason, it is possible to monitor a large amount of information in real time while preventing the encryption key from being read by others and further improving security during wireless communication.

According to the inspection apparatus of one aspect of the present invention, the wireless communication unit that performs wireless communication with the semiconductor integrated circuit, the wired communication unit that performs wired communication with the semiconductor integrated circuit, and the wireless communication unit receive the wireless communication unit. Further, based on data flowing on the bus of the semiconductor integrated circuit or data stored in an internal register, and additional information received by the wired communication unit and attached to the data received by the wireless communication unit And an inspection unit for inspecting the semiconductor integrated circuit.
As a result, data flowing on the bus of the semiconductor integrated circuit or data stored in the internal register can be taken into the inspection device wirelessly, and authentication information at the time of wireless communication can be taken into the inspection device by wire. . For this reason, it is possible to perform a function test of an ASIC in which circuits having a plurality of functions including a CPU are integrated while ensuring security during wireless communication.
Moreover, according to the inspection apparatus according to an aspect of the present invention, the additional information is an encryption key, and the wireless communication unit receives the data received by the wireless communication unit, and receives the data received by the wired communication unit. It is characterized by decrypting with an encryption key.
As a result, the data flowing on the bus of the semiconductor integrated circuit or the data stored in the internal register can be taken into the inspection device by wireless communication, and the encryption key can be taken into the inspection device by wired communication. For this reason, it is possible to perform a function test of an ASIC in which circuits having a plurality of functions including a CPU are integrated while preventing an encryption key from being read by another person and further improving security during wireless communication.

  According to the semiconductor integrated circuit inspection method of one aspect of the present invention, the step of transmitting the control information instructing the data capture to the information capture register and the bus on the semiconductor integrated circuit based on the control information The step of causing the information fetching register to fetch the data flowing through the step, the step of causing the data fetched to the information fetching register to be transmitted wirelessly, and the step of transmitting the additional information associated with the wirelessly transmitted data by wire. It is characterized by providing.

As a result, it is possible to transmit authentication information at the time of wireless communication to the outside while allowing specified data to be captured in the information capture register and then transmitted to the outside wirelessly. Therefore, it is possible to monitor a large amount of information efficiently in real time while ensuring security during wireless communication, and it is possible to perform a function test of an ASIC in which circuits having a plurality of functions including a CPU are integrated. In addition, it is not necessary to provide a pin for outputting the signal of the internal bus of the ASIC outside the IC package, and an increase in the package size can be suppressed.
According to the method for inspecting a semiconductor integrated circuit according to one aspect of the present invention, the additional information is an encryption key, and the step of causing the data fetched to the information fetch register to be transmitted wirelessly is the information fetch register. The captured data is encrypted with the encryption key and then transmitted wirelessly.
As a result, it is possible to transmit the encryption key to the outside by wired communication while allowing the designated data to be captured by the information capturing register and then transmitted to the outside by wireless communication. For this reason, it is possible to efficiently monitor a large amount of information in real time while preventing the encryption key from being read by others and further enhancing security during wireless communication, and a circuit having a plurality of functions including a CPU is integrated. It is possible to perform a function test of the ASIC, and it is not necessary to provide a pin for outputting the signal of the internal bus of the ASIC outside the IC package, so that an increase in the package size can be suppressed.

Hereinafter, a semiconductor integrated circuit and an inspection method thereof according to embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a schematic configuration of a semiconductor integrated circuit according to the first embodiment of the present invention.
In FIG. 1, a CPU 104, a memory 105, logic circuits 106 and 108, a control circuit 107, and a buffer circuit 109 are connected to each other via a bus 111. The bus 111 is connected to an information capture register 103 that captures data flowing on the bus 111, and the information capture register 103 is connected to a wireless communication circuit 102 that wirelessly transmits the data captured in the information capture register 103. Has been. Here, the wireless communication circuit 102 is provided with an antenna 101 that transmits and receives radio waves. The buffer circuit 109 is provided with an external interface 110.

  Note that the CPU 104, the memory 105, the logic circuits 106 and 108, the control circuit 107, and the buffer circuit 109 can be components of circuit function units in the ASIC. The CPU 104, the memory 105, the logic circuits 106 and 108, the control circuit 107, the buffer circuit 109, the antenna 101, the wireless communication circuit 102, and the information capture register 103 can be mounted on the same semiconductor chip.

  When the data flowing on the bus 111 is captured by the information capture register 103, the wireless communication circuit 102 transmits the data captured by the information capture register 103 to the outside via the antenna 101. It should be noted that the JTAG technique can be followed for data fetching into the information fetching register 103 and data dumping from the wireless communication circuit 102.

  As a result, a large amount of data flowing on the bus 111 can be monitored in real time, a function test of an ASIC in which circuits having a plurality of functions including the CPU 104 are integrated can be performed, and the inside of the ASIC It is not necessary to provide a pin for outputting the signal of the bus 111 outside the IC package, and an increase in the package size can be suppressed.

In addition, since the data flowing on the bus 111 is transmitted wirelessly, it is not necessary to probe the data line. Therefore, it is possible to prevent the waveform from being distorted due to the parasitic capacitance of the probe and cause the semiconductor integrated circuit to malfunction, and the semiconductor integrated circuit can be inspected stably.
Note that the wireless communication circuit 102 may receive control information that instructs the information capture register 103 to capture data, and transmit only specified data to the outside. For example, the user selects data output to the wireless communication circuit 102 such as “data accessed the logic circuit 106”, and the information capture register 103 decodes the data on the bus 111 and selects the selected data. It may be possible to take out only.

In addition, the wireless communication circuit 102 can perform broadband short-range wireless communication such as UWB (Ultra Wide Band), and can secure an information transmission speed of about several hundred Mbps. Therefore, high-speed data flowing on the internal bus 111 of the ASIC can be monitored in real time.
FIG. 2 is a block diagram showing a schematic configuration of the wireless communication circuit 102 of FIG.

  In FIG. 2, when data is received by the wireless communication circuit 102, the transmission / reception switching circuit 201 switches the connection with the antenna 101 to the amplifier 202 side. The received signal received via the antenna 101 is amplified by the amplifier 202, and then the unwanted wave interference wave is removed by the band pass filter 203 and input to the synchronization circuit 204. The synchronization circuit 204 detects a preamble in the received signal packet and generates a synchronization timing and clock necessary for demodulation in cooperation with the PLL circuit 206. The demodulation circuit 205 receives the received signal and demodulates the received data using the output of the synchronization circuit 204 or the PLL circuit 206. The logic circuit 207 can cause the information capture register 103 to capture data by generating a clock signal in synchronization with the demodulated reception data and outputting the clock signal to the information capture register 103.

  On the other hand, when the wireless communication circuit 102 transmits data, the transmission / reception switching circuit 201 switches the connection with the antenna 101 to the amplifier 211 side. The parallel-to-serial conversion circuit 208 converts the parallel data output from the information capture register 103 into serial data and outputs the serial data to the modulation circuit 209. The modulation circuit 209 modulates the carrier frequency generated by the PLL circuit 206 with the data received from the parallel-to-serial conversion circuit 208. Then, the modulated signal is transmitted to the antenna 101 via the band pass filter 210 and the amplifier 211 and transmitted to the outside via the antenna 101.

Here, by providing the wireless communication circuit 102 with a bidirectional communication function, a command or the like can be input to the CPU 104 wirelessly. Further, the program written in the memory 105 can be executed by the CPU 104 by writing the program in the memory 105 from outside via wireless.
FIG. 3 is a block diagram showing a schematic configuration of a semiconductor integrated circuit inspection apparatus 350 according to the second embodiment of the present invention.

In FIG. 3, an ASIC 332 is mounted on a circuit board 331. The ASIC 332 includes the antenna 101, the wireless communication circuit 102, and the information capture register 103 shown in FIG.
When the inspection apparatus 350 monitors data in the ASIC 332, the inspection apparatus 350 receives the data transmitted from the ASIC 332 through the antenna 300. The received signal received via the antenna 300 is amplified by the amplifier 302, and then the unwanted wave interference wave is removed by the band pass filter 303 and input to the synchronization circuit 304. The synchronization circuit 304 detects a preamble in the received signal and generates a synchronization timing and clock necessary for demodulation in cooperation with the PLL circuit 306. Demodulation circuit 305 receives the received signal, uses the output of synchronization circuit 304 or PLL circuit 306, demodulates the received signal, and then outputs demodulated data to serial-to-parallel conversion circuit 308. The serial-parallel conversion circuit 308 outputs the data subjected to serial-parallel conversion to the processing circuit 321. The logic circuit 307 generates a clock signal in synchronization with the reception data demodulated by the demodulation circuit 305 and outputs the clock signal to the processing circuit 321. When the processing circuit 321 receives the serial-parallel converted data from the serial-parallel conversion circuit 308, the processing circuit 321 can display the data on the display unit 322 in real time in accordance with the timing output from the logic circuit 307.

FIG. 4 is a block diagram showing a schematic configuration of a semiconductor integrated circuit inspection apparatus 450 according to the third embodiment of the present invention.
In FIG. 4, an ASIC 432 is mounted on a circuit board 431. Note that the ASIC 432 incorporates the antenna 101, the wireless communication circuit 102, and the information capture register 103 shown in FIG.

  When the inspection apparatus 450 performs external control of the ASIC 432, the transmission / reception switching circuit 401 switches the connection with the antenna 400 to the amplifier 411 side. Then, when a data capture instruction is given by the operation unit 423, the processing circuit 421 generates control information instructing data capture and transmits the control information to the logic circuit 407. When the logic circuit 407 receives control information from the processing circuit 421, the logic circuit 407 generates a packet for wireless transmission and outputs the packet to the modulation circuit 409. The modulation circuit 409 modulates the data received from the logic circuit 407 with the carrier frequency generated by the PLL circuit 406. Then, the modulated signal is transmitted to the antenna 400 via the band pass filter 410 and the amplifier 411 and transmitted to the outside via the antenna 400.

  On the other hand, when monitoring data in the ASIC 432, the inspection device 450 receives the signal transmitted from the ASIC 432 by the antenna 400. Then, the received signal received via the antenna 400 is amplified by the amplifier 402, and then the interference wave in the unnecessary band is removed by the band pass filter 403 and input to the synchronization circuit 404. The synchronization circuit 404 detects a preamble in the received signal and generates a synchronization timing and clock necessary for demodulation in cooperation with the PLL circuit 406. The demodulation circuit 405 receives the received signal, uses the output of the synchronization circuit 404 and the PLL circuit 406, demodulates the received data, and outputs the demodulated data to the serial-to-parallel conversion circuit 408. The serial-parallel conversion circuit 408 outputs the data subjected to the serial-parallel conversion to the processing circuit 421. In addition, the logic circuit 407 generates a clock signal in synchronization with the reception data demodulated by the demodulation circuit 405 and outputs the clock signal to the processing circuit 421. When the processing circuit 421 receives the serial-parallel converted data from the serial-parallel conversion circuit 408, the processing circuit 421 can display the data on the display unit 422 in real time in accordance with the timing output from the logic circuit 407.

Note that the semiconductor integrated circuit inspection method described above may be used to confirm whether the semiconductor integrated circuit has been manufactured normally, or may be used for quality inspection of the semiconductor integrated circuit. Alternatively, when developing a semiconductor integrated circuit, it can also be used to confirm whether each circuit function unit constituting the ASIC is correctly designed.
In the above-described embodiment, the method for inspecting the ASIC mounted on the circuit board has been described. However, the ASIC may be inspected after the ASIC is accommodated in the housing.

FIG. 5 is a block diagram showing a schematic configuration of a semiconductor integrated circuit according to the fourth embodiment of the present invention.
In FIG. 5, a CPU 504, a memory 505, logic circuits 506 and 508, a control circuit 507, and a buffer circuit 509 are connected to each other via a bus 511. The CPU 504 is connected to an information capture register 503 that captures data stored in an internal register of the CPU 504, and the information capture register 503 wirelessly transmits the data captured in the information capture register 503. Is connected. Here, the wireless communication circuit 502 is provided with an antenna 501 that transmits and receives radio waves. The buffer circuit 509 is provided with an external interface 510.

When the data stored in the internal register of the CPU 504 is captured by the information capture register 503, the wireless communication circuit 502 transmits the data captured by the information capture register 503 to the outside via the antenna 501.
As a result, internal data (such as instruction cache) of the CPU 504 can be taken into the information take-in register 503, and the internal data of the CPU 504 can be monitored. Therefore, data that cannot be accessed from the bus 511 can be monitored, and the inspection accuracy can be improved.

FIG. 6 is a block diagram showing a schematic configuration of a semiconductor integrated circuit according to the fifth embodiment of the present invention.
In FIG. 6, a CPU 604, logic circuits 606 and 608, a control circuit 607 and a buffer circuit 609 are connected to each other via a bus 611. Further, the memory 605 is provided with a data latch circuit 612 that latches data stored in the memory 605, and the data latch circuit 612 is connected to the bus 611. The data latch circuit 612 is connected to an information capture register 603 that captures the data latched by the data latch circuit 612. The information capture register 603 wirelessly transmits the data captured by the information capture register 603 wirelessly. A communication circuit 602 is connected. Here, the wireless communication circuit 602 is provided with an antenna 601 that transmits and receives radio waves. The buffer circuit 609 is provided with an external interface 610.

When the data latched by the data latch circuit 612 is captured by the information capture register 603, the wireless communication circuit 602 transmits the data captured by the information capture register 603 to the outside via the antenna 601.
As a result, the data stored in the memory 605 can be directly taken into the information take-in register 603, and the operation of the memory 605 can be continuously monitored.

FIG. 7 is a block diagram showing a schematic configuration of a semiconductor integrated circuit according to the sixth embodiment of the present invention.
In FIG. 7, a CPU 704, a memory 705, logic circuits 706 and 708, a control circuit 707 and a buffer circuit 709 are connected to each other via a bus 711. The information capture register 703 that captures data flowing on the bus 711 is connected to the bus 711, and the wireless communication circuit 702 that wirelessly transmits the data captured in the information capture register 703 is connected to the information capture register 703. Has been. Here, the wireless communication circuit 702 is provided with an antenna 701 that transmits and receives radio waves. The buffer circuit 709 is provided with an external interface 710. In addition, the wireless communication circuit 702 is connected to the external interface 710 via a wire 712. Here, additional information associated with wireless communication performed by the wireless communication circuit 702 can be transmitted to the wireless communication circuit 702 by wire. Examples of the additional information include an encryption key and authentication information.

  When the semiconductor integrated circuit is inspected, for example, the encryption key can be sent to the wireless communication circuit 702 via the wire 712. When the data flowing on the bus 711 is captured by the information capture register 703, the wireless communication circuit 702 encrypts the data captured by the information capture register 703 using an encryption key and transmits the data to the outside via the antenna 701. To do.

As a result, the encryption key can be sent to the wireless communication circuit 702 via the wire 712, and the encryption key can be prevented from being read by others. For this reason, it is possible to monitor a large amount of information in real time while ensuring security during wireless communication.
In the above-described embodiment, the method of providing only one antenna in the semiconductor integrated circuit has been described. However, two antennas may be provided in the semiconductor integrated circuit so that transmission and reception can be performed simultaneously.

1 is a block diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. FIG. 2 is a block diagram showing a schematic configuration of a wireless communication circuit 102 in FIG. 1. The block diagram which shows the structure of the test | inspection apparatus of the semiconductor integrated circuit which concerns on 2nd Embodiment. The block diagram which shows the structure of the test | inspection apparatus of the semiconductor integrated circuit which concerns on 3rd Embodiment. The block diagram which shows the structure of the semiconductor integrated circuit which concerns on 4th Embodiment of this invention. The block diagram which shows the structure of the semiconductor integrated circuit which concerns on 5th Embodiment of this invention. The block diagram which shows the structure of the semiconductor integrated circuit which concerns on 6th Embodiment of this invention.

Explanation of symbols

  101, 300, 501, 601, 701 Antenna, 102, 502, 602, 702 Wireless communication circuit, 103, 503, 603, 703 Information capture register, 104, 504, 604, 704 CPU, 105, 505, 605, 705 Memory 106, 108, 207, 307, 407, 506, 508, 606, 608, 706, 708 Logic circuit, 107, 507, 607, 707 Control circuit, 109, 509, 609, 709 Buffer circuit, 110, 510, 610 , 710 interface, 111, 511, 611, 711 bus, 201, 401 transmission / reception switching circuit, 202, 211, 302, 402, 411 amplifier, 203, 210, 303, 403, 410 band pass filter, 204, 304, 404 Synchronous circuit, 205, 305, 405 Demodulator circuit, 206, 306, 406 PLL circuit, 208 Parallel-to-serial converter circuit, 209, 409 Modulator circuit, 308, 408 Serial-to-parallel converter circuit, 331, 431 Circuit board, 332, 432 ASIC, 321, 421 Processing circuit, 322, 422 Display unit, 350, 450 Inspection device, 423 Operation unit, 612 Data latch circuit, 712 Wired

Claims (6)

A circuit function unit;
A bus connected to the circuit function unit;
An information capture register for capturing data flowing on the bus;
A wireless communication circuit for wirelessly transmitting data captured in the information capture register;
A wired communication circuit for transmitting additional information accompanying the wireless communication performed by the wireless communication circuit by wire,
The additional information is an encryption key;
The semiconductor communication circuit, wherein the wireless communication circuit wirelessly transmits data captured in the information capture register after being encrypted with the encryption key. CPU,
An information capture register for capturing data stored in an internal register of the CPU;
A wireless communication circuit for wirelessly transmitting data captured in the information capture register;
A wired communication circuit for transmitting additional information accompanying the wireless communication performed by the wireless communication circuit by wire,
The additional information is an encryption key;
The semiconductor communication circuit, wherein the wireless communication circuit wirelessly transmits data captured in the information capture register after being encrypted with the encryption key. A circuit function unit;
A data latch section provided in the circuit function section;
An information fetch register for fetching data latched in the data latch unit;
A wireless communication circuit for wirelessly transmitting data captured in the information capture register;
A wired communication circuit for transmitting additional information accompanying the wireless communication performed by the wireless communication circuit by wire,
The additional information is an encryption key;
The semiconductor communication circuit, wherein the wireless communication circuit wirelessly transmits data captured in the information capture register after being encrypted with the encryption key.   4. The semiconductor integrated circuit according to claim 1, wherein the wireless communication circuit includes a control information receiving unit that receives control information that instructs the information capturing register to capture data. 5. A wireless communication unit for performing wireless communication with a semiconductor integrated circuit;
A wired communication unit for performing wired communication with the semiconductor integrated circuit;
Data received on the bus of the semiconductor integrated circuit received by the wireless communication unit or data stored in an internal register, and data received by the wireless communication unit received by the wired communication unit And an inspection unit for inspecting the semiconductor integrated circuit based on the additional information accompanying the
The additional information is an encryption key;
The wireless communication unit decrypts the data received by the wireless communication unit with the encryption key received by the wired communication unit. Transmitting control information instructing data capture to the information capture register;
Based on the control information, the step of causing the information capture register to capture data flowing on the bus of the semiconductor integrated circuit;
Wirelessly transmitting data captured in the information capture register;
Additional information accompanying the wirelessly transmitted data is transmitted by wire,
The additional information is an encryption key;
The step of wirelessly transmitting the data captured in the information capture register includes encrypting the data captured in the information capture register with the encryption key and then transmitting the data wirelessly. Inspection method.

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