JP4758164B2 - Information processing apparatus, communication circuit, and communication circuit processing method - Google Patents

Description

  The present invention relates to an information processing device, a communication circuit, and a processing method for a communication circuit, and particularly includes two chips, for example, an IC chip that performs processing related to proximity communication and an IC chip that securely stores data. The present invention relates to an information processing apparatus, a communication circuit, and a processing method for a communication circuit that can reduce processing time in an IC card or the like.

  An IC (Integrated Circuit) card system capable of performing proximity communication, which is one of wireless communications, has been rapidly spreading due to its convenience. The IC card system is composed of, for example, an IC card and a reader / writer, and a so-called RF (Radio Frequency) field (magnetic field) is formed by the reader / writer generating electromagnetic waves. When the IC card approaches the reader / writer, the IC card is supplied with power by electromagnetic induction and transmits data to and from the reader / writer. Such an IC card system is used in, for example, an automatic ticket gate system at a station, a system that performs electronic payment using electronic money, and the like.

  In recent years, mobile phones have rapidly spread, and a device in which an IC card and a mobile phone are integrated, that is, a mobile phone having an IC card (function) for performing near field communication has been put into practical use. Note that the mobile phone has the same function as an IC card, but a so-called chip-shaped IC chip is incorporated instead of a card-shaped IC card. Here, for convenience of explanation, a chip-shaped IC chip having the same function as an IC card is also referred to as an IC card.

  Here, the function of the IC card is an RF function for performing near field communication using electromagnetic waves (RF (Radio Frequency)) output by the reader / writer and data processing for securely processing data obtained by the near field communication using the RF function. It can be divided into functions. Now, let us say that the part responsible for the RF function is the RF part and the part responsible for the data processing function is the data processing part. In general, the RF part and the data processing part are composed of a single chip IC ( LSI (Large Scale Integration)) (see, for example, Patent Document 1).

Japanese Patent Laid-Open No. 2003-36427

  By the way, for a one-chip IC including an RF unit and a data processing unit, for example, even if only one of the RF unit and the data processing unit is improved, the RF unit and the data processing unit are separated. It is necessary to remanufacture the entire IC including one chip.

  In addition, the data processing unit includes a nonvolatile memory in order to hold data without a power source, but the nonvolatile memory is generally vulnerable to heat.

  On the other hand, the RF unit emits more heat than the data processing unit because processing such as obtaining power from current obtained by electromagnetic induction by electromagnetic waves output from the reader / writer is performed.

  For this reason, for a one-chip IC including an RF unit and a data processing unit, it is necessary to take measures against heat so that the heat generated by the RF unit does not affect the data processing unit (nonvolatile memory).

  Therefore, the RF unit and the data processing unit are configured by separate ICs, and an IC card is realized by using two ICs (chips), that is, an IC configuring the RF unit and an IC configuring the data processing unit. There is a way.

  Hereafter, an IC that constitutes an RF unit that performs proximity communication is referred to as an RF chip, and an IC that constitutes a data processing unit that securely processes data obtained by proximity communication is referred to as an SAM (Secure Application Module). ) Chip.

  By the way, when an IC card is composed of two chips (IC), an RF chip and an SAM chip, the data received by the RF chip is transferred to the SAM chip, and the data stored in the SAM chip is also transferred. In order to transfer to the RF chip and transmit from the RF chip, the RF chip and the SAM chip are connected via a serial interface for data transfer.

  The data transfer from the RF chip to the SAM chip (the same applies to the data transfer from the SAM chip to the RF chip), the data transmitted by the reader / writer from the signal obtained from the electromagnetic wave output from the reader / writer in the RF chip. A data transfer clock having a frequency corresponding to the transmission rate is generated and synchronized with the data transfer clock.

  As described above, in an IC card composed of an RF chip and a SAM chip, data transfer from the RF chip to the SAM chip is performed using a data transfer clock having a frequency corresponding to the transmission rate of data transmitted by the reader / writer. Since the processing is performed synchronously via the serial interface, the processing time of processing performed by the IC card may be long.

  That is, in proximity communication between a reader / writer and an IC card, for example, a packet in which a check code for error detection is arranged at the last position is exchanged.

  In the IC card, if the RF chip performs error detection using the check code of the packet transmitted from the reader / writer, it is included in the packet unless the RF chip receives the end of the packet. Unable to detect errors by obtaining a check code. Therefore, the RF chip receives the packet from the reader / writer to the end, performs error detection using the check code included in the packet, and then transfers the packet to the SAM chip.

  That is, FIG. 1 shows an IC card composed of two chips, an RF chip and a SAM chip, until the RF chip receives a packet transmitted from the reader / writer and transfers the packet to the SAM chip. Shows the time required for.

  As described above, the RF chip receives up to the end of the packet transmitted from the reader / writer, and then performs error detection using the check code included in the packet. When the error detection process ends, the RF chip transfers the packet to the SAM chip.

Therefore, RF chip, the time required for receiving the end of the packet transmitted from the reader-writer and T _11, a time in which the RF chip is required for the processing of the error detection and T _12, the SAM chip from the RF chip Assuming that the time required to transfer a packet is expressed as T ₁₃ , transfer of the packet from the RF chip to the SAM chip is started after starting reception of the packet transmitted from the reader / writer in the RF chip. As shown in FIG. 1, the time required to complete the process is T ₁₁ + T ₁₂ + T ₁₃ .

  Therefore, the RF chip starts receiving packets sent from the reader / writer by transferring the already received packet (data) to the SAM chip while receiving the packet from the reader / writer. It may be possible to shorten the time required for the transfer of the packet from the RF chip to the SAM chip to be completed.

  However, it is expected that reader / writers with different data transmission rates will appear in the future. In the case where reader / writers of various transmission rates can exist, in order to transfer the packets from the RF chip to the SAM chip while receiving the packets from the reader / writer with the RF chip in the IC card, for example, RF The chip needs to be provided with a plurality of blocks that perform processing corresponding to each of the plurality of transmission rates.

  That is, in this case, in a plurality of blocks that perform processing corresponding to each of a plurality of transmission rates, processing is started in parallel when data is transmitted from the reader / writer. Of the plurality of blocks, only data obtained by the block that performs processing corresponding to the data transmission rate from the reader / writer is transferred as valid data from the RF chip to the SAM chip.

  Therefore, as described above, a plurality of blocks that perform processing corresponding to each of a plurality of transmission rates are provided in the RF chip, and processing is performed in parallel in the plurality of blocks, whereby the transmission rate of packets from the reader / writer is determined. In order to enable the RF chip to transfer the data of the already received packet to the SAM chip while receiving the packet from the reader / writer with any of the plurality of transmission rates, A plurality of serial interfaces are required to transfer data obtained in a plurality of blocks that perform processing corresponding to each of a plurality of transmission rates to the SAM chip.

  Therefore, in this case, it is necessary to provide terminals corresponding to a plurality of serial interfaces in the IC as the RF chip and the SAM chip, and the RF chip and the SAM chip are increased in size. Alternatively, there may be cases where it is difficult to provide terminals corresponding to a plurality of serial interfaces due to restrictions on the specifications of the RF chip and the SAM chip.

As a method for shortening the time required from the start of reception of a packet transmitted from the reader / writer in the RF chip to the end of transfer of the packet from the RF chip to the SAM chip, the RF chip can be used. After the reception of the entire packet from the reader / writer is completed, the transfer rate when transferring the packet from the RF chip to the SAM chip is increased (increased), whereby the packet from the RF chip to the SAM chip in FIG. It is conceivable to shorten the time T ₁₃ required for transferring.

  However, if the transfer rate when transferring packets from the RF chip to the SAM chip is increased, the power consumption (current) in the RF chip or SAM chip increases.

  The present invention has been made in view of such a situation, and makes it possible to shorten the processing time.

  An information processing apparatus according to a first aspect of the present invention includes a one-chip communication circuit that performs near field communication and receives a packet including a header code used for detecting a transmission rate and a check code for error detection, and securely A one-chip secure circuit that stores data and performs error detection using a check code included in the packet transferred from the communication circuit, wherein the communication circuit includes the header code included in the packet From the packet, the transmission rate detection means detects the transmission rate of the packet, and immediately after detecting the transmission rate of the packet, starts transmission of the packet to the secure circuit. A corresponding clock is generated, and the security clock is used as a clock to be synchronized with the operation of the secure circuit. Clock generating means for supplying to the circuit, and the secure circuit captures the packet whose transfer is started by the transmission rate detecting means in synchronization with the clock supplied from the clock generating means, Error detection is performed using the included check code.

  A communication circuit according to a second aspect of the present invention is a one-chip communication circuit that performs proximity communication and receives a packet including a header code used for detection of a transmission rate and a check code for error detection. In the communication circuit that transfers the received packet to a one-chip secure circuit that performs error detection using a check code included in the packet transferred from the communication circuit. Transmission rate detection means for detecting the transmission rate of the packet from the header code included in the packet, and immediately starting the transfer of the packet to the secure circuit, after detecting the transmission rate of the packet; To generate a clock corresponding to the transmission rate of the packet, and the secure circuit operates. As a clock to be synchronized, and a clock generating means for supplying to said secure circuit.

  A processing method according to a second aspect of the present invention is a one-chip communication circuit that performs near field communication and receives a packet including a header code used for detection of a transmission rate and a check code for error detection. Processing of the communication circuit that transfers the received packet to a one-chip secure circuit that stores data in the memory and performs error detection using a check code included in the packet transferred from the communication circuit In the method, the transmission rate of the packet is detected from the header code included in the packet, and immediately after the transmission rate of the packet is detected, the transfer of the packet to the secure circuit is started. Generates a clock corresponding to the transmission rate of the packet, and synchronizes the operation of the secure circuit As to the clock, comprising providing to said secure circuit.

  The information processing apparatus according to the first aspect of the present invention, and the communication circuit and processing method according to the second aspect of the present invention perform proximity communication and include a header code used for detecting a transmission rate and a check code for error detection. A one-chip communication circuit that receives a packet securely stores data, and performs error detection using a check code included in the packet transferred from the communication circuit. The received packet is transferred. That is, the communication circuit detects the transmission rate of the packet from the header code included in the packet, and immediately after the transmission rate of the packet is detected, the transfer of the packet to the secure circuit is started. Further, a clock corresponding to the transmission rate of the packet is generated from the packet, and is supplied to the secure circuit as a clock to be synchronized with the operation of the secure circuit.

  According to the present invention, the processing time can be shortened.

  Embodiments of the present invention will be described below. Correspondences between the configuration requirements of the present invention and the embodiments described in the detailed description of the invention are exemplified as follows. This description is to confirm that the embodiments supporting the present invention are described in the detailed description of the invention. Accordingly, although there are embodiments that are described in the detailed description of the invention but are not described here as embodiments corresponding to the constituent elements of the present invention, It does not mean that the embodiment does not correspond to the configuration requirements. Conversely, even if an embodiment is described here as corresponding to a configuration requirement, that means that the embodiment does not correspond to a configuration requirement other than the configuration requirement. Not something to do.

The information processing apparatus according to the first aspect of the present invention provides:
A one-chip communication circuit (for example, the RF chip 11 in FIG. 2) that performs near field communication and receives a packet including a header code used for detection of a transmission rate and an error detection check code;
Information processing comprising: a one-chip secure circuit (for example, the SAM chip 12 in FIG. 2) that securely stores data and performs error detection using a check code included in the packet transferred from the communication circuit Device (for example, IC card 2 in FIG. 2),
The communication circuit includes:
Transmission rate detection means (for example, FIG. 5) detects the transmission rate of the packet from the header code included in the packet, and starts the transfer of the packet to the secure circuit immediately after the detection of the transmission rate of the packet. 4 transmission rate detector 22B),
Clock generation means that generates a clock corresponding to the transmission rate of the packet from the packet and supplies it to the secure circuit as a clock to be synchronized with the operation of the secure circuit (for example, the clock generation unit 22A in FIG. 4) ) And
The secure circuit captures the packet whose transfer is started by the transmission rate detection means in synchronization with the clock supplied from the clock generation means, and performs error detection using a check code included in the packet.

The communication circuit according to the second aspect of the present invention is, firstly,
A one-chip communication circuit (for example, the RF chip 11 in FIG. 2) that performs a near field communication and receives a packet including a header code used for detection of a transmission rate and an error detection check code;
Data is securely stored and received by a one-chip secure circuit (for example, the SAM chip 12 in FIG. 2) that performs error detection using a check code included in the packet transferred from the communication circuit. In the communication circuit for transferring the packet,
Transmission rate detection means (for example, FIG. 5) detects the transmission rate of the packet from the header code included in the packet, and starts the transfer of the packet to the secure circuit immediately after the detection of the transmission rate of the packet. 4 transmission rate detector 22B),
Clock generation means that generates a clock corresponding to the transmission rate of the packet from the packet and supplies it to the secure circuit as a clock to be synchronized with the operation of the secure circuit (for example, the clock generation unit 22A in FIG. 4) ) And.

Secondly, the communication circuit according to the second aspect of the present invention includes:
An error detection unit that detects an error in the packet that can be detected without the check code, and notifies the secure circuit that the error has been detected, thereby stopping the capture of the packet by the secure circuit (for example, The code error detection unit 41) of FIGS. 10 and 13 is further provided.

The processing method according to the second aspect of the present invention includes:
A one-chip communication circuit (for example, the RF chip 11 in FIG. 2) that performs a near field communication and receives a packet including a header code used for detection of a transmission rate and an error detection check code;
Data is securely stored and received by a one-chip secure circuit (for example, the SAM chip 12 in FIG. 2) that performs error detection using a check code included in the packet transferred from the communication circuit. In the processing method of the communication circuit for transferring the packet,
The packet transmission rate is detected from the header code included in the packet, and immediately after the transmission rate of the packet is detected, the packet is started to be transferred to the secure circuit (for example, step of FIG. 5). S4),
A clock corresponding to the transmission rate of the packet is generated from the packet and supplied to the secure circuit as a clock to be synchronized with the operation of the secure circuit (for example, step S1 in FIG. 5).
Includes steps.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 2 shows a configuration example of an embodiment of an IC card system to which the present invention is applied.

  In FIG. 2, the IC card system includes a reader / writer 1 and a (non-contact) IC card 2.

  The reader / writer 1 has an antenna 1 </ b> A and outputs proximity electromagnetic waves from the antenna 1 </ b> A to perform proximity communication with the IC card 2 located in the vicinity of the reader / writer 1.

  The IC card 2 includes an antenna 2A, an RF chip 11, and a SAM chip 12. The RF chip 11 and the SAM chip 12 supply data from the RF chip 11 to the SAM chip 12, and the SAM chip 12 to the RF chip 11 And a data transfer clock from the RF chip 11 to the SAM chip 12 are connected via a serial interface.

  The antenna 2A forms a closed loop coil and receives a signal transmitted from the reader / writer 1. That is, when the antenna 2 </ b> A approaches the reader / writer 1, a current flows through the antenna 1 </ b> A by electromagnetic induction due to electromagnetic waves output from the antenna 1 </ b> A of the reader / writer 1.

  The RF chip 11 is composed of a one-chip IC, performs near field communication, receives a packet transmitted from the reader / writer 1, and supplies it to the SAM chip 12. The RF chip 11 obtains data from the SAM chip 12 and transmits a packet including the data to the reader / writer 1.

  That is, the RF chip 11 demodulates, for example, ASK (Amplitude Shift Keying) the signal received by the antenna 2A (current flowing through the antenna 2A), and converts, for example, Manchester code as demodulated data obtained as a result, 12 is supplied. That is, for example, the reader / writer 1 encodes data into a Manchester code and transmits a signal (electromagnetic wave) obtained by ASK-modulating the carrier using the Manchester code, and the RF chip 11 thus reads the reader / writer. A signal transmitted from 1 is ASK demodulated to obtain a Manchester code, which is supplied to the SAM chip 12.

  Further, the RF chip 11 acquires the Manchester code of data to be transmitted to the reader / writer 1 from the SAM chip 12, and when the antenna 2A of the IC card 2 is viewed from the reader / writer 1 side according to the Manchester code. Data is transmitted to the reader / writer 1 by performing load modulation (modulation of an unmodulated electromagnetic wave (carrier) output from the reader / writer 1) that changes the impedance.

  The RF chip 11 generates a data transfer clock based on data (including a packet) transmitted from the reader / writer 1 and supplies the data transfer clock to the SAM chip 12. Data exchange between the RF chip 11 and the SAM chip 12 is performed in synchronization with the data transfer clock.

  The SAM chip 12 is composed of a one-chip IC and incorporates a nonvolatile memory (not shown). Then, the SAM chip 12 decrypts the Manchester code supplied from the RF chip into the original data, performs other necessary processing, and secures the resulting data, that is, for example, encrypts the nonvolatile data. Store in memory. Further, the SAM chip 12 reads out data stored in the nonvolatile memory, performs necessary processing, further encodes it into a Manchester code, and supplies it to the RF chip 11.

  As described above, the data transfer clock is supplied from the RF chip 11 to the SAM chip 12, and the SAM chip 12 performs processing in synchronization with the data transfer clock from the RF chip 11. I do.

  In the IC card system configured as described above, the reader / writer 1 performs so-called polling by outputting an electromagnetic wave from the antenna 1A.

  Then, when the IC card 2 comes close to the reader / writer 1, a current flows through the antenna 2 </ b> A of the IC card 2 by electromagnetic induction due to electromagnetic waves output from the antenna 1 </ b> A of the reader / writer 1. When a current flows through the antenna 2A, in the IC card 2, a power circuit (not shown) built in the RF chip 11 obtains power from the current flowing through the antenna 2A and supplies it to the necessary blocks constituting the IC card 2. As a result, the IC card 2 becomes operable.

  Thereafter, the RF chip 11 demodulates a signal as a current flowing through the antenna 2A, generates a data transfer clock from the demodulated data obtained as a result, and supplies the data transfer clock to the SAM chip 12 together with the demodulated data. The SAM chip 12 receives the demodulated data from the RF chip 11, performs necessary processing, and stores it.

  Further, the RF chip 11 receives supply of data to be transmitted to the reader / writer 1 from the SAM chip 12 and performs load modulation on the electromagnetic wave (carrier) output from the reader / writer 1 based on the data, thereby obtaining data. Is transmitted to the reader / writer 1.

  In the following, description of data transmission from the IC card 2 (the RF chip 11) to the reader / writer 1 is omitted.

  Next, data is exchanged between the reader / writer 1 and the IC card 2 in units called packets (frames).

  FIG. 3 shows an example of a packet format.

  A packet is configured by sequentially arranging a header code field, a payload field, and a check code field from the beginning.

  For example, a header code including a predetermined pattern is arranged in the header code field. Therefore, for example, if a predetermined pattern can be detected when the header code is sampled with a certain clock, the clock corresponds to the transmission rate of the packet (data), and the frequency of the clock. From this, the transmission rate can be detected. That is, the header code can be used for detection of the transmission rate.

  In the payload field, actual data (including a command) as a payload is arranged (included).

  A check code for error detection is arranged in the check code field. As an error detection method, for example, CRC (Cyclic Redundancy Checking) or checksum can be adopted.

  When such a packet is transmitted from the reader / writer 1 to the IC card 2, in the IC card 2, the RF chip 11 detects the transmission rate of the packet from the header code included in the packet, and the transmission rate. Is generated and supplied to the SAM chip 12 as a clock to be synchronized with the operation of the SAM chip 12.

  Further, the RF chip 11 starts transferring the packet to the SAM chip 12 immediately after detecting the packet transmission rate. That is, the RF chip 11 starts transferring the packet to the SAM chip 12 before receiving the check code arranged at the end of the packet. Here, the packet transfer from the RF chip 11 to the SAM chip 12 is performed in synchronization with the data transfer clock.

  Even when the RF chip 11 receives the check code, the RF chip 11 does not perform error detection using the check code.

  On the other hand, when the supply of the data transfer clock and the packet is started from the RF chip 11, the SAM chip 12 starts to take in (receive) the packet in synchronization with the data transfer clock. When the SAM chip 12 receives up to the end of the packet, the SAM chip 12 performs error detection using a check code arranged at the end of the packet. The SAM chip 12 discards a packet, for example, when an error is detected by error detection using a check code, and processes data (payload) included in the packet when an error is not detected.

  Next, FIG. 4 shows a configuration example of the RF chip 11 of FIG. In FIG. 4 (the same applies to FIGS. 10 and 13 to be described later), the part related to the reception of the packet from the reader / writer 1 is shown, and the part related to the transmission of the packet to the reader / writer 1 is shown. It is omitted.

  In FIG. 4, the RF chip 11 includes a demodulator 21, a clock processor 22, and a data buffer 23.

  The demodulator 21 detects the current flowing through the antenna 2 </ b> A, that is, performs ASK demodulation, and supplies a packet as demodulated data obtained as a result to the clock processor 22.

  The clock processing unit 22 includes a clock generation unit 22A and a transmission rate detection unit 22B. Based on the demodulated data (packets) supplied from the demodulation unit 21, the clock processing unit 22 generates a data transfer clock and transmits the transmission rate. In addition to performing detection, the demodulated data supplied from the demodulator 21 is sequentially supplied to the data buffer 23.

  That is, the clock generation unit 22A includes, for example, a PLL (Phase Lock Loop) circuit (not shown), and generates a data transfer clock based on the demodulated data supplied from the demodulation unit 21 by the PLL circuit. Output.

  The transmission rate detector 22B samples the demodulated data supplied from the demodulator 21 at the timing of the data transfer clock output from the clock generator 22A, and detects the header code of the packet as the demodulated data. Detect the modulation data transmission rate. When the transmission rate is detected by the transmission rate detection unit 22B, in the clock generation unit 22A, the built-in PLL circuit compares the demodulated data supplied from the demodulation unit 21 and the data transfer clock output from the PLL circuit. According to the phase difference, the phase of a clock having a frequency corresponding to the transmission rate detected by the transmission rate detection unit 22B is adjusted, and the clock after the phase adjustment is output as a data transfer clock. That is, in the clock generation unit 22A (PLL circuit thereof), after the transmission rate is detected by the transmission rate detection unit 22B, a data transfer clock having a frequency corresponding to the transmission rate is output.

  Further, when the transmission rate detection unit 22B detects the transmission rate of the modulated data, the transmission rate detection unit 22B controls the data buffer 23 to transfer the demodulated data stored in the data buffer 23 to the SAM chip 12.

  The data buffer 23 sequentially stores the demodulated data supplied from the clock processing unit 22. Further, the data buffer 23 reads the stored demodulated data by a so-called FIFO (First In First Out) method and transfers it to the SAM chip 12 under the control of the transmission rate detection unit 22B.

  Next, the operation when the RF chip 11 of FIG. 4 receives a signal (packet) from the reader / writer 1 will be described with reference to the flowchart of FIG.

  When a signal is transmitted from the reader / writer 1, the demodulator 21 of the RF chip 11 sequentially demodulates the signal from the reader / writer 1, and sequentially supplies the demodulated data obtained as a result to the clock processor 22.

  When the supply of the demodulated data from the demodulator 21 is started, the clock processing unit 22 starts to supply the demodulated data to the data buffer 23, so that the data buffer 23 is supplied from the demodulator 21. The demodulated data is temporarily stored.

  Furthermore, in the clock processing unit 22, the clock generation unit 22A starts generating a data transfer clock based on the demodulated data from the demodulation unit 21 in step S1. The data transfer clock generated by the clock generation unit 22A is supplied to the SAM chip 12.

  Further, in the clock processing unit 22, has the transmission rate detection unit 22B started detecting the transmission rate of the demodulated data from the demodulation unit 21 in step S2, and has proceeded to step S3 to detect the transmission rate? Determine if. If it is determined in step S3 that the transmission rate cannot be detected, that is, the RF chip 11 has not yet received all the header codes in the packet as demodulated data from the demodulator 21. If not, the process returns to step S3.

  If it is determined in step S3 that the transmission rate can be detected, that is, the RF chip 11 completes reception of all header codes in the packet as demodulated data from the demodulator 21, and the transmission rate When the detection unit 22B can detect the header code of the packet, the process proceeds to step S4, and the transmission rate detection unit 22B controls the data buffer 23 to thereby transmit the packet as the demodulated data stored in the data buffer 23. The transfer to the SAM chip 12 is started. Then, when all of the packets are transferred from the RF chip 11 (the data buffer 23) to the SAM chip 12, the processing is terminated.

  Note that, as described above, when the SAM chip 12 receives up to the end of the packet transferred from the RF chip 11, the SAM chip 12 performs error detection using the check code arranged at the end of the packet.

  As described above, error detection based on the check code is performed not by the RF chip 11 but by the SAM chip 12. In the RF chip 11, the packet transmission rate is determined from the header code included in the packet from the reader / writer 1. Immediately after detecting the transmission rate, transfer of the packet to the SAM chip 12 is started. Therefore, even if the data transfer rate from the RF chip 11 to the SAM chip 12 is not increased, that is, power consumption The processing time of processing performed by the IC card 2 can be shortened without increasing the value.

  That is, FIG. 6 shows the time taken for the RF chip 11 to receive a packet transmitted from the reader / writer 1 and transfer the packet to the SAM chip 12 in the IC card 2 of FIG. .

  The RF chip 11 generates a data transfer clock and detects a transmission rate while receiving a packet transmitted from the reader / writer 1. When the RF chip 11 detects the transmission rate, the RF chip 11 transfers the packet from the reader / writer 1 to the SAM chip 12 in synchronization with a data transfer clock having a frequency corresponding to the transmission rate.

  In the RF chip 11, the transmission rate is detected by detecting the header code of the packet. Therefore, when the packet is transferred from the RF chip 11 to the SAM chip 12, the header code of the packet is detected (received). Be started.

Therefore, if the time required for the RF chip 11 to receive all the header code of the head part of the packet transmitted from the reader / writer is represented by T ₂₁ , the RF chip 11 has transmitted from the reader / writer 1. The time required from the start of receiving a packet until the transfer of the packet from the RF chip 11 to the SAM chip 12 is completed is T ₂₁ + T ₁₃ as shown in FIG. Compared to the case of 1, it can be shortened.

  In other words, in the IC card 2 of FIG. 2, error detection by the check code is performed by the SAM chip 12 instead of the RF chip 11, so that before the RF packet 11 completes reception of the entire packet, the RF chip 11 performs the SAM Transfer of the packet to the chip 12 can be started.

Then, in the IC card 2 of FIG. 2, when the packet header code is detected, and when the packet transmission rate is detected, the transfer of the packet from the RF chip 11 to the SAM chip 12 is started. That is, the RF chip 11 does not wait for the time T ₁₁ required to receive the entire packet after starting reception of the packet, that is, the time required to receive the header code of the entire packet. Waiting for T ₂₁ (<T ₁₁ ), packet transfer from the RF chip 11 to the SAM chip 12 is started.

As a result, the time required for the transfer of the packet from the RF chip 11 to the SAM chip 12 after the reception of the packet transmitted from the reader / writer 1 in the RF chip 11 is completed is determined by the header code. The time T ₂₁ required for reception and the time T ₂₁ + T _{13 obtained} by adding T ₁₃ to the time required to transfer a packet from the RF chip 11 to the SAM chip 12 are shown in the case of FIG. It can be shortened in comparison.

  Further, the RF chip 11 detects the packet transmission rate and generates a data transfer clock having a frequency corresponding to the transmission rate. Therefore, the RF chip 11 performs processing corresponding to each of the plurality of transmission rates. There is no need to provide a plurality of blocks to be performed. Therefore, the RF chip 11 (the same applies to the SAM chip 12) has a single function for transferring a packet from the RF chip 11 to the SAM chip 12 in synchronization with a data transfer clock having a frequency corresponding to the detected transmission rate. You only need to provide a serial interface.

  By the way, the electromagnetic wave output by the reader / writer 2 is a weak electromagnetic wave, and the IC card 2, particularly the RF chip 11, is so sensitively configured that it can process such a weak electromagnetic wave. Therefore, an electromagnetic wave that is not a packet may be received and the header code of the packet may be erroneously detected (a signal that is not a header code may be erroneously detected as a header code signal).

  Then, when a packet is transmitted from the reader / writer 1 to the IC card 2 after the header code is erroneously detected, the packet transmitted from the reader / writer 1 is transmitted to the IC card 2 as shown in FIG. It happens that it cannot be processed.

  That is, in FIG. 7, the header code is erroneously detected in the RF chip 11, and data transfer from the RF chip 11 to the SAM chip 12 is started. When the data transfer from the RF chip 11 is started, the SAM chip 12 starts a data capturing process.

  Note that the SAM chip 12 performs error detection using a check code, but this error detection cannot be performed unless the packet is taken in (until it is received). For this reason, the SAM chip 12 continues the data capturing process until, for example, the data is captured until the end of the packet, or data of a certain size is captured.

  Thereafter, when a normal packet is transmitted from the reader / writer 1 to the IC card 2, the RF chip 11 starts receiving the normal packet. Then, when the RF chip 11 detects the header code of the normal packet, as described above, the transfer of the normal packet from the RF chip 11 to the SAM chip 12 is started. At this time, if the SAM chip 12 is performing capture processing due to erroneous detection of the header code by the RF chip 11, the SAM chip 12 cannot perform capture processing for capturing a normal packet.

  Therefore, in this case, the SAM chip 12 cannot process a normal packet.

  FIG. 8 shows a configuration example of another embodiment of the IC card system to which the present invention is applied.

  In the figure, portions corresponding to those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. That is, the IC card system of FIG. 8 is common to the IC card system of FIG. 2 in that it is composed of the reader / writer 1 and the IC card 2. Further, the IC card 2 of FIG. 8 is common to the IC card 2 of FIG. 2 in that the antenna 2A and the SAM chip 12 are provided. However, the IC card 2 of FIG. 8 differs from the case of FIG. 2 in that an RF chip 31 is provided instead of the RF chip 11.

  The RF chip 31 performs the same processing as that of the RF chip 11 of FIG. 2, and detects an error that can be detected without a check code for the received signal. By notifying the SAM chip 12, the capturing process by the SAM chip 12 is stopped.

  That is, the RF chip 31 performs an error detection process for detecting an error that can be detected without a check code for the received signal, and when an error is detected, an error detection signal indicating that is sent to the SAM chip. 12 is supplied.

  When the SAM chip 12 is supplied with an error detection signal from the RF chip 31, the SAM chip 12 initializes its internal state so that the capturing process can be stopped and a new data capturing process can be started.

  In the embodiment of FIG. 8, the RF chip 31 and the SAM chip 12 supply data from the RF chip 11 to the SAM chip 12, supply data from the SAM chip 12 to the RF chip 11, and RF chip 11. Are connected via a serial interface for supplying an error detection signal from the RF chip 11 to the SAM chip 12 in addition to the supply of the data transfer clock from the RF chip 11 to the SAM chip 12.

  Next, the operation of the IC card 2 of FIG. 8 will be described with reference to FIG.

  In FIG. 9, a header code is erroneously detected in the RF chip 31, and data transfer from the RF chip 31 to the SAM chip 12 is started. When the data transfer from the RF chip 31 is started, the SAM chip 12 starts a data capturing process.

  The RF chip 31 performs data transfer to the SAM chip 12 and also performs error detection processing for data to be transferred to the SAM chip 12, and when an error is detected by the error detection processing, an error indicating that fact is detected. A detection signal is supplied to the SAM chip 12.

  When the error detection signal is supplied from the RF chip 31, the SAM chip 12 stops the capturing process and initializes its internal state so that a new data capturing process can be started.

  Thereafter, when a normal packet is transmitted from the reader / writer 1 to the IC card 2, the RF chip 31 starts receiving the normal packet. Then, when the RF chip 31 detects the header code of the normal packet, as described above, the transfer of the normal packet from the RF chip 31 to the SAM chip 12 is started.

  At this time, since the SAM chip 12 that has already been supplied with the error detection signal from the RF chip 11 is in a state where it can perform the capturing process, the capturing process for capturing a normal packet from the RF chip 11 is performed. It can be carried out).

  Next, FIG. 10 shows a configuration example of the RF chip 31 of FIG.

  In the figure, portions corresponding to those of the RF chip 11 of FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted below as appropriate. That is, the RF chip 31 is common to the RF chip 11 of FIG. 4 in that it includes a demodulating unit 21, a clock processing unit 22, and a data buffer 23. However, the RF chip 31 is newly provided with a code error detecting unit 41. Unlike the RF chip 11 of FIG.

  The code error detector 41 is supplied with demodulated data output from the demodulator 21. The demodulation error detection unit 41 performs an error detection process for detecting an error that can be detected without a check code on the demodulated data from the demodulation unit 21, and when an error is detected, an error indicating the error is detected. A detection signal is supplied to the SAM chip 12.

  Here, the code error detector 41 detects an error that can be detected without a check code. As a method of detecting such an error, the characteristic (property) of the demodulated data output from the demodulator 21 is used. There is a method used.

  That is, in the present embodiment, the demodulated data output from the demodulator 21 is, for example, a Manchester code as described above. The Manchester code is a code that uses logic 0 data as a signal that changes from H (High) level to L (Low) level, and logic 1 data as a signal that changes from L level to H level. This level has a characteristic that the level continues only twice, and the same level does not continue three times.

  Therefore, the code error detection unit 41 has an error in the demodulated data in both cases where the H level continues three times and the L level continues three times in the demodulated data output from the demodulation unit 21. If there is, an error detection signal is output.

  Next, the operation when the RF chip 31 of FIG. 10 receives a signal (packet) from the reader / writer 1 will be described with reference to the flowchart of FIG.

  When a signal is transmitted from the reader / writer 1, the demodulator 21 of the RF chip 31 sequentially demodulates the signal from the reader / writer 1, and the demodulated data obtained as a result is sequentially detected with the clock processor 22. Supplied to the unit 41.

  When the supply of the demodulated data from the demodulator 21 is started, the clock processing unit 22 starts to supply the demodulated data to the data buffer 23, so that the data buffer 23 is supplied from the demodulator 21. The demodulated data is temporarily stored.

  Further, in the clock processing unit 22, the clock generation unit 22A starts generating a data transfer clock based on the demodulated data from the demodulation unit 21 in step S21. The data transfer clock generated by the clock generation unit 22A is supplied to the SAM chip 12.

  Further, in the clock processing unit 22, has the transmission rate detection unit 22B started detecting the transmission rate of the demodulated data from the demodulation unit 21 in step S22, and has proceeded to step S23 to detect the transmission rate? Determine if. If it is determined in step S23 that the transmission rate cannot be detected, that is, the RF chip 31 has not yet received all the header codes in the packet as demodulated data from the demodulator 21. If not, the process returns to step S23.

  If it is determined in step S23 that the transmission rate can be detected, that is, the RF chip 31 completes reception of all header codes in the packet as demodulated data from the demodulator 21, and the transmission rate When the detection unit 22B can detect the header code of the packet, the process proceeds to step S24, and the transmission rate detection unit 22B controls the data buffer 23 to thereby transmit the packet as the demodulated data stored in the data buffer 23. The transfer to the SAM chip 12 is started.

  Here, when the transfer of the demodulated data from the RF chip 11 is started, the SAM chip 12 starts taking in the demodulated data.

  In step S25, the code error detection unit 41 determines whether there is an error in the demodulated data from the demodulation unit 21. If it is determined in step S25 that there is no error in the demodulated data from the demodulator 21, the process proceeds to step S26, and the clock processor 22 determines that all of the packets as demodulated data from the demodulator 21 are RF chip 31 ( Whether the data has been transferred from the data buffer 23) to the SAM chip 12 is determined.

  If it is determined in step S26 that all of the packets have been transferred from the RF chip 31 to the SAM chip 12, the process ends.

  If it is determined in step S26 that all of the packets have not yet been transferred from the RF chip 31 to the SAM chip 12, the process returns to step S25, and the same processing is repeated thereafter.

  On the other hand, when it is determined in step S25 that the demodulated data from the demodulator 21 has an error, the process proceeds to step S27, where the code error detector 41 supplies the error detection signal to the SAM chip 12 to demodulate. The SAM chip 12 is notified that there is an error in the data, and the process is terminated.

  Here, when the error detection signal is supplied from the RF chip 31, the SAM chip 12 stops the capturing process and initializes its internal state so that a new demodulated data capturing process can be started. .

  As described above, in the RF chip 31, as in the RF chip 11, immediately after the transmission rate is detected, the transfer of the packet to the SAM chip 12 is started, so that the processing time of the processing performed by the IC card 2 is shortened. can do. Further, the RF chip 31 detects an error without a check code, and when an error is detected, notifies the SAM chip 12 to that effect and stops the capturing process. When a normal packet is transmitted from the writer 1 to the IC card 2, the IC card 2 receives the normal packet at the RF chip 31 and transfers it to the SAM chip 12. The SAM chip 12 receives the RF chip 31. Normal packets transferred from can be captured.

  Next, FIG. 12 shows a configuration example of still another embodiment of the IC card system to which the present invention is applied.

  In the figure, portions corresponding to those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. That is, the IC card system of FIG. 12 is common to the IC card system of FIG. 2 in that it is composed of the reader / writer 1 and the IC card 2. Furthermore, the IC card 2 of FIG. 12 is common to the IC card 2 of FIG. 2 in that it includes an antenna 2A and a SAM chip 12. However, the IC card 2 of FIG. 12 is different from the case of FIG. 2 in that an RF chip 51 is provided instead of the RF chip 11.

  The RF chip 51 performs the same processing as that of the RF chip 11 of FIG. 2 and detects an error that can be detected without a check code for the received signal in the same manner as the RF chip 31 of FIG. When it is detected, the SAM chip 12 is notified of this, and the capturing process by the SAM chip 12 is stopped.

  However, the RF chip 31 in FIG. 8 notifies the SAM chip 12 that an error has been detected by supplying an error detection signal to the SAM chip 12, but the RF chip 51 in FIG. The supply of the data transfer clock to the SAM chip 12 is stopped to notify the SAM chip 12 that an error has been detected.

  That is, FIG. 13 shows a configuration example of the RF chip 51 of FIG.

  In the figure, portions corresponding to those of the RF chip 31 of FIG. 10 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. That is, the RF chip 31 is common to the RF chip 31 of FIG. 10 in that the demodulating unit 21, the clock processing unit 22, the data buffer 23, and the code error detecting unit 41 are provided, but the switch 61 is newly provided. This is different from the RF chip 31 of FIG.

  The switch 61 is turned on or off in accordance with the output of the code error detection unit 41, whereby the supply of the data transfer clock to the SAM chip 12 by the clock processing unit 22 (the clock generation unit 22A) is turned on or off. It is supposed to be turned off.

  That is, the switch 61 is turned on when the code error detection unit 41 does not output an error detection signal, so that the data transfer clock output from the clock processing unit 22 is transmitted via the switch 61 to the SAM chip 12. To be supplied.

  On the other hand, the switch 61 is turned off when the code error detection unit 41 outputs an error detection signal, whereby the supply of the data transfer clock output from the clock processing unit 22 to the SAM chip 12 is stopped. That is, the supply of the data transfer clock to the SAM chip 12 is stopped, so that the SAM chip 12 is notified that an error has occurred.

  Here, in the embodiment of FIG. 12, when the supply of the data transfer clock from the RF chip 51 is stopped, the SAM chip 12 stops the acquisition process and starts the acquisition process of new demodulated data. Initialize its internal state so that

  As described above, by stopping the supply of the data transfer clock from the RF chip 51 to the SAM chip 12, the fact that an error has occurred is notified to the SAM chip 12, and as in the embodiment of FIG. In addition, it is not necessary to connect the RF chip 51 and the SAM chip 12 with a dedicated connection line for supplying an error detection signal from the RF chip 31 to the SAM chip 12.

  In the RF chip 51 of FIG. 13, the supply of the data transfer clock to the SAM chip 12 is stopped to notify the SAM chip 12 that an error has occurred. By supplying to the SAM chip 12 a clock having a frequency that is not used as a transfer clock, it is possible to notify the SAM chip 12 that an error has occurred.

  Furthermore, the processing steps described with reference to the flowcharts in this specification do not necessarily have to be processed in chronological order in the order described in the flowcharts, and may be executed in parallel or individually as necessary. Is possible.

  In the present embodiment, the case where the present invention is applied to an IC card system has been described. However, the present invention is not limited to an IC chip having an IC card function, a mobile phone incorporating the IC chip, and the like. It is applicable to a device that performs near-field communication.

  Furthermore, in the present embodiment, ASK is adopted as a modulation scheme, but the modulation scheme is not limited to ASK, and for example, PSK (Phase Shift Keying) modulation, QAM (Quadrature Amplitude Modulation) modulation and the like. There may be.

  The code for encoding the data is not limited to the Manchester code, and may be a modified mirror, NRZ (Non Return to Zero), or the like.

  The embodiment of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.

It is a figure explaining the time required for an IC card composed of two chips to receive a packet and transfer it from the RF chip to the SAM chip. It is a block diagram which shows the structural example of 1st Embodiment of the IC card system to which this invention is applied. It is a figure which shows the format of a packet. 2 is a block diagram illustrating a configuration example of an RF chip 11. FIG. 3 is a flowchart for explaining the operation of the RF chip 11. It is a figure explaining the time required for receiving a packet and transferring it from RF chip 11 to SAM chip 12. It is a figure for demonstrating the process of RF chip 11 and SAM chip 12 when a header code is detected incorrectly. It is a block diagram which shows the structural example of 2nd Embodiment of the IC card system to which this invention is applied. It is a figure for demonstrating the process of the RF chip 31 and the SAM chip 12 when a header code is detected incorrectly. 3 is a block diagram illustrating a configuration example of an RF chip 31. FIG. 4 is a flowchart for explaining the operation of the RF chip 31. It is a block diagram which shows the structural example of 3rd Embodiment of the IC card system to which this invention is applied. 3 is a block diagram illustrating a configuration example of an RF chip 51. FIG.

Explanation of symbols

  1 reader / writer, 1A antenna, 2 IC card, 2A antenna, 11 RF chip, 12 SAM chip, 21 demodulator, 22 clock processor, 22A clock generator, 22B transmission rate detector, 23 data buffer, 31 RF chip, 41 code error detector, 51 RF chip, 61 switch

Claims (5)

A one-chip communication circuit that performs proximity communication and receives a packet including a header code used for detection of a transmission rate and an error detection check code;
An information processing apparatus comprising: a one-chip secure circuit that securely stores data and performs error detection using a check code included in the packet transferred from the communication circuit;
The communication circuit includes:
Transmission rate detection means for detecting the transmission rate of the packet from the header code included in the packet, and immediately starting the transfer of the packet to the secure circuit, after detecting the transmission rate of the packet;
A clock generation unit configured to generate a clock corresponding to a transmission rate of the packet from the packet and supply the secure circuit as a clock to be synchronized with the operation of the secure circuit;
The secure circuit captures the packet whose transfer is started by the transmission rate detection means in synchronization with the clock supplied from the clock generation means, and performs error detection using a check code included in the packet. Processing equipment. A one-chip communication circuit that performs near field communication and receives a packet including a header code used for detection of a transmission rate and an error detection check code,
In the communication circuit that stores the data securely and transfers the received packet to a one-chip secure circuit that performs error detection using a check code included in the packet transferred from the communication circuit ,
Transmission rate detection means for detecting the transmission rate of the packet from the header code included in the packet, and immediately starting the transfer of the packet to the secure circuit, after detecting the transmission rate of the packet;
A communication circuit comprising: a clock generation unit configured to generate a clock corresponding to a transmission rate of the packet from the packet and supply the clock to the secure circuit as a clock to be synchronized with the operation of the secure circuit. Error detection means for detecting an error in the packet that can be detected without the check code, and notifying the secure circuit that the error has been detected, thereby stopping the capturing of the packet by the secure circuit The communication circuit according to claim 2. The communication circuit according to claim 3, wherein the error detection unit notifies the secure circuit that an error has been detected by stopping the supply of the clock to the secure circuit. A one-chip communication circuit that performs near field communication and receives a packet including a header code used for detection of a transmission rate and an error detection check code,
The communication circuit that securely stores data and transfers the received packet to a one-chip secure circuit that performs error detection using a check code included in the packet transferred from the communication circuit. In the processing method,
From the header code included in the packet, the transmission rate of the packet is detected, and immediately after the detection of the transmission rate of the packet, the transfer of the packet to the secure circuit is started,
A processing method comprising: generating a clock corresponding to a transmission rate of the packet from the packet and supplying the clock to the secure circuit as a clock to be synchronized with the operation of the secure circuit.

Images