JPH114240A - Communication controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily check a chip for executing a communication control by providing a generating means for generating data for test for testing whether a normal operation is performed or not and storing a packet processing means and generating means in one chip. SOLUTION: In a test system for testing a LINK circuit and a PHY circuit, a LINK chip 1 incorporates a test circuit 1A and the test circuit 1A outputs test data. The LINK chip 1 is also equipped with a switch and is made to select either a host interface side or the test circuit 1A side in accordance with a control signal supplied from outside. The testing circuit 1A consists of a data generation circuit for test packet and this data generation circuit for test packet is made to generate and output the test data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a communication control device, and more particularly to, for example, an IEEE (Institute of Electrica).
l and Electronic Engineers) One-chip IC (Integrated Curve) that performs communication control conforming to standards such as 1394
The present invention relates to a communication control device suitable for use in cuit).

[0002]

2. Description of the Related Art For example, a communication control device for performing communication control conforming to the IEEE 1394 standard functions as an interface with an application, and a LINK circuit (link circuit) for converting data between one packet and a LINK circuit. A PHY circuit (PHYsical layout) transmits a packet from the circuit via a cable, receives a packet from the cable, and supplies it to a LINK circuit.
er driver circuit). LINK circuit and P
The HY circuit may be configured as separate ICs, or may be configured as one integrated IC.

[0003] The LINK circuit and the PHY circuit generally have a test mode for testing whether or not the circuit operates normally, in addition to a normal mode for performing a normal operation.

FIG. 6 shows that a LINK circuit and a PHY circuit
For example, in the case of being constituted by separate chips, its LINK
An example of a test system for testing a circuit and a PHY circuit (a system is a logical collection of a plurality of devices, and it does not matter whether each device is in the same housing or not) Is shown.

The external controller 100 includes LINK chips 101 and 102 and PHY chips 3 and 4
Test data (test data) for confirming whether or not the LINK chip operates normally, for example, the LINK chip 10
Output to 1. The LINK chip 101 has a LINK
A circuit is configured to output test data from the external controller 100 to the PHY chip 3. On the PHY chip 3, a PHY circuit is configured, and a LINK circuit is provided.
The test data from the chip 101 is, for example, IEEE
Output to the cable 5 in accordance with the 1394 standard. The test data output to the cable 5 is
Is received by the PHY chip 4 configured in the same manner as
The data is supplied to the external controller 100 via the chip 102.

When the external controller 100 receives the test data from the LINK chip 102 after transmitting the test data to the LINK chip 101, the external controller 100 compares the two.
Based on the comparison result, it is checked whether the LINK chips 101 and 102 and the PHY chips 3 and 4 are operating normally.

In the above case, the test data is output to the external controller 100 and the
The test data output from the LINK chip 102 via the Y chips 3 and 4 is transferred to the external controller 100
In addition, the test data is transmitted to the LINK chip 102 in the external controller 100.
, And may be received from the LINK chip 101.

Further, the check is made by the external controller 10.
For example, it is also possible to connect a measuring instrument such as a logic analyzer to a connection point between 0 and each of the LINK chips 101 and 102, for example.

Furthermore, the test data output from the LINK chip 102 can be received by an external controller other than the external controller 100.

FIG. 7 shows a configuration example of the LINK chips 101 and 102 of FIG.

The host interface (Host I /
F) 13 functions as an interface for exchanging data with the external controller 100, outputs data from the external controller 100 to the packet data generation / detection circuit 15, and outputs a packet data generation / detection circuit 15 from the external controller 1
00 is output. The packet data generation / detection circuit 15 converts the data from the host interface 13 into a packet conforming to the IEEE 1394 standard, outputs the packet to the transmitter 16, and restores the packet from the receiver 17 to the original data. The data is output to the host interface 13. The transmitter 16 outputs a packet from the packet data generation / detection circuit 15 to an RHY interface (RHY I / F) 18. The receiver 17 outputs a packet from the RHY interface 18 to the packet data generation / detection circuit 15. RHY interface 1
3 functions as an interface for exchanging data with the RHY chip 3 (or 4), outputs a packet from the transmitter 16 to the RHY chip 3 (or 4), and outputs a packet from the RHY chip 3 (or 4). 4)
Is output to the receiver 17.

Now, in the LINK chips 101 and 102 configured as described above, the LINK chip 10
The test data is transmitted from the first side, and the LINK chip 10
Assuming that the test data is received on the two sides,
The test data from the external controller 100 is LIN
It is supplied to the K chip 101.

In the LINK chip 101, test data from the external controller 100 is transmitted to the packet data generation / detection circuit 15 via the host interface 13.
Supplied to In the packet data generation / detection circuit 15, the test data is converted into a packet and transmitted to the transmitter 1.
6. In the transmitter 16, the packet from the packet data generation / detection circuit 15 is transmitted to the PHY chip 3 via the PHY interface 18.

This packet is transmitted to the PHY chip 3
From the LI via the cable 5 and the PHY chip 4.
It is received by the NK chip 102. LINK chip 102
Then, the packet is supplied to the receiver 17 via the PHY interface 18. The receiver 17
The packet is output to the packet data generation / detection circuit 15, where the packet from the receiver 17 is restored to the original test data. This test data is stored in host interface 1
3 to the external controller 100.

[0015]

As described above, conventionally, an external controller that outputs test data to check whether the LINK chips 101 and 102 and the PHY chips 3 and 4 are operating normally is described. I had to prepare 100 and it was troublesome.

The present invention has been made in view of such a situation, and it is an object of the present invention to easily check a chip for performing communication control.

[0017]

SUMMARY OF THE INVENTION A communication control device according to the present invention includes a generation unit for generating test data for testing whether the communication device operates normally, and the packet processing unit and the generation unit are contained in one chip. It is characterized by having been done.

In the communication control device having the above-described configuration, the generation means generates test data for testing whether the operation is normal, and the packet processing means and the generation means are contained in one chip. Have been.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a configuration example of a first embodiment of a test system for testing a LINK circuit and a PHY circuit when the LINK circuit and the PHY circuit are constituted by separate chips, for example. Is shown. In the figure, parts corresponding to those in FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted below as appropriate. That is, in this test system, the external controller 100 is not provided, and instead of the LINK chip 101 or 102, the LINK chip 1 or 2 is used.
Is basically the same as the test system of FIG.

The LINK chip 1 has a built-in test circuit 1A, and the test circuit 1A outputs test data. Although not shown, LI
The NK chip 2 also includes a similar test circuit. It should be noted that the LINK chip 2 does not have a built-in test circuit, that is, the LINK chip 2 can be configured similarly to the LINK chip 102 (LINK link).
At least one of the chips 1 or 2 is a test circuit 1A
Should be built in).

FIG. 2 shows a configuration example of the LINK chip 1 of FIG. In the figure, parts corresponding to those in FIG. 7 are denoted by the same reference numerals, and a description thereof will be omitted as appropriate below. That is, the LINK chip 1 includes the switches 11 and 12 and the test circuit 1A.
LINK chip 1 in FIG.
It is basically configured in the same manner as 01.

The switches 11 and 12 select either the host interface 13 or the test circuit 1A according to a control signal supplied from the outside. The test circuit 1A is composed of a test packet data generation circuit 14 (generation means), and the test packet data generation circuit 14 generates and outputs test data.

Next, the operation will be described.

In the normal mode, switches 11 and 12
Is switched to select the host interface 13 side, the host interface 13 is enabled, and the test circuit 1A is disabled. Therefore, external data is transmitted to the switch 11 and the host interface 1.
3, and is supplied to the packet data generation / detection circuit 15 (packet processing means) via the switch 12. Therefore, in this case, the data is packetized by the packet data generation / detection circuit 15 and then output via the transmitter 16 and the PHY interface 18.

When a packet is supplied to the PHY interface 18, the packet is supplied to the packet data generation / detection circuit 15 via the receiver 17. In the packet generation / detection circuit 15, the packet from the receiver 17 is restored to the original data, and the switch 12, the host interface 13, and the switch 11
Is output to the outside through

On the other hand, in the test mode, the switches 11 and 12 are switched to select the test circuit 1A side, the host interface 13 is disabled, and the test circuit 1A is enabled. Is done. Here, for example, test data is transmitted from the LINK chip 1 and
It is assumed that the test data is received by the INK chip 2. In this case, only the LINK chip 1 that transmits the test data switches the switches 11 and 12 as described above, and the LINK chip 2 does not perform such switching. Further, in this case, LI
In the NK chip 2, as in the normal mode, the host interface 13 is in an enabled state, and the test circuit 1A is in a disabled state.

In the LINK chip 1, the test circuit 1
When A is enabled, it outputs test data to the switches 11 and 12. Since the switch 12 selects the test circuit 1A, the test data from the test circuit 1A is supplied to the packet data generation / detection circuit 15 via the switch 12.
Thereafter, the test data is transmitted to the LINK chip 2 via the PHY chips 3 and 4 in the same manner as in the case of transmitting normal data.

LINK chip 2 for receiving test data
In the above, as described above, the switches 11 and 12
Selects the host interface 13 side, so that LIN is the same as in the case of receiving normal data.
The test data from the K chip 1 includes a PHY interface 18, a receiver 17, a packet data generation / detection circuit 15, a switch 12, a host interface 13,
And output via the switch 11 to the outside.

In the LINK chip 1, the test data output from the test circuit 1A is also supplied to the switch 11 as described above, and is output to the outside via the switch 11.

As described above, the same test data output from the LINK chip 1 and transmitted to the LINK 2 and the output from the LINK chip 2
The test data received from the LINK chip 1 is compared with, for example, a logic alanizer or the like, thereby confirming whether the LINK chips 1 and 2 and the PHY chips 3 and 4 are operating normally.

As described above, the test circuit 1A is connected to the LIN
Since it is incorporated in the K chip 1, for example, FIG.
It is not necessary to prepare an external controller 100 or the like for generating test data to perform the check, unlike the related art described in (1). That is, checking can be facilitated.

In the above-described case, the test data is transmitted from the LINK chip 1 and the test data is received by the LINK chip 2. On the contrary, the test data is transmitted from the LINK chip 2. ,
The LINK chip 1 can receive the test data. However, in this case, the switches 11 and 12 are switched to output test data only for the LINK chip 2.
Such switching is not performed for the LINK chip 1. In this case, in the LINK chip 2, the host interface 13 is disabled (disabl
In the state e), the test circuit 1A is enabled. In the LINK chip 1, the host interface 13 is enabled (enab) as in the normal mode.
le), the test circuit 1A is disabled (disabl
e) state.

FIG. 3 shows a configuration example of a second embodiment of the test system to which the present invention is applied. In addition,
In the figure, portions corresponding to those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted below as appropriate. That is, this test system is different from the test system of FIG. 1 in that a LINK chip 21 or 22 is provided instead of the LINK chip 1 or 2, and the LINK chips 21 and 22 are directly connected by a cable 23. And basically the same configuration.

FIG. 4 shows a configuration example of the LINK chip 21 of FIG. In the figure, portions corresponding to those in FIG. 2 are denoted by the same reference numerals, and a description thereof will be omitted as appropriate below. That is, the LINK chip 21 is basically configured the same as the LINK chip 1 except that the test circuit 21A is provided instead of the test circuit 1A.

The test circuit 21A has a data comparison circuit 31 (comparison means) in addition to the test packet data generation circuit 14. The data comparison circuit 31 includes the switch 1
1 is compared with data supplied through the switch 12, and the comparison result is output to the outside.

The LINK chip 22 shown in FIG.
Has the same configuration as the LINK chip 21 shown in FIG.
Hereafter, each block shown in FIG.
As for the NK chip 21,
With respect to the LINK chip 22 with the subscript 21 attached, each code is described with the subscript 22 appended. That is, for example, host interface 13 constituting the LINK chip 21 includes a host interface 13 _21, host interface 13 constituting the LINK chip 22 includes a host interface 13 ₂₂ describe, respectively. However, LINK chip 2
2, a test circuit corresponding to the test circuit 21A is described as, for example, a test circuit 22A as shown in FIG.

Next, the operation will be described with reference to the timing chart of FIG. In the normal mode, data exchange is performed in the same manner as in FIGS. 1 and 2, and therefore description thereof is omitted, and only the case of the test mode will be described.

In the test mode, in the LINK chip 21, the switches 11 ₂₁ and 12 ₂₁ are connected to the test circuit 2
1A, and the host interface 13 ₂₁ is disabled (disabl
e) In the state, the test circuit 21A is enabled.
State. Furthermore, even in the LINK chip 22, switch 11 ₂₂ and 12 _22, the test circuit 22A
Together is switched so as to select the side, host interface 13 ₂₂ disabled (disable) state, the test circuit 22A is enabled (enable) state.

Then, for example, now, the LINK chip 2
1 transmits test data, and the LINK chip 22
Assuming that the test data is received, the test circuit 2 of the LINK chip 21 transmitting the test data
Data packet data generation circuit 14 ₂₁ constituting 1A
Or of the data comparison circuit 31 _21, the data packet data generation circuit 14 ₂₁ The privileged (enable) state,
Data comparing circuit 31 ₂₁ is disabled (disable) state. Also, of the LINK data packet data generating circuit 14 ₂₂ or the data comparison circuit 31 constituting the test circuit 22A of the chip 22 ₂₂ for receiving the test data, a data packet data generation circuit 14 ₂₁ disables (disable) state the data comparison circuit 31 ₂₁ is enabled (enable) state.

In the LINK chip 21, the test packet data generation circuit 14 _{21, which} has been enabled, sends test data to the switches 11 ₂₁ and 1 1.
Output to 2 ₂₁ (FIG. 5 (A)). Since the switch 12 ₂₁ selects the test circuit 21A side, the test data output from the test packet data generation circuit 14 ₂₁ is supplied to the packet data generation / detection circuit 15 ₂₁ via the switch 12 _21. . Then, in the same manner as when transmitting normal data, the test data (packet of)
Is transmitted to the LINK chip 22 via the PHY chips 3 and 4 (FIG. 5B).

In the LINK chip 21, since the switch 11 ₂₁ also selects the test circuit 21A, the test data output from the test packet data generation circuit 14 ₂₁ is output via the switch 11 _21. You. In this case, the switch 11 _{21 of the} LINK chip ₂₁
When, the switch 11 ₂₂ of LINK chip 22 are directly connected via a cable 23 (FIG. 3), therefore,
The test data output via the switch 11 ₂₁ is L
Is supplied to the switch 11 ₂₂ of INK chip 22 (FIG. 5
(D)). Switch 11 _22, as described above, and select the test circuit 22A side, therefore, the switch 11 ₂₂
Test data supplied to is supplied to the test circuit 22A, are received by the data comparing circuit 31 ₂₂ is enabled (enable) state. The data comparison circuit 31 _22, above the test data supplied is stored (latched) (FIG. 5 (D)).

The test data (packet) (FIG. 5B) transmitted from the LINK chip 21 via the PHY chips 3 and 4 is transmitted to the LINK chip 2.
It is received by the second PHY interface 18 _22, via the receiver 17 _22, and a packet data generation / detection circuit 15 ₂₂ is supplied to the switch 12 _22. Switch 12 ₂₂
Has selected test circuit 22A side, therefore, the test data supplied via a packet data generation / detection circuit 15 _22, through the switch 12 _22, test circuit 2
2A (FIG. 5C). In test circuit 22A, test data supplied through the switch 12 ₂₂ is received by the data comparing circuit 31 ₂₂ is enabled (enable) state. The data comparison circuit 31 _22,
Test data supplied through the switch 12 ₂₂ (FIG. 5
And (C)), is supplied via the switch 11 _22, already a stored test data (FIG. 5 (D)) are compared, the comparison, thereby, LINK chip 21 and 22,
It is confirmed whether the PHY chips 3 and 4 are operating normally. Then, in response to the result of the confirmation as to whether the operation is normal, a flag indicating that fact is output to the outside.

As described above, the test circuit 21A or 2
2A is built in the LINK chip 21 or 22, respectively. For example, as in the conventional case described with reference to FIG.
There is no need to prepare anything. Further, in this case, it is not necessary to prepare a measuring instrument such as a logic analyzer. That is, the check can be made easier.

In the above case, the test data is transmitted from the LINK chip 21 and the LINK chip 2
2, the test data is received, but conversely, the test data can be transmitted from the LINK chip 22 and the LINK chip 21 can receive the test data. However, in this case, the data packet data generation circuit 14 ₂₁ or data comparator circuit 31 ₂₁ constituting the test circuit 21A is respectively disabled (disable) state or enabled (enable) state, also form the test circuit 22A data packet data generating circuit 14 ₂₂ or the data comparison circuit 31 _22, respectively enable (enable)
State or disable state.

The case where the present invention is applied to a chip that performs communication control in conformity with the IEEE 1394 standard has been described above, but the present invention is also applicable to a chip that performs communication control in accordance with other standards. .

In the present embodiment, the LINK circuit and the PHY circuit are constituted by separate chips, but they may be constituted by one chip.

[0047]

As described above, according to the communication control apparatus of the present invention, packet processing means for packetizing data and restoring the packet to data, and a test device for testing whether or not normal operation is performed. Since the generation means for generating data is contained in one chip, it is possible to easily perform a test as to whether or not it operates normally.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a first embodiment of a test system to which the present invention has been applied.

FIG. 2 is a block diagram illustrating a configuration example of a LINK chip 1 of FIG. 1;

FIG. 3 is a block diagram illustrating a configuration example of a second embodiment of a test system to which the present invention has been applied.

FIG. 4 is a block diagram illustrating a configuration example of a LINK chip 21 of FIG. 3;

FIG. 5 is a timing chart for explaining the operation of the second embodiment.

FIG. 6 is a block diagram illustrating a configuration of an example of a conventional test system.

FIG. 7 is a block diagram illustrating a configuration example of a link chip 101 (102) in FIG. 6;

[Explanation of symbols]

1, 2, LINK chip, 3, 4 PHY chip,
5 cable, 11, 12 switch, 13 host interface, 14 test packet data generation circuit (generation means), 15 packet data generation /
Detection circuit (packet processing means), 16 transmitter, 17 receiver, 18 PHY interface, 21, 22 LINK chip, 21A, 22A
Test circuit, 23 cables, 31 Data comparison circuit (comparison means)

Claims (2)

[Claims] 1. A communication control device for performing communication control, comprising packet processing means for packetizing data and restoring the packet to data, wherein test control data for testing whether or not normal operation is performed. A communication control device, comprising: generating means for generating, wherein the packet processing means and the generating means are contained in one chip. 2. The apparatus according to claim 1, further comprising: a comparing unit configured to compare data obtained by reconstructing a packetized version of the test data with the test data, wherein the packet processing unit, the generating unit, and the comparing unit include one unit.
The communication control device according to claim 1, wherein the communication control device is contained in a chip.