JP3797094B2 - Packet detection display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a packet detection display device, and more specifically, a TS signal generator, a TS signal analysis device, which is used for production, adjustment, and design of digital broadcasting equipment, and that inputs and outputs TS (Transport Stream) signals, The present invention also relates to a packet detection display device mounted on a TS signal interface / data rate conversion device or the like.
[0002]
[Prior art]
TV broadcasting is scheduled to shift to digital broadcasting by BS broadcasting this year and terrestrial broadcasting by 2010, instead of the current analog broadcasting, and will be digitized in several years. The TS signal is a signal obtained by digitizing and multiplexing transmission information such as an image, sound, and data. In digital broadcasting, a broadcast wave in which a TS signal is modulated is transmitted to users in each home.
[0003]
When the manufacturer develops a set-top BOX (digital BS tuner), etc., the TS signal from the TS signal generator is used as the reference signal, or the TS signal containing an error is used to output the transmission information correctly. The operation is confirmed whether or not it is performed. A packet detection display device is used to confirm that a packet signal such as a TS signal is correctly transmitted or received.
[0004]
FIG. 3 is a block diagram of a conventional packet detection and display apparatus. FIG. 5A shows an application example to a TV broadcast receiving apparatus that receives a TS signal. The packet detection display device inputs an externally input TS signal 101 to the data processing circuit 22 via the input buffer 21. The data processing circuit 22 performs data analysis, TS signal data rate and synchronization signal detection, and other error analysis, and inputs an analysis signal 104 as a result of the analysis to the display device control circuit 23. The display device control circuit 23 inputs data corresponding to the display method to the display device 24 based on the analysis signal 104. The display device 24 displays the input state of the TS signal 101 by a display method such as a data rate method, a progress bar method, or a counter method.
[0005]
The data processing circuit 22 performs interface conversion, data rate conversion, and the like, and outputs the converted signal to the outside. Some TV broadcast receivers only perform TS signal interface conversion and data rate conversion, and do not require the display device control circuit 23 and the display device 24.
[0006]
FIG. 5B is an example applied to a TV broadcast transmitting apparatus that transmits a TS signal. The data output circuit 25 generates the TS signal 101 and outputs it to the outside via the output buffer 26. The packet detection display device uses the display device control circuit 23 and the display device 24 to display the output state of the TS signal to be output to the outside, similarly to the TV broadcast reception device. In the packet detection display device, when the TS signal 101 from the data output circuit 25 is input to the display device control circuit 23, there are two methods indicated by a solid line and a broken line.
[0007]
In the first method indicated by the solid line, the data output circuit 25 stores all of the generated TS signals 101 and inputs them to the display device control circuit 23 as all TS signals 105. In the TV broadcast transmitting apparatus, the user cannot confirm whether all the data of the output TS signal 101 is correct unless all the TS signals from the data output circuit 25 are analyzed.
[0008]
In the second method indicated by the broken line, the data output circuit 25 inputs the generated TS signal 101 to the data processing circuit 22. The data processing circuit 22 performs data analysis and error analysis, and inputs the analysis signal 104 to the display device control circuit 23. In the TV broadcast transmitting apparatus, the output state of the TS signal 101 from the data output circuit 25 is displayed in real time, and the user can confirm whether or not the content of the output TS signal 101 is correct.
[0009]
[Problems to be solved by the invention]
In the conventional packet detection display device, the input state or output state of the TS signal 101 is displayed using the data processing circuit 22, the display device control circuit 23, the display device 24, and the like. Here, since the data processing circuit 22 performs data analysis and error analysis, a data rate analysis circuit, a synchronization signal generation circuit, and the like are required, and the circuit configuration is complicated. The display device control circuit 23 and the display device 24 are expensive because they correspond to the display of the data rate, the display of the synchronization detection result, and the like.
[0010]
In the case of a TV broadcast receiving device, there is a device that displays only the result of synchronization detection without displaying the data rate, but the result of synchronization detection is irrelevant to the data rate, and the user accurately determines the input state of the TS signal. Difficult to grasp.
[0011]
In the case of a TV broadcast transmission apparatus, according to the first method, the amount of data stored in the TS signal 101 is about several Gbytes and requires a large storage capacity, and according to the second method, the same as the TV broadcast reception apparatus. become. Although there are devices that do not have the display device 24, it is difficult for the user to grasp the output state of the TS signal.
[0012]
The present invention has been made to solve the above-described problems of the prior art, and is used to check the data rate of a packet signal having a packet structure such as a TS signal and the presence or absence of the packet signal. It is an object of the present invention to provide a packet detection display device having a simple configuration.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, the packet detection display device of the present invention provides:
In a packet detection display device that detects and displays packets of a transport stream signal,
A SYNC detection circuit that generates a detection pulse when a synchronization bit string is detected from a packet of a transport stream signal, and performs counting when recognizing the detection pulse, and each time a byte of a packet of a transport stream signal is recognized, A synchronization signal having a period counter that generates a count pulse when the count value reaches the number of bytes of the packet of the transport stream signal, and a coincidence comparison circuit that generates a synchronization signal when the detection pulse and the count pulse occur simultaneously Generating circuit;
A frequency dividing circuit that divides the synchronization signal by a predetermined ratio to generate a frequency-divided signal;
Display means for displaying the divided signal;
And displaying the input / output state of the transport stream signal based on the divided signal.
[0014]
In the packet detection display device of the present invention, the synchronization signal generation circuit generates a synchronization signal based on the bit string for synchronization of the packet signal having the packet structure, and the display means indicates the generation state of the divided signal obtained by dividing the synchronization signal. Since the data is displayed, the circuit configuration for confirming the input / output state of the packet signal data rate and presence / absence is simplified.
[0015]
In the packet detection display device of the present invention, it is preferable that the display means includes a light emitting element and visually displays the input / output state. In this case, since a small and low-cost LED can be adopted as the display means, the configuration is easy and inexpensive.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a packet detection display device of the present invention will be described with reference to the drawings based on an embodiment of the present invention. FIG. 1 is a block diagram of a packet detection / display apparatus according to a first embodiment of the present invention.
[0018]
The packet detection display device according to the present embodiment is mounted on, for example, a device to which a TS signal is input from the outside or a device that outputs a generated TS signal to the outside. Devices to which a TS signal is input from the outside include a TV broadcast receiving device, a TS signal analyzing device, a TS signal interface / data rate converting device, and the like. Devices that output the generated TS signal to the outside include a TV broadcast transmitter and a TS signal generator.
[0019]
FIG. 5A shows an application example to a TV broadcast receiving apparatus. The packet detection display device includes an input buffer 1, a synchronization signal generation circuit 2, a frequency dividing circuit 3, a light emitting element control circuit 4, a light emitting element unit 5, and a data processing circuit 6. The light emitting element part 5 is comprised with small light emitting elements, such as LED. The light emitting element control circuit 4 and the light emitting element unit 5 constitute display means.
[0020]
The packet detection display device inputs the TS signal 101 input from the outside to the synchronization signal generation circuit 2 and the data processing circuit 6 via the input buffer 1. The data processing circuit 6 performs data analysis and error analysis, and performs interface conversion, data rate conversion, and the like. The data processing circuit 6 can input the analyzed or converted signal to another circuit and use the analyzed or converted signal. However, if only the input state indicating the data rate and presence / absence of the TS signal 101 is confirmed, It can be omitted.
[0021]
FIG. 2 shows the packet structure of the TS signal. The TS signal is composed of a plurality of TS packets having a fixed length of 188 bytes. The TS packet includes a 4-byte header part and a 184-byte data part. The data part stores transmission information such as images, sounds, and data.
[0022]
The header section is composed of an 8-bit synchronization section, a 3-bit instruction section, a 13-bit PID section, a 4-bit control section, and a 4-bit counter section. A SYNC value of 0x47 (47 in hexadecimal) is assigned in advance to the synchronization unit as a synchronization bit string.
[0023]
The synchronization signal generation circuit 2 includes a period counter, a coincidence comparison circuit, a SYNC detection circuit, and a false detection prevention circuit. The period counter, the coincidence comparison circuit, the SYNC detection circuit, and the false detection prevention circuit operate in synchronization with a clock generated for each byte of the TS packet. When detecting the SYNC value from the TS packet of the TS signal 101, the SYNC detection circuit generates a detection pulse. When the period counter recognizes the detection pulse, it starts counting from 0. The period counter increments the count value by one for each byte of the TS packet, and generates a count pulse when the count value reaches 188 (the number of bytes of the TS packet). The coincidence comparison circuit generates the synchronization signal 102 when the detection pulse and the count pulse are generated simultaneously. Thus, the synchronization signal generation circuit 2 generates one pulse of the synchronization signal 102 for every 188 bytes of the TS signal 101.
[0024]
The SYNC detection circuit also generates a detection pulse when the value of the bit string stored in the data portion of the TS packet matches the SYNC value. The false detection prevention circuit controls the SYNC detection circuit for the bit string of the data portion and stops the generation of the detection pulse. In addition, erroneous detection pulses occur with a probability of 1/256, and the erroneous detection pulse has little influence on the display state of the light-emitting element unit 5, and erroneous detection may not occur due to functions of other circuits. Therefore, the false detection prevention circuit can be omitted.
[0025]
The synchronization signal generation circuit 2 inputs the synchronization signal 102 to the frequency dividing circuit 3. The frequency dividing circuit 3 divides the synchronization signal 102 by 1 / N and inputs it to the light emitting element control circuit 4 as the frequency divided signal 103. The light emitting element control circuit 4 inputs a blinking signal for driving the light emitting element to the light emitting element unit 5 in synchronization with the pulse of the frequency-divided signal 103. The light emitting element unit 5 emits light based on the blinking signal, and the blinking interval of the light emission changes in proportion to the data rate of the TS signal 101.
[0026]
FIG. 1B shows an application example to a TV broadcast transmitting apparatus. The packet detection display device includes a synchronization signal generation circuit 2, a frequency dividing circuit 3, a light emitting element control circuit 4, a light emitting element unit 5, a data output circuit 7, and an output buffer 8. The data output circuit 7 generates a TS signal 101 and inputs it to the output buffer 8 and the synchronization signal generation circuit 2. The TS signal 101 has a data part having a predetermined content. The output buffer 8 amplifies the TS signal 101 and outputs it to the outside of the packet detection display device.
[0027]
The synchronization signal generating circuit 2, the frequency dividing circuit 3, the light emitting element control circuit 4, and the light emitting element unit 5 operate in the same manner as in the application example to the TV broadcast receiving apparatus. The synchronization signal generation circuit 2 inputs the generated synchronization signal 102 to the frequency dividing circuit 3 based on the TS signal 101. The frequency divider circuit 3 inputs the frequency-divided frequency signal 103 to the light emitting element control circuit 4 based on the synchronization signal 102. The light emitting element control circuit 4 displays the output state of the TS signal 101 on the light emitting element unit 5.
[0028]
Here, contents that can be confirmed by the user using the packet detection display device will be described. The TS signal 101 is used at a transmission rate of about 1 Mbit / s to 80 Mbit / s. Since the frequency division ratio N of the frequency dividing circuit 3 is set to a predetermined value, the blinking interval of the light emitting element unit 5 based on the frequency divided signal 103 can be visually recognized. Even if the user is not familiar with the TS signal, the user can determine the presence or absence of the TS signal by observing the blinking of the light emitting element unit 5, and always use it by observing the blinking interval of the light emitting element unit 5 several times. It can be determined whether or not the TS signal is the same.
[0029]
According to the above embodiment, the synchronization signal generation circuit generates the synchronization signal based on the bit string for synchronization of the packet signal having the packet structure, and the display means displays the generation state of the divided signal obtained by dividing the synchronization signal. This simplifies the circuit configuration for confirming the input / output status of the packet signal data rate and presence / absence.
[0030]
In the above-described embodiment, an apparatus for inputting / outputting a TS signal has been described. However, the same effect can be obtained for an apparatus for inputting / outputting a packet signal having a fixed-length packet structure having a pre-allocated bit string for synchronization. .
[0031]
In addition to the visual method, an auditory method using sound can be adopted as the display means.
[0032]
As described above, the present invention has been described based on the preferred embodiment. However, the packet detection display device of the present invention is not limited to the configuration of the above-described embodiment. The packet detection and display device subjected to the above correction and change is also included in the scope of the present invention.
[0033]
【The invention's effect】
As described above, in the packet detection display device of the present invention, the synchronization signal generation circuit generates the synchronization signal based on the synchronization bit string of the packet signal having the packet structure, and the display means divides the synchronization signal. Since the generation state of the peripheral signal is displayed, the circuit configuration that can check the input / output state of the data rate and presence / absence of the packet signal is simplified.
[0034]
In addition, since a device equipped with a packet detection display device adopts a small and low-cost LED as a display means, the configuration is easy and inexpensive, so the size and cost can be reduced, and a general user can easily packet Since it can be used as an additional function for confirming the signal input / output state, convenience is improved.
[Brief description of the drawings]
FIG. 1 is a block diagram of a packet detection display device according to a first embodiment of the present invention.
FIG. 2 shows a packet structure of a TS signal.
FIG. 3 is a block diagram of a conventional packet detection display device.
[Explanation of symbols]
1, 2 21 Input buffer 2 Sync signal generating circuit 3 Frequency dividing circuit 4 Light emitting element control circuit 5 Light emitting element section 6, 22 Data processing circuit 7, 25 Data output circuit 8, 26 Output buffer 23 Display device control circuit 24 Display device 101 TS Signal 102 Synchronization signal 103 Divided signal 104 Analysis signal 105 All TS signals

Claims (2)

In a packet detection display device that detects and displays packets of a transport stream signal,
A SYNC detection circuit that generates a detection pulse when a synchronization bit string is detected from a packet of a transport stream signal, and performs counting when recognizing the detection pulse, and each time a byte of a packet of a transport stream signal is recognized, A synchronization signal having a period counter that generates a count pulse when the count value reaches the number of bytes of the packet of the transport stream signal, and a coincidence comparison circuit that generates a synchronization signal when the detection pulse and the count pulse occur simultaneously Generating circuit;
A frequency dividing circuit that divides the synchronization signal by a predetermined ratio to generate a frequency-divided signal;
Display means for displaying the divided signal;
And a packet detection display device that displays an input / output state of a transport stream signal based on the divided signal. The packet detection display device according to claim 1, wherein the display unit includes a light emitting element and visually displays the input / output state.

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