JP3511631B2 - Solid-state imaging device - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to a charge coupled device (CCD:
The present invention relates to a solid-state imaging device that generates and outputs digitized image data from an imaging signal obtained by a solid-state image sensor such as a CCD image sensor formed by a Charge Coupled Device), and particularly converts a data clock of the generated image data. The present invention relates to a solid-state imaging device having a rate conversion function.

[0002]

2. Description of the Related Art Generally, in a solid-state image pickup device using a solid-state image sensor having a discrete pixel structure such as a CCD image sensor as an image pickup means, since the solid-state image sensor itself is a sampling system, It is known that the aliasing component from the spatial sampling frequency is mixed in the image pickup signal by the method. Conventionally,
By providing a birefringent optical low-pass filter in the image pickup optical system and suppressing the high frequency component of the baseband component of the image pickup signal, the Nyquist condition of the sampling system by the solid-state image sensor is satisfied, and the image pickup signal is obtained. The generation of the aliasing component to the baseband component of is prevented.

Further, in a color television camera device for picking up a color image, a two-plate type for picking up images of three primary colors by a solid-state image sensor for picking up a green image and a solid-state image sensor provided with color coding filters for red and blue pixels. 2. Description of the Related Art Solid-state image pickup devices and multi-plate type solid-state image pickup devices such as three-plate type solid-state image pickup devices that pick up three primary color images by individual solid-state image sensors have been put into practical use.

Further, as a method for improving the resolution in the multi-plate type solid-state image pickup device, as compared with a solid-state image sensor for green image pickup, only 1/2 of the spatial sampling period of pixels is used for red image pickup. A spatial pixel shift method is known in which solid-state image sensors for capturing a blue image are arranged in a shifted manner. By adopting this spatial pixel shift method, a high resolution exceeding the limit of the number of pixels of the solid-state image sensor can be realized in the analog output multi-plate solid-state imaging device.

Further, the D-1 standard and the D-2 standard have been standardized as standards for professional-use digital video tape recorders used in broadcasting stations and the like, and for digital video-related equipment conforming to these standards. Digital interfaces are also needed for color television camera devices.

Here, in the D-1 standard, which is a standard of a 4: 2: 2 digital component video signal, the sampling frequency is a horizontal frequency f in the NTSC system.
13.5M, which is 858 times _{H (NTSC)} and 864 times the horizontal frequency f _{H (PAL)} in the PAL system.
The frequency is set to Hz, and it is possible to lock at an integer multiple of the horizontal frequency in either method. Further, in the D-2 standard, which is a standard for digital composite video signals, the sampling frequency is set to 4F _{SC, which} is four times as large as the subcarrier, so that the beat interference between the subcarrier and the sampling clock is minimized. Has a sampling frequency f _{S (NTSC)} of 14.3 MHz and a PAL sampling frequency f _{S (PAL)} of 17.734 MHz.

[0007]

By the way, in the case of realizing a solid-state image pickup device which directly outputs a digital image signal conforming to the D-1 standard or the D-2 standard as described above, the resolution is high. In order to directly output a good-quality digital image signal with little aliasing distortion, the sampling rate (the number of pixels) of the solid-state image sensor used in the image pickup unit is set to that of an optical low-pass filter which is a pre-filter for the solid-state image sensor. Considering imperfections, that is, an optical low-pass filter can only obtain a gentle roll-off characteristic, and it is difficult to achieve both a good MTF characteristic and a small aliasing distortion component at the same time. It is necessary to make it higher than the sampling rate in the D-1 standard and the D-2 standard.

In addition, regarding the image pickup signal from the solid-state image sensor, considering that the defect correction processing for each pixel of the solid-state image sensor is digitally processed and that beat interference is prevented, the solid-state image sensor is It is desirable that the sampling rate and the sampling rate in the analog-digital conversion unit that digitizes the image pickup signal from the solid-state image sensor be matched.

In this case, the most standard CCD image sensor at present is designed to be driven at a clock rate of 14.3 MHz = f _{SC (NTSC)} , and digital processing using this CCD image sensor in the image pickup section is performed. With the camera,
The image pickup signal output from the solid-state image sensor is digitized at the clock rate of 14.3 MHz = f _{SC (NTSC)} to perform digital signal processing.

However, as described above, the clock rate in the D-1 standard, which is the standard of the 4: 2: 2 digital component video signal, is such that the luminance signal Y is 13.5 MHz and the color difference signals C _R / C _B are 6. Since it is 75 MHz, there is a problem that it cannot be matched with the clock rate in the digital processing camera using the standard CCD image sensor in the image pickup section. If a CCD image sensor with a read rate of 13.5 MHz is newly prepared in order to comply with the D-1 standard, there are problems in terms of cost and versatility.

Further, a multi-plate solid-state imaging device that employs a method shifting space pixels, unless a signal processing system that operates at twice the clock rate 2f _S1 of the CCD image sensor relative to the clock rate f _S1, analog output Can not be high resolution. In the signal processing system, f _S1 , 2f _S1
In after signal processing, once into analog at f _S1 or 2f _S1, it is conceivable to re-digitized at a clock rate at D-1 standard after treatment with the analog filter, 14.3 MHz system and the 13 Beat interference occurs with the 0.5 MHz system, which causes deterioration of image quality.

Therefore, in view of the above situation, the present invention provides a solid-state image pickup device which can obtain a digital image signal of a clock rate of D-1 standard or another clock rate by using a standard CCD image sensor. The purpose is to do.

It is another object of the present invention to provide a solid-state image pickup device which can obtain a digital image signal of good image quality without causing beat interference by using a signal processing system which operates at the same clock rate as the clock rate of the CCD image sensor. And

Further, by adopting the spatial pixel shift method, a high resolution analog image signal and a high MT with less aliasing distortion.
It is an object of the present invention to provide a solid-state imaging device that can simultaneously obtain an F digital image signal.

A further object is to simplify the structure of the solid-state image pickup device.

[0016]

In order to achieve the above-mentioned object, a solid-state image pickup device according to the present invention outputs at least one solid-state image sensor driven at an f _S1 rate. An analog-to-digital converter that digitizes the image pickup signal at a predetermined phase f _S1 rate and at least a digital signal from the image data digitized by the analog-to-digital converter that operates at a clock rate related to the f _S1 rate. A first digital operation unit for generating a luminance signal Y and two digital color difference signals C _R , C _B ; and an input data rate signal Y related to the f _S1 rate generated by the first digital operation unit, converting C _R, a _{C B} signal _Y output data rate associated with _{f S2 rate,} C R, a _{C B} Characterized by comprising a second digital processing unit a plurality of rate conversion ratios that can be set by changing the filter coefficients.

According to the present invention, in the above solid-state image pickup device, the first digital arithmetic unit has a 2f _S1 rate.
A digital luminance signal Y is generated, and the second digital arithmetic unit generates f for the 2f _S1 rate digital luminance signal Y generated by the first digital arithmetic unit.
_It functions as a Nyquist filter for the clock rate of _S2 , and the 2f _S1 rate digital luminance signal Y (2
f _S1 ) and a 2f _S1 rate digital luminance signal Y (2) supplied through the filter.
It is characterized by comprising a rate conversion filter that performs a rate conversion process of 2f _S1 → f _{S2 on} f _S1 ), the characteristics of the filter are fixed, and the rate conversion ratio of the rate conversion filter can be freely set.

Further, according to the present invention, in the above solid-state image pickup device, the second digital arithmetic unit produces each signal Y (2f) of a clock rate generated by the first digital arithmetic unit and related to the f _S1 rate. _S1 ), _CR (f
_{S 1} ), C _B (f _S1 ), f _S2 , f _S2 /
Functions as the Nyquist filter for _{2, f S2} / 2 clock rate digital luminance signal Y _{(2f S1),} respectively _{f S1} rate digital color difference signals _C R _{(f S1)} of the _{2f S1} rate, C B _{(f S1)} And a signal Y supplied through the filter.
For (2f _S1 ), C _R (f _S1 ), and C _B (f _S1 ), 2f with respect to the digital luminance signal Y (2f _S1 ).
_S1 → performs rate conversion processing _{f S2,} digital color difference signals _{C R (f S1), f} S1 respect C B _{(f S1)} →
It is characterized in that it is composed of a rate conversion filter for performing the rate conversion processing of f _S2 / 2, the characteristic of the filter is fixed, and the rate conversion ratio of the rate conversion filter can be freely set.

The solid-state image pickup device according to the present invention is arranged by adopting the spatial pixel shift method in the color separation optical system, and f
A plurality of the solid-state image sensor driven in _S1 rate, and analog-to-digital converter for digitizing the respective image signal at f _S1 rates of the respective predetermined phase output from the solid-state image sensor, by the analog-digital conversion unit From each digitized image data, at least a 2f _S1 rate digital luminance signal Y (2f
_S1 ) and two digital color difference signals C _R (f _S1 ), C _B (f _S1 ) each having an f _S1 rate, and the above-mentioned f generated by the first digital calculation unit. Each signal Y (2f _S1 ), (f _S1 ), C _B (f of the input data rate related to the _S1 rate
_S1 ) is subjected to a rate conversion process of 2m → n (m and n are positive integers), and f _S2 = f _S1 · n / m rate digital luminance signal Y (f _S2 ) and f _S2 / 2 Rate digital color difference signals C _R (f _S2 / 2), C _B (f _S2)
/ 2) for generating a plurality of rate conversion ratios n / m can be set.

Further, according to the present invention, in the solid-state image pickup device, the second digital operation unit is a digital luminance signal Y (2f _S1 ) of 2f _S1 rate generated by the first digital operation unit, _It functions as a Nyquist filter for the clock rate of _S2 , and 2f
A filter that outputs a digital luminance signal Y (2f _S1 ) at the _S1 rate, and 2f that is supplied through the filter.
_The rate conversion filter is configured to perform rate conversion processing of 2f _S1 → f _{S2 on} the _S1 rate digital luminance signal Y (2f _S1 ), the characteristics of the filter are fixed, and the rate conversion ratio of the rate conversion filter can be set freely. It is characterized by

According to the present invention, in the above solid-state image pickup device, the second digital arithmetic section produces each signal Y (of the input data rate related to the f _S1 rate generated by the first digital arithmetic section. 2f _S1 ),
For (f _S1 ), C _B (f _S1 ), f _S2 , f _S2
/ _{2, f S2} / 2 of functions as the Nyquist filter for the clock rate, _{2f S1} rate of the digital luminance signal Y _{(2f S1),} respectively _{f S1} rate digital color difference signals _{C R (f S1), C} B (f S1 ) a filter for outputting the respective signals _{Y (2f} S1 supplied through the _{filter), C R (f S1)} , 2 for C B _{(f S1),} the digital luminance signal Y _{(2f S1)}
performs rate conversion processing _{f S1} → f _S2, digital color difference signals _{C R (f S1), f} S1 respect C B _{(f S1)}
It is characterized in that it is composed of a rate conversion filter for performing rate conversion processing of f _S2 / 2, the characteristic of the filter is fixed, and the rate conversion ratio of the rate conversion filter can be freely set.

Further, according to the present invention, in the solid-state image pickup device, each signal Y of the input data rate related to the f _S1 rate generated by the first digital arithmetic unit is generated.
(2f _S1 ), C _R (f _S1 ), and C _B (f _S1 ) are analogized, and a digital-analog conversion unit that outputs an analog luminance signal and an analog color difference signal is provided.

[0023]

In the solid-state image pickup device according to the present invention, the image pickup signal output from at least one solid-state image sensor driven at the _fS1 rate is digitized by the analog-digital converter at the predetermined phase _fS1 rate, f
_At least the digital luminance signal Y and the two digital color difference signals C _R and C _B are generated by the first digital operation unit that operates at the clock rate related to the _S1 rate, and a plurality of rate conversion ratios are obtained by changing the filter coefficient. The settable second digital operation unit causes the signals Y, C _R and C _{B of} the input data rate related to the f _S1 rate to be set.
The output data rate signal Y related to the f _S2 rate,
Convert to C _R and C _B.

Further, in the solid-state image pickup device according to the present invention, each image pickup output from a plurality of solid-state image sensors which are arranged in the color separation optical system by adopting the spatial pixel shift method and each driven at the f _S1 rate. The signal is digitized by the analog-digital conversion unit at each f _S1 rate of a predetermined phase, and the first digital operation unit digitizes the digital luminance signal Y (2f _S1 ) of at least 2f _S1 rate and two digital color difference signals of each f _S1 rate. _CR
(F _S1 ), C _B (f _S1 ) is generated, and each signal Y (of the input data rate related to the f _S1 rate is generated by the second digital operation unit capable of setting a plurality of rate conversion ratios n / m. For 2f _S1 ), (f _S1 ), and C _B (f _S1 ), a rate conversion process of 2 m → n (m and n are positive integers) is performed, and f _S2 = f _S1 · n / m rate digital The luminance signal Y (f _S2 ) and the digital color difference signals C _R (f _S2 / 2) and C _B (f _S2 / 2) at the f _S2 / 2 rate are generated.

Further, in the solid-state image pickup device according to the present invention, the second digital operation unit is the digital luminance signal Y (2) generated by the first digital operation unit.
For f _S1), performs band limitation processing by fill <br/> data of fixing the characteristic functioning as a Nyquist filter for the clock rate of f _S2, the settable rate conversion filter rate conversion ratio of 2f _S1 → f _S2 Performs rate conversion processing.

Further, in the solid-state image pickup device according to the present invention, the second digital arithmetic unit is arranged so that each of the signals Y (2f _S1 ) generated by the first digital arithmetic unit,
For (f _S1 ), C _B (f _S1 ), f _S2 , f _S2
/ 2, f _S2 / 2, the band limiting process is performed by a filter having a fixed characteristic that functions as a Nyquist filter for the clock rate, and the digital luminance signal Y (2
The rate conversion process of 2f _S1 → f _S2 is performed on f _S1 ) to obtain digital color difference signals C _R (f _S1 ) and C _B (f
The rate conversion process of f _S1 → f _S2 / 2 is performed on _S1 ).

Further, in the solid-state image pickup device according to the present invention,
Each signal Y generated by the first digital arithmetic unit
_{(2f S1), C R (} f S1), and outputs an analog luminance signal and analog color difference signals to analog form by a digital-analog converter and C _B (f _S1).

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the solid-state image pickup device according to the present invention will be described in detail below with reference to the drawings. The solid-state imaging device according to the present invention is configured, for example, as shown in FIG.

The solid-state image pickup device of the first embodiment shown in FIG. 1 is applied to a digital camcorder for digitizing an image pickup signal obtained by the image pickup section 1 and recording it as image data conforming to the D1 standard. The analog-to-digital converter 3 to which the three primary color image pickup signals R, G, and B obtained by the unit 1 are supplied via the analog signal processing unit 2, and the image pickup data of each color digitized by the analog-digital (A / D) converter 3. A first digital arithmetic unit 4 to which R, G and B are supplied, and a second digital luminance signal Y generated by the first digital arithmetic unit 4 and a second digital color difference signal C _R and C _{B to} be supplied. The recording / reproducing unit 7 for storing and reproducing the image data conforming to the D1 standard is provided with the digital arithmetic unit 5 and the signal processing unit 6 for analog output. And it is connected to the digital processing unit 5.

The image pickup section 1 splits the image pickup light incident from an image pickup lens (not shown) through an optical low-pass filter into three primary color light components by a color separation prism and picks up three primary color images of a subject image. It is composed of CCD image sensors 1R, 1G, 1B.

In this embodiment, the three CCD image sensors 1R, 1G and 1B adopt the spatial pixel shift method to pick up the CCD image sensor 1G for green image pickup.
On the other hand, the CCD image sensors 1R and 1B for red image capturing and blue image capturing are displaced by 1/2 of the spatial sampling period τ _s of pixels.

The invention of the present application is not applicable only to the three-plate type solid-state image pickup device adopting the spatial pixel shift method as in this embodiment, but is also applicable to a single-plate type or two-plate type solid-state image pickup device or the spatial pixel shift method. The present invention can also be applied to other types of solid-state image pickup devices such as a three-plate type solid-state image pickup device that does not adopt.

The above three CCD image sensors 1R, 1
G and 1B are driven at a f _S1 rate by a drive clock CK (f _S1 ) generated by a timing generator (TG) 9 based on a 2 f _S1 rate clock CK (2f _S1 ) provided by a voltage controlled oscillator (VCO) 8. Driven.

Here, the above three CCD image sensors 1R, 1G and 1B have f _S1 = 910f _H , C in EIA.
In the CIR, the number of pixels is selected so that the imaging charge is read at a rate of f _S1 = 912f _H. Then, the oscillation frequency of the VCO 8 is set to 2f _S1 , and the TG 9 drives the drive clock CK at the f _S1 rate obtained by dividing the clock CK (2f _S1 ) by 1/2.
(F _S1 ) allows the above three CCD image sensors 1R,
It is designed to drive 1G and 1B.

CCD image sensor 1R, 1G, 1
Each color imaging signal R read from B at the rate f _S1
(F _S1 ), G (f _S1 ), B (f _S1 ) are supplied to the analog signal processing section 2.

The analog signal processing unit 2 includes a correlated double sampling (CDS) processing circuit 21R, 21G, 21B and a level control circuit 22.
CDS processing circuit 21R, which is composed of R, 22G, and 22B, and performs correlated double sampling processing on the respective color image pickup signals R, G, and B read out from the CCD image sensors 1R, 1G, and 1B at the rate f _S1. , 21G, 21
B, and level control such as white balance and black balance is performed by the level control circuits 22R, 22G and 22B.

The A / D converter 3 to which the image pickup signals R (f _S1 ), G (f _S1 ), B (f _S1 ) of the respective colors obtained by the image pickup unit 1 are supplied via the analog signal processing unit 2 is , Three A / D converters 3R, 3G, each having a 10-bit word length,
It consists of 3B. Each of these A / D converters 3R, 3G, 3B
Are the image pickup signals R (f _S1 ), G (f _S1 ), B of the respective colors.
Drive clock having a predetermined phase equal f _S1 rate to the sampling rate of _{(f S1) CK (f S1} ) is the TG
It is supplied from 9. The analog-to-digital converter 3 uses the A / D converters 3R, 3G, and 3B to pick up the color image pickup signals R (f _S1 ) and G (f at the f _S1 rate.
_S1 ), B (f _S1 ) are digitized by the drive clock CK (f _S1 ) at a predetermined phase f _S1 rate, and the color image signals R (f _S1 ), G (f _S1 ), B (f _S1 ) are digitized. ) Each digital color signal R of the same signal spectrum as the spectrum of
(F _S1 ), G (f _S1 ) and B (f _S1 ) are formed.

The A / D converters 3R, 3G,
3B may have a word length of about 12 to 14 bits if necessary.

Then, each color image data R (f _S1 ) of the f _S1 rate digitized by the A / D converter 3 is
G (f _S1 ) and B (f _S1 ) are supplied to the first digital operation unit 4.

The first digital operation section 4 comprises a first digital process processing circuit 41 and a second digital process processing circuit 42.

First digital process processing circuit 4
1 is the drive clock CK (f
_S1 ) to operate at the f _S1 rate, and the A / D converter 3
From each digital color signal R (f _S1 ), G (f
_S1 ) and B (f _S1 ) are detected by detecting various correction signal levels, and white balance control data, black balance control data, black shading correction data, white shading correction data and defect correction data are stored in the memory 43. The D / A converters 44R, 44G, 4 are stored for each color signal.
Image processing such as black-and-white balance control, shading correction, and defect correction is performed by converting the signal into an analog signal by 4B and feeding it back to the level control circuits 22R, 22G, and 22B of the analog signal processing unit 2.

The memory 43 is composed of SRAM, and a battery 45 is connected as a backup power source.

Thus, in this embodiment, the CCD described above is used.
Imaging signals R (f _S1 ), G (f _S1 ), B (f) of the respective colors read out from the image sensors 1R, 1G, 1B at the f _S1 rate.
_S1 ) of each color imaged data R of f _S1 rate obtained by digitizing _S1 ) in the A / D converter 3 at f _S1 rate
Since (f _S1 ), G (f _S1 ), and B (f _S1 ) are obtained, the first digital process processing circuit 41 is operated at the f _S1 rate to perform image correction in pixel units such as shading correction and defect correction. Processing can be performed.

The second digital process processing circuit 42 is the same as the first digital process processing circuit 4.
For each of the digital color signals R, G, and B on which the image processing is performed in pixel units by 1, the image enhancement processing, the pedestal addition, the nonlinear processing such as gamma and knee, and the linear matrix processing are performed. Digital color signals R (f _S1 ), G (f _S1 ), B
Digital luminance signal Y (2f _S1) and two digital color difference signals C _R (f _S1) from (f _S1), to produce a C _B (f _S1).

Here, the second digital process processing circuit 42 is supplied with the clock CK (2f _S1 ) at the 2f _S1 rate from the VCO 8 and also receives the TG 9 from the TG 9.
And f _S1 rates driving clock CK (f _S1) are supplied from these clocks CK (2f _S1), CK
By operating (f _S1 ) as a master clock, a known resolution increasing process corresponding to the spatial pixel shift method in the image pickup unit 1 is performed, and the digital color signals R (f _S1 ),
G (f _S1), from B (f _S1), generating a 2f _S1 rate of the digital luminance signal Y (2f _S1), each of f _S1 rate digital color difference signals C _R (f _S1), a C _B (f _S1) To do.

The master clock CK (2
f _S1 ) and CK (f _S1 ) are also supplied to a sync signal generator (SG) 11 that forms various sync signals such as a horizontal sync signal HD and a vertical sync signal VD.

The second digital operation section 5 is
Bidirectional rate conversion is performed between a signal having a data rate related to the f _S1 rate and a signal having a data rate related to the f _S2 rate. In the recording mode, the rate conversion is performed by the first digital operation unit 4. And the data rate signals Y (2f _S1 ), C _R (f _S1 ), which are related to the above f _S1 rate,
C _B (f _S1 ) is the data rate signal Y (f _S2 ), C _R (f _S2 / 2), C _B (f _S2 /) related to the f _S2 rate.
2) and supplies it to the recording / reproducing unit 7, and in the reproduction mode, signals Y (f _S2 ), C _R (f) of the data rate related to the f _S2 rate supplied from the recording / reproducing unit 7.
_{S2 / 2), C B (} f S2 / 2) signal of the data rate associated with the f _S1 rate _{(2f S1), C R (} f S1), C B
(F _S1 ) and converted to the analog output signal processing unit 6
Supply to.

The second digital operation section 5 comprises a rate conversion circuit 50Y for luminance signals and a rate conversion circuit 50C for color difference signals.

Further, a digital interface 13 for an external device is provided between the second digital operation section 5 and the recording / reproducing section 7, and the second digital operation section 5 operates in the external input mode. Digital return signals Y (f _S2 ), C _R (f _S2 /) of the data rate related to the f _S2 rate input from the digital camera control unit (D-CCU) 14 through the digital camera adapter (D-CA) 15. 2), C _B
(F _S2 / 2) the data rate associated with the f _S1 rate signal _{Y (2f S1), C R} (f S1), C B is converted to (f _S1) signal processing unit 6 for the analog output Can be supplied to.

In this embodiment, the signal processing unit 6 for analog output has a data rate related to the f _S1 rate generated by the first digital operation unit 4 or the second digital operation unit 5. Signal Y (2
f _S1 ), C _R (f _S1 ), and C _B (f _S1 ) function as an analog interface, and include a digital-analog (D / A) converter 61 and an analog encoder 62.
Consists of.

The D / A converter 61 comprises three D / A converters 61Y, 61C _R and 61C _B and post filters 61PFY, 61PFC _R and 61PFC _B , respectively.

In the D / A converter 61, the digital luminance signal Y (2f _S1 ) at the 2f _S1 rate is converted into the D / A value mentioned above.
The converter 61Y converts the signal into an analog signal, the post-filter 61Y that functions as a Nyquist filter removes the sampling carrier component, and the analog signal is supplied to the analog encoder 62. Further, the digital color difference signals C _R (f _S1 ) and C _B (f _S1 ) at the f _S1 rate are respectively the above D
A / A converters 61C _R and 61C _B convert to analog,
The sampling carrier components are removed by the post filters 61PFC _R and 61PFC _{B which} respectively function as Nyquist filters.
Is supplied to.

The analog encoder 62 is a normal NTSC or PAL compliant encoder, which outputs the component signals Y, C _R and C _B and the composite signal CS, and supplies the monitor signal to the viewfinder 16. It has a function to output Y _VF .

The analog encoder 62 is constructed, for example, as shown in FIG.

In this analog encoder 62, the two analog color difference signals C _R and C _B supplied from the D / A converter 61 are respectively low pass filters 63.
The band is limited to a predetermined band (fc≈1 MHz) by C _R and 63C _B , the burst flag BF is added by the signal synthesizers 64C _R and 64C _B , and then the signal is supplied to the modulator 65. The modulator 65 outputs the analog color difference signal C _R ,
The quadrature two-phase subcarrier SC is modulated by C _B to generate a modulated chroma signal C _OUT .

On the other hand, the analog luminance signal Y supplied from the D / A converter 61 is the low-pass filter 63.
After the delay amount due to C _R and 63C _B is compensated for by the delay circuit 66, the signal synthesizer 67 adds a synchronization signal and a setup signal to the prescribed luminance signal Y.
_OUT . The luminance signal Y _OUT obtained in this way
The high resolution is achieved by the digital processing according to the above-mentioned spatial pixel shift method, and the aliasing distortion is small.

Then, the luminance signal Y _OUT and the modulated chroma signal C _OUT are mixed by the signal mixer 68 to generate the composite signal CS _OUT .

As for the luminance signal Y _OUT , the character signal from the character generator 69 is the signal mixer 7.
After being mixed by 0, it is output as the monitor signal Y _VF via the switching circuit 71. The switching circuit 71 includes a return signal RET and an intensity signal Y which are input from the outside.
_Switch to _OUT .

Here, instead of the analog encoder 62, the signal processing unit 6 for analog output is a third digital operation unit that operates at a clock rate related to the f _S1 rate, as shown in FIG. Using the digital encoder 73, the digital luminance signal Y _OUT , the digital composite signal CS _OUT , and the digital monitor signal Y _VF generated by the digital encoder 73 are analogized by the D / A converters 74Y, 74CS, 75Y _VF , respectively, and post-filtered. 74PFY, 74PFC
You may comprise so that it may output via S, 75PFY _VF .

Further, in this embodiment, the second data
The digital operation unit 5 uses f_S1Data rate related to rate
Signal and f_S2Data rate signal related to rate and
It performs rate conversion in both directions between
2f in recording mode_S1Rate digital luminance signal Y
(2f_S1) F_S2Rate digital luminance signal Y
(F _S2), And convert each to f_S1Leh
Digital color difference signal C_R(F_S1), C_B(F_S1)
f_S2/ 2 rate digital color difference signal C_R(F_S2/
2), C_B(F_S2/ 2) rate conversion, in playback mode
Has f_S2Rate digital luminance signal Y (f_S2) 2
f_S1Rate digital luminance signal Y (2f_S1) To rate
Convert and convert f_S2/ 2 rate digital
Color difference signal C_R(F_S2/ 2), C_B(F_S2/ 2) f_S1
Rate digital color difference signal C_R(F_S1), C
_B(F_S1), But each rate conversion
In order to simplify the configuration of the circuits 50Y and 50C, the playback mode
At the time of reading, f_S2Rate digital luminance signal Y
(F_S2) 2f_S2Rate digital luminance signal Y (2f
_S2), And convert each to f_S2/ 2 races
Digital color difference signal C_R(F_S2/ 2), C_B(F_S2
/ 2) f_S2Rate digital color difference signal C
_R(F_S2), C_B(F_S2) To convert rate
There is.

The clock of the D / A converter 61 is also switched to 2f _S2 , f _S2 , f _S2 in the reproduction mode. Even in this case, the frequencies f _S1 and f _S2 are quite close to each other, and the post filters 61PFY, 61PFC _R and 61PFC _B of the D / A converter 61 can be shared without switching the characteristics.

Regarding the word length, the signals Y, C _{R of} the D / A converter 61 and the digital interface,
For C _B , about 10 bits is sufficient, but for the signals Y, C _R , and C _B supplied to the second digital operation unit 5,
It is desirable to set 1 to 2 bits more in consideration of rounding in the rate conversion circuit.

Therefore, in this embodiment, the 11-bit signals Y, C _R , and C _B are processed by the first digital operation unit 4.
Is generated and the signals Y and C of the upper 10 bits are generated.
_R and C _B are supplied to the D / A converter 61. Then, in the second digital operation unit 5, further 2-3
An operation with a large number of bits is performed, and it is rounded to 10 bits at the final stage.

Next, a concrete example of the rate conversion circuit 50Y for the luminance signal and the rate conversion circuit 50C for the color difference signal which constitute the second digital operation section 5 will be described.

Rate conversion circuit 50Y for the luminance signal
Is a half band filter 51Y,
Rate converting filter 52Y, rounding circuit 53Y, a delay compensating circuit 54Y and 0 insertion circuit 55Y and first to sixth switching circuit 56Y ₁ ~ 56 switches these input and output
It is composed of Y ₆ .

Then, in the recording mode, the rate conversion circuit 50Y, as shown in FIG.
The switching circuits 56Y _{1 to} 56Y ₆ are set.

That is, in the recording mode, the 2f _S1 rate digital luminance signal Y (2f _S1 ) generated by the first digital operation unit 4 is input to the half band filter 51Y, and the rate conversion filter 52Y and the rounding process are performed. circuit 53Y, by being passed through the delay compensating circuit 54Y in this order, f _S2 rate of the digital luminance signal Y (f
_The rate is converted to _S2 ).

The half band filter 51Y is 2f.
_With respect to the digital luminance signal Y (2f _S1 ) of _S1 rate, it has an output data rate of 2f _S1 and has f _S2 / 2 as a pass band, and has a characteristic of functioning as a Nyquist filter for the f _S2 rate. In this example,
0 ± 0.1 dB (up to 5.75 MHz), <-12 dB
(~ 6.75MHz), <-40dB (8.0MHz)
And

Further, the rate conversion filter 52Y is
2 supplied through the half band filter 51Y
Among the high-order carrier components included in the digital luminance signal Y (2f _S1 ) at the f _S1 rate, 1 to n−1 are suppressed.
The rate conversion filter 52Y includes an equalization filter that operates at the 2f _S1 rate and compensates for attenuation within the band of the half band filter 51Y.

Then, the digital luminance signal Y of the f _S2 rate obtained by the rate conversion filter 52Y is obtained.
(F _S2 ) is after the scaling processing, the clipping processing, and the rounding processing are performed in the rounding processing circuit 53Y,
The delay compensation circuit 54Y performs delay compensation with respect to the color difference signal channel and outputs the signal.

Here, the rate conversion circuit 50Y for the luminance signal in this embodiment has a frequency of 2m → _fS2 = _fS1 · n / m in principle, where m and n are positive integers.
n rate conversion, for example EIA / CCIR
In order to correspond to a system having a plurality of f _S1 rates depending on the number of pixels of the CCD image sensor or the CCD image sensor, as shown in Table 1, a plurality of rate conversion ratios can be variably set to operate in a plurality of modes. .

[0072]

[Table 1]

The rate conversion circuit 50Y needs to change the characteristics and operation of rate conversion corresponding to each mode, but the half-band filter 51Y may have a common characteristic because f _S1 is close in each mode. Conversion filter 52Y
Only change the characteristics and behavior.

In the reproduction mode, the rate conversion circuit 50Y for the luminance signal is set with the _{first to sixth} switching circuits 56Y1 to 46Y6 as shown in FIG.

That is, in the reproducing mode, the digital luminance signal Y (f _s2 ) at the f _s2 rate reproduced by the recording / reproducing unit 7 is supplied to the delay compensating circuit 54Y to compensate the delay with the color difference signal channel. Is supplied to the half band filter 51Y through the 0 insertion circuit 55Y.

[0076] The zero inserter circuit 55Y, by inserting 0 data between each sample, and upconverts the f _s2 rate digital luminance signal Y and (f _s2) to 2f _s2 rate. In addition, the half band filter 51Y
In the reproduction mode, suppresses an odd-order carrier component in the 2f _s2 rate digital luminance signal Y (f _s2 ) to function as an up-rate conversion filter of f _s2 → 2f _s2 .

Then, the half band filter 51Y
2f _s2 rate digital luminance signal Y obtained by
(F _s2 ) is subjected to scaling processing, clipping processing, and rounding processing in the rounding processing circuit 53Y and is output. In the reproduction mode, the rate conversion filter 62Y is not used.

The rate conversion circuit 5 for the color difference signal is also provided.
As shown in FIG. 7, 0C is a multiplexer / demultiplexer (MPX / DMPX) 51C, a half-band filter 52C, a rate conversion filter 53C, a rounding processing circuit 54C and a 0 insertion circuit 55C, and a first input / output for switching these inputs and outputs. or it is constituted by a fourth switching circuit 56C ₁ ~56C _4.

In the recording mode, the rate conversion circuit 50C, as shown in FIG.
The switching circuits 56C _{1 to} 56C ₄ are set.

That is, in the recording mode, the digital color difference signals C _R (f _S1 ), C _B (f _S1 ) at the f _S1 rate generated by the first digital operation unit 4 are dot-sequentially converted by the MPX / DMPX 51 C. 2f _S1
Rate digital dot sequential color difference signal C _R / C _B (2f
_S1) as the input to the half-band filter 52C, a rate converting filter 53C, by being passed through the rounding circuit 54C _{sequentially,} rate conversion sequentially color difference signals digital point of _{f S2} rate _{C R / C B (f S2} ) To be done.

The half band filter 52C is 2f.
_S1 rate digital dot sequential color difference signal C _R / C _B (2
f _S1 ) at an output data rate of 2f _S1 , f
_S2 is used as a pass band and has a characteristic of functioning as a Nyquist filter for the f _S2 rate.

Further, the rate conversion filter 53C is
2 supplied through the half band filter 52C
f _S1 rate digital dot sequential color difference signal C _R / C _B (2
Of the higher-order carrier components included in f _S1 ), ₁ to n−
Suppress one. This rate conversion filter 53C is 2f
_Operates at the _S1 rate and operates the half band filter 52C.
It includes an equalization filter that compensates for attenuation in the band.

The f _S2 rate digital point sequential color difference signal C _R / C _B (f _S2 ) obtained by the rate conversion filter 53 C is subjected to scaling processing, clipping processing and rounding processing in the rounding processing circuit 54 C. Is output.

Here, the color difference signal rate conversion circuit 50C in this embodiment is, in principle, f _S2 = f _S1 where m and n are positive integers, like the above-described luminance signal rate conversion circuit 50Y.・ 2m → n at a frequency of n / m
In order to correspond to a system in which a plurality of f _S1 rates exist depending on the number of pixels of the EIA / CCIR or CCD image sensor, a plurality of rate conversion ratios can be variably set and operate in a plurality of modes. It is like this.

In this color difference signal rate conversion circuit 50C as well, it is necessary to change the characteristics and operation of the rate conversion corresponding to each mode, but the half band filter 52C is used.
Since f _S1 is a close value in each mode, a common characteristic may be used, and only the rate conversion filter 53C changes the characteristic / operation.

In the reproduction mode, the color difference signal rate conversion circuit 50C _R / C _B is set to the _{first to fourth} switching circuits 56C _{1 to} 56C ₄ as shown in FIG.

That is, in the reproduction mode, the digital dot-sequential color difference signal C _R / C _B (f _S2 ) of the f _S2 rate reproduced by the recording / reproducing unit 7 is transferred to the half band filter 52C via the 0 insertion circuit 55C. Supplied.

[0088] The 0-insertion circuit 55C, by inserting 0 data between each sample, and upconverts the f _s2 rate digital dot sequential color difference signal C _R / C _B a (f _S2) to 2f _s2 rate. In the reproduction mode, the half-band filter 52C suppresses the odd-order carrier component with respect to the digital point sequential color difference signal C _R / C _B (f _S2 ) at the 2f _s2 rate, so that f _s2 →
It functions as a 2f _{s2 uprate} conversion filter.

Then, the half band filter 52C
The 2f _S2 rate digital dot-sequential color difference signal C _R / C _B (f _S2 ) obtained by
In the scaling process or clipping, the rounding process is performed after a synchronization is _{f S1} rate digital color difference signals _C R (f by the MPX / DMPX51C
_S1 ) and C _B (f _S1 ) are output.

In the reproduction mode, the rate conversion filter 63C is not used.

[0091] Thus, the rate converting circuit 50C for color difference signals, f _S1 rate digital color difference signals C _R (f
By treating _S1 ) and C _B (f _S1 ) as digital point sequential color difference signals C _R / C _B of 2f _S1 rate, the scale of hardware can be reduced, and the same characteristics can be obtained for two color difference signals. Can be processed.

In this embodiment, the delay compensation circuit 42DLY is provided in the luminance signal channel at the output stage of the luminance signal channel of the second digital process processing circuit 42 in the first digital operation section 4. .

The delay compensating circuit 42DLY is for compensating the delay of each of the low-pass filters 63C _R and 63C _B of the analog encoder 62 in the signal processing unit 6 for analog output, and the component from the signal processing unit 6 is used. If only signals Y, C _R , C _B are used,
Each post filter 61PFY of the D / A converter 61,
61PFC _R and 61PFC _B are for delay compensation with respect to the delay amount, and when the composite signal CS or Y / C is used without using the component signals Y, C _R , and C _B , the analog encoder 62 The delay amount is set so as to compensate for the delay amount of each of the low pass filters 63C _R and 63C _B.

The difference in delay amount between the post filter 61PFY and the post filters 61PFC _R and 61PFC _B is usually as small as about 1 or 2 clocks at the f _S1 rate, and can be corrected anywhere in the processing system.

Further, in this embodiment, each low-pass filter 63C _R , 6 in the analog encoder 62 is used.
The delay amount of the 3C _B and _{DL LPF,} the delay compensating circuit 6
The delay amount of 6 is DL ₀ , the delay amount of the delay compensation circuit 42DLY provided in the output stage of the luminance signal channel of the first digital operation unit 4 is DL _1, and
The delay amounts of the half band filter 52Y, the rate conversion filter 53Y and the delay compensation circuit 54Y in the rate conversion circuit 50Y for the luminance signal are DL ₂ , DL ₃ and DL.
And the half band filter 52C and the rate conversion filter 5 in the rate conversion circuit 50C for the color difference signal.
The delay amounts of 3C are DL ₄ and DL ₅ , and in the recording mode, DL ₁ + DL ₂ + DL ₃ + DL = DL ₄ + DL
_{In 5} playback modes, DL ₂ + DL ₀ = DL ₄ + DL
Each delay amount is set so as to be an _LPF .

Here, the substantial conversion rate of the color difference signal rate conversion circuit 50C is lower than that of the luminance signal rate conversion circuit 50Y, and DL ₂ <DL ₄ , DL ₃ <
DL ₅ .

Furthermore, the 2f _s1 rate digital luminance signal Y (2
The f _s1) as an example of a specific operation of the rate converting circuit 50Y for the luminance signal to be converted to f _s2 rate digital luminance signal Y (f _s2), the rate of f _s2 = 18f _s1 / 19 i.e. 19 → 9 The case of the conversion ratio will be described with reference to the spectrum diagram shown in FIG. 10 and the time chart shown in FIG.

That is, in the recording mode, a digital luminance signal Y (2f _s1 ) [band: 0 to 2 f _s1 rate of the spectrum generated by the first digital operation section 4 as shown in FIG. f _s1 ] in the rate conversion circuit 50Y for the luminance signal, as shown in FIG.
Is band-limited to the Nyquist frequency with respect to the f _s2 rate by the half-band filter 51Y having the characteristics shown in
Digital luminance signal Y (2f _s1 ) at a 2 f _s1 rate with a spectrum as shown in FIG. 10 (C) [band: 0 to f _s2
/ 2] is supplied to the rate conversion filter 52Y.

That is, for example, a digital luminance signal Y (2f _S1 ) composed of a 2f _S1 rate sample sequence {a _n } as shown in FIG. 11 (A) is converted by the half band filter 51Y into f _S2 / 2 rate. To the rate conversion filter 52Y after being band-limited to the Nyquist frequency for.

The rate conversion filter 52Y divides each sample into 9 equal parts to the input 2f _s1 rate sample sequence {b _n }, as shown in FIG.
The point where the sample <b _m > exists [indicated by ◯ in FIG. 11B] is the original sample {b _n }, and the sample <b _m >
Is inserted at a point where the symbol does not exist [indicated by-in FIG. 11 (B)], and converted into a sample sequence {b _p } having a rate of 9 × 2f _s1 = 18f _s1 . Then, the impulse response {h of the rate conversion filter also _{expressed at the} rate of 18 f _s1 {h
_p } and the 18 f _s1 rate sample sequence {b _p } are convolved to generate an 18 f _s1 rate interpolated sample sequence. In FIG. 11B, the virtual interpolation sample sequence by the rate conversion filter 52Y is indicated by x, and the output sample sequence {c _n } at the f _s2 rate is indicated by ⊚.

Then, the above rate conversion filter 52Y
Is defined as k × 18f _s1 as defined in FIG.
± f _c (k: integer) is used as the pass band, and other than that, g × 1
The digital luminance signal Y (2f _s1 ) at the 2f _s1 rate, which has a characteristic that the stop band is 8f _s1 ± f _c (g: integer) and is supplied from the half-band filter 51Y, is shown in FIG. 2f _s1 , 4f _{s1 to} 16f _{s1 shown in}
Suppress the surrounding 2f _s1 sampling carrier component.

As a result, the digital luminance signal Y (2f _s1 ) of the above 2f _s1 rate is up-converted to the nine times 18 f _s1 rate, as shown in FIG. _s1 ).

[0103] band characteristic of the 18f _s1 rate digital luminance signal Y (18f _s1) has a Nyquist characteristic of f _s2 rate defined by the half band filter 51Y.

Here, the 18f _s1 rate filtering process is virtual, and is actually an output sample sequence {c _n } at the f _s2 rate obtained by down-sampling the 18 f _s1 rate signal every 19 samples.

[0105] Thus, convolution of the impulse response of the 18f _s1 rate {h _p} and 18f _s1 rate sample sequence {b _p} is when the sample sequence {b _p} is non-zero samples {b _m} Since it is only necessary to execute it, for example, c ₀ = h ₋₉ · b ₁ + h ₀ · b ₀ + h ₉ · b ₋₁ c ₁ = h ₋₈ · b ₃ + h ₁ · b ₂ + h ₁₀ · b ₁ c ₂ = h _-7 · b ₅ + h ₂ · b ₄ + h ₁₁ · b ₃ c ₃ = h _-6 · b ₇ + h ₃ · b ₆ + h ₁₂ · b ₅ c ₄ = h _-5 · b ₉ + h ₄ · b ₈ c ₅ = h _-4・ b ₁₁ + h ₅・ b ₁₀ c ₆ = h _-12・ b ₁₄ + h _-3・ b ₁₃ + h ₆・ b ₁₂ c ₇ = h _-11・ b ₁₆ + h _-2・ b _{15 + h 7 · b 14 c 8} = h -10 · b 18 + h -1 · b 17 + h 8 · b 16 · · · of may be performed an operation. This operation can be performed at the f _S1 rate or the f _S2 rate, for example.

Here, what is characteristically important in the rate conversion operation by the rate conversion circuit 50Y is the following first to third requirements.

First requirement: the half band filter 5
2f _s1 rate digital luminance signal Y supplied to 1Y
(2f _s1) [shown in FIG. 10 (A)] and the digital luminance signal Y (18 which is virtually up rate conversion 9 times 18f _s1 rate at said rate converting filter 52Y
f _s1 ) [(E) in FIG. 10] has the same characteristics in the band of 0 to fc, that is, the characteristics of the half-band filter 51Y [(B) in FIG. 10] and the rate conversion filter 52Y. 0 of the characteristic of the product with the characteristic [(D) of FIG. 10]
The band of ˜fc can be approximated to 1.

Second requirement: Digital luminance signal Y (18f _s1 ) up-rate converted to the above 18f _s1 rate.
[F in FIG. 10 (E)] to 2f in (18f _s1 -fc)
_{The s1} sampling carrier component is sufficiently suppressed, that is, the product of the characteristics of the half band filter 51Y [(B) of FIG. 10] and the characteristics of the rate conversion filter 52Y [(D) of FIG. 10]. Characteristic fc ~ (18f
The band of ( _s1− fc) can be approximated to 0, and in particular, the characteristics of the rate conversion filter 52Y [(D) in FIG. 10] 2f
_{s1 to} 16f When _s1 becomes 0 and the input is DC, it is output (α
.2f _s1 −βf _s2 ) component does not occur, and the characteristics of the half band filter 51Y [(B) of FIG. 10] and the characteristics of the rate conversion filter 52Y [FIG.
That is, 1f _{s2 to} 18f _{s2, which} is the characteristic of the product of 0 (D)], is sufficiently suppressed.

Third requirement: the above rate conversion filter 52
A digital luminance signal Y (18f _s1 ) that has been virtually up-converted to 18 f _s1 rate that is 9 times higher than Y [18 f _s1 ] [Fig.
That is, the filter characteristic of the rate conversion circuit 50Y is set so that the frequency characteristic near fc of (E)] of 0 is within the regulation.

In the rate conversion circuit 51 of this embodiment, the digital luminance signal Y (2f _s1 ) of 2f _s1 rate is first passed through the half band filter 51Y to achieve the above first and second requirements. The rate conversion filter 52Y can effectively achieve the third requirement. Further, since the half-band filter 51Y is a fixed coefficient FIR filter, the circuit scale can be reduced by using various filter design methods. Also,
Since the rate conversion filter 52Y is a variable coefficient filter, it requires a multiplier, but as shown in the characteristic of FIG. 10D, its roll-off characteristic is gentle and there are few restrictions on the stop band. Since it is good, it is very easy to configure.

[0111] For example, the impulse response of the rate converting filter 52Y {h _p} is {1,3,6,10,15,21,28,35,43,49,54,57,58,57, ...・}
/ 78 and 24th order, and three multipliers of the rate conversion filter 52Y can be configured. The coefficient word length is also 6 in this case.
Since it becomes a bit, the coefficient generator and the multiplier can be simplified.

The rate conversion filter 52Y of such a rate conversion circuit 51 is constructed, for example, as shown in FIG.

The rate conversion filter 52 shown in FIG.
A specific example of Y is to perform the above calculation at an output rate f _S2 to generate a sample sequence {c _n } at a rate of f _S2 from a sample sequence {b _n } at a rate of 2f _s1. Stage shift register 151, data rearrangement circuit 152,
Latch circuits 153A, 153B, 153C, three coefficient generators 154A, 154B, 154C, multiplier 155
A, 155B, 155C, an adder 156 and a latch circuit 157 are provided.

In this rate conversion filter 52Y,
The shift register 151 is serially input with the 2f _s1 rate sample sequence {b _n } shown in FIG. The shift register 151 operates by the 2f _s1 rate clock CK (2f _s1 ) and sequentially delays the 2f _s1 rate sample sequence {b _n }. Then, the 1-clock delay output of the sample sequence {b _n } obtained by the 4-stage shift register 151 [(B) of FIG. 13], 2-clock delay output [(C) of FIG. 13], 3
The clock delay output [(D) of FIG. 13] and the 4-clock delay output [(E) of FIG. 13] are the data rearrangement circuit 1 described above.
It is input to 52 at a rate of 2f _s1 in parallel.

The data rearrangement circuit 152 outputs a 1-clock delay of the sample string {b _n } input in parallel from the shift register 151 at a rate of 2f _s1.
The clock delay output, the 3-clock delay output, and the 4-clock delay output are rearranged at the f _s2 rate, and three kinds of sample sequences {b _n } _A , which are used in the above calculation,
{B _n } _B , {b _n } _C [(F), (G) in FIG. 13,
(H)] is generated. Then, each sample sequence {b of the f _s2 rate generated by the data rearrangement circuit 152
_{n} A, {b n}} B, {b n} C is the latch circuit 15
Multipliers 154A, 1 through 3A, 153B, 153C
54B and 154C.

Further, the coefficient generators 155A and 155
B and 155C sequentially generate the three types of multiplication coefficients A _COEF , B _COEF , and C _COEF used in the above-described calculation at the rate f _s2 . That is, the coefficient generators 155A, 155
The coefficient generator 155A of the B and 155C has a multiplication coefficient A _COEF {h _-9 , h _-8 ,
h _-7 , h _-6 , h _-5 , 0, h _-12 , h _-11 , h _-10 } [(I) of FIG. 13] are sequentially supplied to the multiplier 154A, and the coefficient generator 155B The multiplication coefficient B _COEF of the second term {h ₀ ,
h ₁ , h ₂ , h ₃ , h ₄ , h _-4 , h _-3 , h _-2 , h _-1 }
13 (J) is sequentially supplied to the multiplier 154B, and the coefficient generator 155C causes the multiplication coefficient C _COEF {h ₉ , h ₁₀ , h ₂ , h ₁₁ , h ₁₂ , h 3, 0, h ₅ , h
₆ , h ₇ , h ₈ } [(K) in FIG. 13] is added to the multiplier 15
Supply to 4C sequentially.

Further, each of the multipliers 154A, 154
B and 154C are the latch circuits 12A, 12B and 1 described above.
2C latch outputs, that is, the data rearrangement circuit 1
Each sample sequence {b _n } _A , {b _n } _B , {b _n } _{C of} the f _s2 rate generated by 52 and each multiplication coefficient A _COEF supplied from each coefficient generator 155A, _155B , _155C . The multiplication process for multiplying B _COEF and C _COEF in parallel is sequentially performed at the f _s2 rate. These multipliers 154A,
The output of each multiplication by 154B and 154C is the above-mentioned adder 1
56.

Then, the adder 156 adds the multiplication outputs from the multipliers 154A, 154B, and 154C to obtain a sample sequence {c _n } of f _S2 rate shown in (L) of FIG. c ₀ = h _-9 · b ₁ + h ₀ · b ₀ + h ₉ · b _-1 c ₁ = h _-8 · b ₃ + h ₁ · b ₂ + h ₁₀ · b ₁ c ₂ = h _-7 · b ₅ + h _{2 · b 4 + h 11 · b} 3 c 3 = h -6 · b 7 + h 3 · b 6 + h 12 · b 5 c 4 = h -5 · b 9 + h 4 · b 8 c 5 = h -4 · b 11 _{+ h 5 · b 10 c 6} = h -12 · b 14 + h -3 · b 13 + h 6 · b 12 c 7 = h -11 · b 16 + h -2 · b 15 + h 7 · b 14 c 8 = h - calculating a _{10 · b 18 + h -1 ·} b 17 + h 8 · b 16.

Then, the sample sequence {c _n } of the f _S2 rate generated from the sample sequence {b _n } of the 2f _s1 rate in this way passes through the latch circuit 157 as shown in (M) of FIG. Are sequentially output.

Here, the multiplication coefficients A _COEF , B _COEF , and C _COEF used in the above-described arithmetic processing are as in this specific example.
In the case of f _s2 = 18 f _s1 / 19, the coefficient generator 155 can be made to appear cyclically every 9 clocks of f _s2.
Each of A, 155B and 155C can be easily configured by a shift register as shown in FIG. 14, for example.

The coefficient generator 155 shown in FIG. 14 includes first to third shift registers 161, 16 connected in cascade.
2, 163 and these shift registers 161, 16
A first switch circuit 164 for switching the clocks of 2, 163 and a second switch circuit 165 for switching the output.
And a control circuit 166 for controlling the operation of each of the switch circuits 164 and 165.

The above first to third shift registers 16
1, 162, 163 have respective clock input terminals selectively connected to the first or second clock input terminals 160A, 160B via the first switch circuit 164. A data input terminal of the first shift register 161 is connected to a data output terminal of the first shift register 161 via the second switch circuit 165, a data output terminal of the second shift register 162, The data output terminal of the third shift register 163 or the coefficient data input terminal 160C is selectively connected. Then, the first shift register 161 is
The shift register has six stages, and its data output terminal is connected to the coefficient data output terminal 155C. The second shift register 162 is a three-stage shift register. Further, the third shift register 163
Is a 24-stage shift register.

Here, the first clock input terminal 16
A clock CK (f _S2 ) of f _S2 rate is supplied to 0A, and a load clock LDCKI is supplied to the second clock input terminal 160B from a system controller (not shown). Further, coefficient data COEFI is supplied to the coefficient data input terminal 160C from a system controller (not shown). Further, the control circuit 166 is supplied with a horizontal synchronizing signal HD from the synchronizing signal generator 11 and a mode signal MODEI from a system controller (not shown).

Then, in the coefficient generator 155,
Each of the switch circuits 164 and 165 has a mode signal MODEI supplied from a system controller (not shown).
In accordance with the above, the control circuit 166 controls as follows.

That is, the first switch circuit 164
Selects the load clock LDCKI supplied from the system controller when the camera is activated, and selects the clock CK (f _s2 ) at the f _s2 rate during normal operation.

Further, the second switch circuit 165 is
The coefficient data COEFI supplied from the system controller is selected when the camera is activated, and the output data of the first to third shift registers 161, 162, 163 is selected according to the operation mode during normal operation. In mode 1, the first shift register 16
1 output data is selected, in the case of mode 2, the output data of the second shift register 162 is selected, and
In the case of mode 3, the output data of the third shift register 163 is selected.

In the coefficient generator 155 having such a configuration,
When the camera is activated, coefficient data COEFI necessary for rate conversion at a desired rate conversion ratio is supplied from the system controller to the data input terminal of the first shift register SR1 via the second switch circuit 165. The load clock LDCK is used to perform the synchronous writing to the first to third shift registers 161, 162, 163 in a required number of stages, and coefficient data COE having a desired rate conversion ratio.
FI is set to the first to third shift registers 161, 16
It can be set to 2,163.

In the normal operation, the first to third shift registers 16 described above are selected according to the operation mode.
Coefficient data COEF set to 1,162,163
By circulating I at the f _s2 rate by the clock CK (f _s2 ), it is possible to output the multiplication coefficient COEF necessary for the rate conversion at the desired rate conversion ratio in real time.

That is, in mode 1, the coefficient data COEFI set in the first shift register 161 is set.
By circulating the clock CK (f _S2 ) at the f _S2 rate, f _S2 = 12f _S1 / 13, that is,
The multiplication coefficient COEF required for rate conversion at the rate conversion ratio of 13 → 6 is output.

In the case of mode 2, the above first and second
_{F S2} of the shift register 161, 162 set coefficient data COEFI by the clock CK _{(f S2)}
By circulating at a rate, f _S2 = 18f _S1 /
That is, the multiplication coefficient COEF required for rate conversion at a rate conversion ratio of 19 → 9 is output.

Further, in the case of mode 3, the coefficient data COEFI set in the first to third shift registers 161, 162, 163 is circulated at the rate f _s2 by the clock CK (f _s2 ), so that f _s2 = 33f _s1 / 35 That is, the multiplication coefficient COEF required for rate conversion at the rate conversion ratio of 70 → 33 is output.

The coefficient generator 155 may be composed of a random access memory 171, an address control circuit 172, a control circuit 173, etc., as shown in FIG.

In the coefficient generator 155 shown in FIG. 15, the control circuit 173 performs the following control operation according to the mode signal MODEI supplied from the system controller (not shown).

That is, when the camera is activated, the address control circuit 172 is controlled so as to generate the write address according to the load clock LDCK supplied from the system controller (not shown), and the write control of the random access memory 171 is performed. In addition, at the time of normal operation, f _s2 rate of the clock CK (f
The address control circuit 172 is controlled so as to generate a read address according to _s2 ), and the random access memory 171 is read.

Then, the random access memory 17
When the camera is activated, coefficient data COEFI required for rate conversion at a desired rate conversion ratio is written in 1 from the system controller (not shown) via the control circuit 173. During normal operation, the coefficient data COEFI set in the random access memory 171 is clocked by the clock CK (f _s2 ) according to the operation mode.
_Is repeatedly read at the f _s2 rate, and the multiplication coefficient COE necessary for the rate conversion at the desired rate conversion ratio in real time is obtained.
F is output via the latch circuit 174.

[0136] In addition, the rate conversion circuit 50C for color difference signal in this embodiment, as described above, f _S1 rate digital color difference signals _{C R (f S1), C} B (f S1) and 2f _S1
It is treated as a digital point sequential color difference signal C _R / C _B of the rate, and f _s2 = 18 f _s1 / 19, that is, 19
The operation in the case of the rate conversion ratio of 9 is shown in FIG. 16 and FIG.
As shown in the time chart of No. 7, as in the case of the rate conversion circuit 50Y for the luminance signal described above, in principle, m and n are positive integers and f _S2 = f _S1 · n / m has a frequency of 2 m. → Perform rate conversion of n.

The rate conversion filter 53C of the color difference signal rate conversion circuit 50C can have the same structure as the rate conversion filter 52Y of the luminance signal rate conversion circuit 50Y described above, and as shown in FIG. Four-stage shift register 251, data rearrangement circuit 252, latch circuits 253A, 253B, 253C, three multipliers 2
54A, 254B, 254C, coefficient generators 255A, 2
55B, 255C, adder 256 and latch circuit 257
It is composed of

As shown in FIG. 19, each of the coefficient generators 255A, 255B, 255C of the rate conversion filter 53C has first to third shift registers 261, 262, 263 connected in cascade and each of them. First to switch clocks of shift registers 261, 262, 263
Switch circuit 264, a second switch circuit 265 for switching the output, and the switch circuits 264, 265.
20 and a control circuit 266 for controlling the above operation, or as shown in FIG. 20, a random access memory 271, an address control circuit 272, a control circuit 273, and the like.

Since these operations are similar to those of the above-mentioned luminance signal rate conversion filter 52Y, the description thereof is omitted.

Here, as described above, for example, m = 19, n
= 9 and rate conversion from 9 to 9 n × 2f _s1 = mf
_In the rate conversion processing of _s2 , the input data string of 2f _s1 rate has a large energy at a frequency of an integral multiple [1 to (n-1)] thereof. Therefore, the rate conversion filter that performs this rate conversion process may have filter characteristics that suppress the carrier components and higher-order carrier sideband components of these frequencies, and have a zero point at the frequency of n × 2f _s1. a first transfer function H ₁ (z ^-1), the product H ₁ between the n × second transfer having respective zero point and below the frequency of the 2f _s1 function ^{_{H 2 (z -1) (z}} -1) × H
_It may have an impulse response of an integer coefficient given in the expanded form of ₂ (z ^-1 ).

That is, it is assumed that the rate conversion filter 52Y for the luminance signal has at least one zero point in n × 2f _s1 and an impulse response of an integer coefficient having two zero points in the vicinity thereof. You can Further, in the rate conversion filter 53C for the color difference signal, n × f _s1
Has at least one zero, and has an integer coefficient impulse response having two zeros in its vicinity.

Then, the first and second transfer functions H ₁
(Z ⁻¹ ), H ₂ (z ⁻¹ ) are, for example, the following first equation and second equation
Given by the formula.

[0143]

[Equation 1]

[0144]

[Equation 2]

The first transfer function H ₁ (z ⁻¹ ) is
(N-1) having the following integer coefficient, for example, H
₁ (z ⁻¹ ) = 1 + z ⁻¹ + z ⁻² + z ⁻³ + z ⁻⁴ +
It is given by z ⁻⁵ + z ⁻⁶ + z ⁻⁷ + z ⁻⁸ . In addition, the second transfer function H ₂ (z ⁻¹ ) is 2 (n−
1) having the following integer coefficient, for example, H ₂ (z ⁻¹ ) = (1 + 2z ⁻¹ + 3z ⁻³ + 4z ⁻³ + 5z ⁻⁴ + 6z ⁻⁵ + 7z ⁻⁶ + 8z ⁻⁷ + 9z ⁻⁸ + z ⁻¹⁶ + 2z ^-15 + 3z ^-14 + 4z ^-13 + 5z ^-12 + 6z ^-11 + 7z ^-10 + 8z ^-9 )-(z ^-7 + 2z ^-8 + z ^-9 ) = 1 + 2z ^-1 + 3z ^-2 + 4z ^-3 + 5z ^-4 + 6z ^-5 + 7z. ^{It is given by -6} + 7z ^-7 + 7z ^-8 + 7z ^-9 + 7z ^-10 + 6z ^-11 + 5z ^-12 + 4z ^-13 + 3z ^-14 + 2z ^-15 + z ^-16 . This allows the rate conversion filter to
The coefficient becomes a 3n-order integer coefficient, and the characteristics shown in FIG. 21 are obtained.
Note that z ⁻¹ is a unit delay operator corresponding to n × 2f _S1 .

Since the data string input to the rate conversion filter has actual samples only every n units with respect to the impulse response of this rate conversion filter, three multipliers are required for actual convolution. . As described above, by operating the rate conversion filter only for suppressing the high-order carrier component of 2f _S1 , the number of multipliers required in the actual circuit can be reduced. Note that the roll-off of the amplitude characteristic becomes blunt near the base band, but it can be corrected in advance by the half band filter.

In the digital camcorder having such a configuration, the image pickup signals R, G, 1B output from the solid-state image sensors 1R, 1G, 1B of the image pickup section 1 driven at the f _S1 rate are used.
B of the predetermined phase is f
Imaging data R, G, B digitized at the _S1 rate and digitized by the analog-to-digital converter 3
Since at least the digital luminance signal Y and the two digital color difference signals C _R and C _B are generated by the first digital operation unit 4 operating at the clock rate related to the f _S1 rate, the image quality can be prevented without causing beat interference. It is possible to obtain a good digital image signal.

Then, as shown in FIG. 22, the operation state of the main part in the recording mode is shown. In the recording mode, the digital luminance signal related to the f _S1 rate generated by the first digital operation part 4 is generated. Y and the digital color difference signals C _R and C _B are transferred to the above-mentioned f by the second digital operation unit 5.
_The digital luminance signal Y related to the _S2 rate and the two digital color difference signals C _R and C _B are converted and supplied to the recording / reproducing unit 7, and the digital luminance signal Y and the digital color difference signal C related to the f _S1 rate are also supplied. _R and C _B are output via the signal processing unit 6 for analog output. Also, as shown in FIG. 23, which shows the operation state of the main part in the reproduction mode, in the reproduction mode, the digital luminance signal Y and the digital color difference signal C related to the f _S2 rate reproduced by the recording / reproducing section 7 are reproduced. _R, C _B digital luminance associated with the f _S1 rate by the second digital processing unit 5 signals Y and two digital color difference signals C _R, C _B
And is output via the signal processing unit 6 for analog output.

That is, in this digital camcorder, the second digital operation unit 5 has a function of bidirectionally performing rate conversion between the data rate associated with the f _S1 rate and the data rate associated with the f _S2 rate. In the recording mode, the digital luminance signal Y generated by the first digital operation unit 4 and the two digital color difference signals C _R and C _B are output via the signal processing unit 6 and the second digital color difference signal is output. The signals Y, C _R , and C _B, which are supplied to the recording / reproducing unit 7 via the arithmetic unit 5 and are reproduced by the recording / reproducing unit 7 in the reproduction mode, are related to the data rate f _S2 . Digital operation unit 7
Is supplied to the signal processing unit via the signal processing unit 6 and the reproduced signal is output via the signal processing unit 6. Therefore, the recording / reproducing unit 7 causes the signal Y of the data rate related to the f _S2 rate,
It is possible to record and reproduce C _R and C _B.

Further, in this digital camcorder, the second digital operation section 5 can set a plurality of rate conversion ratios, and the input data rate signals Y, C _R and C related to the f _S1 rate can be set. _{Since B} is converted into output data rate signals Y, C _R and C _B related to the f _S2 rate, the CCD image sensors 1R and 1 of the image pickup unit 1 are converted.
By using a standard CCD image sensor as G and 1B, it is possible to obtain a digital image signal having a clock rate of D-1 standard or another clock rate.

Also, in this digital camcorder, the first digital operation section 4 causes the 2
A digital luminance signal Y (2f _S1 ) having a rate of f _S1 is generated, and the second digital operation unit 5 performs rate conversion processing of 2f _S1 → f _{S2 on} the digital luminance signal Y (2f _S1 ) and reproduces it. In the mode, the digital luminance signal Y (f _S2 ) of the f _S2 rate supplied from the recording / reproducing unit
On the other hand, since the rate conversion processing of f _S2 → 2f _S1 or f _S2 → 2f _S2 is performed by the second digital operation unit, the configuration of the second digital operation unit can be simplified.

Further, the second digital operation section 5 is
In the recording mode, the signals Y (2f _S1 ), C _R (f _S1 ), and C generated by the first digital operation unit 4 are operated at the clock rates of 2f _S1 , f _S1 , and f _S1.
B (f _S1 ) functions as a Nyquist filter for clock rates of f _S2 , f _S2 / 2 and f _S2 / 2,
In the reproduction mode, the half-band filters 51Y and 52C that operate at the clock rates of 2f _S2 , f _S2 , and f _S2 and exhibit the same frequency characteristics as in the recording mode are shared in the reproduction mode and the recording mode. The signal Y (2 supplied by the rate conversion filters 52Y and 53C via the half-band filters 51Y and 52C.
For f _S1 ), C _R (f _S1 ), and C _B (f _S1 ), a rate conversion process of ₂ f _S1 → f _S2 is performed on the digital luminance signal Y (2f _S1 ) to obtain a digital color difference signal C _R (f _S1). ),
The rate conversion process of f _S1 → f _S2 / 2 is substantially performed on C _B (f _S1 ). By thus sharing the half-band filters 51Y and 52C in the reproduction mode and the recording mode, the configuration of the second digital operation section 5 can be simplified.

Furthermore, the second digital operation unit 5
Is 2f with respect to the signals Y, C _R and C _{B of} the input data rate generated by the first digital operation unit 5.
The output data rates of _{S 1} , f _S1 , f _S1 , f _S2 ,
Band limiting processing is performed by the half-band filters 51Y and 52C having f _S2 / 2 and f _S2 / 2 as pass bands, and 2f _S1 → f by the rate conversion filters 52Y and 53C.
_S2 , f _S1 → f _S2 / 2 or f _S2 / 4, f _S1 → f
_S2 / 2 or _fS2 / 4 rate conversion processing is performed, and n ×
2f _S1 , n × f _S1 , n × f _S1 (n is a positive integer) A low-order linear phase finite-length impulse response that suppresses higher-order sideband components is f _S2 , f _S2 / 2 or f
_{The signal} is output in the form of being downsampled at _S2 / 4, _fS2 / 2 or _fS2 / 4. Further, the pass roll-off characteristics of the rate conversion filters 52Y and 53C are compensated by the characteristics of the half band filters 51Y and 52C. As a result, the rate conversion process can be reliably performed by the second digital operation unit 5 having a simple configuration.

In this digital camcorder, the rate conversion filters 52Y and 53C, which perform rate conversion processing on the signals band-limited by the half band filters 51Y and 52C, are n × 2f _S1 , n ×.
f _S1 , n × f _S1 has at least one zero point, and has an impulse response of an integer coefficient having two zero points in the vicinity thereof, each having three multipliers 154A to 154.
C, 254A to 254C.

Further, the half band filters 51Y, 5 for band limiting the signals Y, C _R , C _{B of} the input data rate generated by the first digital operation unit 4 mentioned above.
2C can be a simple one consisting of the product of partial filters made up of integer coefficients.

Furthermore, in this digital camcorder,
The image pickup signals R, G, B output from the solid-state image sensors 1R, 1G, 1B arranged in the color separation optical system of the image pickup unit 1 adopting the spatial pixel shift method are given predetermined values by the A / D conversion unit 3. It is digitized at the phase f _S1 rate, and is digitalized by the first digital operation unit 4 to at least the 2 f _S1 rate digital luminance signal Y (2f _S1 ) and two digital color difference signals C _R (f _S1 ) and C _{B at the} f _S1 rate, respectively. (F
_S1 ) is generated, and the rate conversion process of 2m → n (m and n are positive integers) is performed by the second digital operation unit 5 capable of setting a plurality of rate conversion ratios n / m, and f _S2 = f _S1・ n /
m rate digital luminance signal Y (f _S2 ) and substantially f _S2 / 2 rate digital color difference signal C _R (f _S2 /
2) and C _B (f _S2 / 2) are generated, the spatial pixel shift method can be adopted to obtain a digital image signal with good image quality without causing beat interference, and the aliasing distortion is small and high. An MTF digital image signal can be obtained.

Furthermore, in this digital camcorder,
The signals Y (2f _S1 ), C _R (f _S1 ), and C _B (f _S1 ) generated by the first digital operation unit 4 are converted into analog signals by the D / A conversion unit 61 of the signal processing unit 6. Luminance signal Y _OUT and analog color difference signals Y _OUT , C _ROUT , C
_{Since BOUT} is output, a high resolution analog image signal and a high MTF digital image signal with little aliasing can be obtained at the same time. In the recording mode, the signal processing unit 6 produces the digital luminance signal Y (2f _S1 ) of the 2f _S1 rate generated by the first digital operation unit 4.
Is analogized and output by the D / A converter 61, and in the reproduction mode, the 2f _S2 rate digital luminance signal Y (2
Since f _S2 ) is analogized and output by the D / A converter 61, a high-resolution analog luminance signal can be obtained in the recording mode and the reproducing mode.

The second digital operation section 5 is
Since the digital luminance signal Y is interfaced by the digital interface 13 at the clock rate of 2f _S2 and the digital color difference signals C _R and C _{B at} the clock rate of f _S2 / 2, respectively, the digital luminance signal Y of 2f _S2 rate (2f _S2 ) And the digital color difference signals C _R (f _S2 / 2) and C _B (f _S2 / 2) of f _S2 / 2 rate can be transmitted and received to and from an external device.

Furthermore, in this digital camcorder,
The signals Y, C _R and C _B generated by the first digital operation unit 4 are converted into D / A conversion units 61 of the signal processing unit 6.
The low-pass filter 6 that performs band limitation processing on the analog color difference signal in the analog encoder 62 that is converted to analog by the analog encoder 62 and is supplied with the analog luminance signal and the analog color difference signal.
First delay compensating circuit 4 for compensating for group delay due to 3, 64
2DLY is provided at the output stage of the luminance signal channel of the second digital process processing circuit 42 of the first digital operation section 4, so that the image pickup signals R by the CCD image sensors 1R, 1G, 1B of the image pickup section 1, By compensating for the delay difference between the luminance signal Y generated from G and B and the color difference signals C _R and C _B , an analog image signal with good image quality can be obtained.

In this digital camcorder, the signals Y, C _R , C _{B of} the output data rate related to the f _S2 rate generated by the second digital operation unit 5 are also used.
Since the second delay compensating circuit 54Y for outputting the same group delay is provided in the rate conversion circuit 50Y for the luminance signal of the second digital operation section 5, the CCD of the image pickup section 1 is provided.
Image pickup signals R by the image sensors 1R, 1G, 1B,
Luminance signal Y and color difference signals C _R and C _B generated from G and _B
It is possible to obtain a digital image signal with good image quality by compensating for the delay difference between and.

Further, in this digital camcorder, the second digital operation section 5 bidirectionally performs rate conversion between the data rate associated with the f _S1 rate and the data rate associated with the f _S2 rate. The second delay compensation circuit 54Y having a function in the external input mode.
The digital luminance signal and the digital color difference signal of the data rate related to the f _S2 rate input via the respective signals Y and C output from the first digital operation unit 4
_R, the f _S1 rate related data rate signals Y having a group delay equal to the group delay of the C _B, C _R, and generates a C _B, supplied to the D / A converter 61 of the signal processing section 6 Therefore, even in the external input mode, it is possible to compensate for the delay difference between the luminance signal Y and the color difference signals C _R and C _B to obtain an analog image signal with good image quality.

[0162]

In the solid-state imaging device according to the present invention digitizes at least one predetermined phase of the f _S1 rate by analog-to-digital conversion unit and image signal output from the solid-state image sensor driven at f _S1 rates , Above f
_At least the digital luminance signal Y is generated by the first digital operation unit operating at the clock rate related to the _S1 rate.
And two digital color difference signals C _R and C _B are generated, a digital image signal with good image quality can be obtained without causing beat interference, and a second rate conversion ratio can be set. The digital operation unit causes the signals Y and C of the input data rate related to the above f _S1 rate to be input.
_{Since R} and C _B are converted into output data rate signals Y, C _R and C _B related to the f _S2 rate, a standard CCD image sensor is used and a D-1 standard clock rate or another clock rate is used. It is possible to obtain the digital image signal of

Further, in the solid-state image pickup device according to the present invention, each image pickup output from a plurality of solid-state image sensors arranged in the color separation optical system by using the spatial pixel shift method and driven at the f _S1 rate. The signal is digitized by the analog-to-digital converter at the f _S1 rate of a predetermined phase, and at least 2f by the first digital calculator.
_S1 rate digital luminance signal Y (2f _S1 ) and two f _S1 rate digital color difference signals C _R (f _S1 ),
The second digital operation unit that generates C _B (f _S1 ) and can set a plurality of rate conversion ratios n / m is 2m → n.
(M and n are positive integers) rate conversion processing is performed, and f _S2 =
Digital luminance signal Y (f _S2 ) at f _S1 · n / m rate
And the digital color difference signal C _{R of} substantially f _S2 / 2 rate
Since (f _S2 / 2) and C _B (f _S2 / 2) are generated, the spatial pixel shift method can be adopted to obtain a digital image signal with good image quality without causing beat interference.
It is possible to obtain a high MTF digital image signal with little aliasing.

Furthermore, in the solid-state image pickup device according to the present invention,
Each signal Y generated by the first digital arithmetic unit
_{(2f S1), C R (} f S1), C B since the (f _S1) and outputs an analog luminance signal and analog color difference signals to analog form by a digital-analog converter, an analog image signal and aliasing distortion of the high-resolution less A high MTF digital image signal can be obtained at the same time.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital camcorder to which the present invention is applied.

FIG. 2 is a block diagram showing a configuration example of a signal processing unit for analog output in the digital camcorder.

FIG. 3 is a block diagram showing another configuration example of a signal processing unit for analog output in the digital camcorder.

FIG. 4 is a block diagram showing a configuration example of a rate conversion circuit for a luminance signal in the digital camcorder.

FIG. 5 is a block diagram showing a connection state of the rate conversion circuit for the luminance signal in a recording mode.

FIG. 6 is a block diagram showing a connection state in a reproduction mode of the rate conversion circuit for the luminance signal.

FIG. 7 is a block diagram showing a configuration example of a rate conversion circuit for color difference signals in the digital camcorder.

FIG. 8 is a block diagram showing a connection state in a recording mode of the rate conversion circuit for the color difference signal.

FIG. 9 is a block diagram showing a connection state in a reproduction mode of the rate conversion circuit for the color difference signal.

FIG. 10 is a spectrum diagram showing the operation of the rate conversion circuit for the luminance signal.

FIG. 11 is a time chart showing the operation of the rate conversion circuit for the luminance signal.

FIG. 12 is a block circuit showing a configuration example of a rate conversion filter in the rate conversion circuit for the luminance signal.

FIG. 13 is a time chart showing the operation of the rate conversion filter for the luminance signal.

FIG. 14 is a block circuit showing a configuration example of a coefficient generator in the rate conversion filter for the luminance signal.

FIG. 15 is a block circuit showing another configuration example of the coefficient generator in the rate conversion filter for the luminance signal.

FIG. 16 is a time chart showing the operation of the rate conversion circuit for the color difference signal.

FIG. 17 is a time chart showing the operation of the rate conversion filter for the color difference signal.

FIG. 18 is a block circuit showing a configuration example of a rate conversion filter in the color conversion signal rate conversion circuit.

FIG. 19 is a block circuit showing a configuration example of a coefficient generator in the rate conversion filter for the color difference signal.

FIG. 20 is a block circuit showing another configuration example of the coefficient generator in the rate conversion filter for the color difference signal.

FIG. 21 is a characteristic diagram showing a specific example of characteristics of the rate conversion filter for the luminance signal.

FIG. 22 is a block diagram showing an operation state of a main part in the recording mode of the digital camcorder.

FIG. 23 is a block diagram showing an operation state of a main part in a reproduction mode of the digital camcorder.

[Explanation of symbols]

1. Image pickup unit 1R, 1G, 1B CCD image sensor 2 Analog signal processing unit 3 A / D converters 3R, 3G, 3B ... A / D converter 4 ... First digital operation unit 5 ... Second digital Calculation unit 6 --- Signal processing unit 7 --- Recording / reproducing unit 41 --- First digital process processing circuit 42- ..... second digital process processing circuit 42DLY ..... first delay compensation circuits 50Y and 50C ... rate conversion circuits 51Y and 52C ... half Band filter 51C ... MPX / DMPX 52Y, 54C ... Rate conversion filter 54Y ...・ ・ ・ Second delay compensation circuit 61 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ D / A converter 62 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Analog encoders 63C _R , 63C _B・ ・ ・ Low pass filter 73 ・..... Digital encoder

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-3-112287 (JP, A) JP-A-4-269091 (JP, A) JP-A-1-259689 (JP, A) JP-A-6- 125561 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 9/09

Claims (7)

(57) [Claims] 1. At least one driven at an f _S1 rate
Individual solid-state image sensors, an analog-to-digital converter that digitizes the image pickup signal output from the solid-state image sensor at a predetermined phase f _S1 rate, and operates at a clock rate related to the f _S1 rate, At least a digital luminance signal Y is obtained from the imaged data digitized by the analog-to-digital converter.
For generating two digital color difference signals C _R and C _B
And the f generated by the first digital calculation unit.
Input data rate signal Y related to _S1 rate,
C _R, the signal _Y output data rate of _{C B} associated with _{f S2 rate,} C R, the change of the filter coefficients to be converted to _{C B}
A solid-state imaging apparatus characterized by comprising a further plurality of rate conversion ratio is the second digital processing unit can be set. 2. The first digital operation unit is 2f
A digital luminance signal Y of _S1 rate is generated, and the second digital arithmetic unit generates 2f _S1 generated by the first digital arithmetic unit.
For the rate digital luminance signal Y, it functions as a Nyquist filter for the clock rate of f _S2 ,
2f _S1 rate of the digital luminance signal Y _{(2f S1)} and a filter for outputting a digital luminance signal Y of the _{2f S1} rate supplied through the filter _{(2f S1)} relative to _{2f S1} → f
_2. The solid-state imaging device according to claim 1, comprising a rate conversion filter that performs the rate conversion process of _S2 , wherein the characteristic of the filter is fixed and the rate conversion ratio of the rate conversion filter can be set freely. 3. The second digital operation unit is the f generated by the first digital operation unit.
Each signal Y (2f at the clock rate related to the _S1 rate
_{For S1} ), C _R (f _S1 ), C _B (f _S1 ), f
_{S2, f S2 / 2, f} S2 / 2 of functions as the Nyquist filter for the clock rate, _{2f S1} rate of the digital luminance signal Y _{(2f S1),} respectively _{f S1} rate digital color difference signals _C R _(f S1), _{C B} (f
_S1 ) and a signal Y (2) supplied through the filter.
f _S1 ), C _R (f _S1 ), and C _B (f _S1 ),
2f _S1 → for digital luminance signal Y (2f _S1 )
The rate conversion process of f _S2 is performed to obtain the digital color difference signal C
_{For R} (f _S1 ), C _B (f _S1 ) , f _S1 → f _S2
2. The solid-state image pickup device according to claim 1, wherein the solid-state image pickup device comprises a rate conversion filter that performs a rate conversion process of / 2, the characteristic of the filter is fixed, and the rate conversion ratio of the rate conversion filter can be freely set. 4. A plurality of solid-state image sensors which are arranged in a color separation optical system by adopting a spatial pixel shift method and are driven at an f _S1 rate, and image pickup signals output from the solid-state image sensor, respectively. An analog-to-digital converter that digitizes at a predetermined phase f _S1 rate, and a digital luminance signal Y (2f _S1 ) at a rate of at least 2 f _S1 from each imaged data digitized by the analog-to-digital converter and a f _S1 rate Two digital color difference signals C _R (f _S1 ), C _B (f
_S1 ) for generating a first digital operation unit, and the f generated by the first digital operation unit.
Each signal Y (2 at the input data rate associated with the _S1 rate
2 m for f _S1 ), (f _S1 ), and C _B (f _S1 ).
→ Performs rate conversion processing of n (m and n are positive integers) and f
_S2 = f _S1.n / m rate digital luminance signal Y
And _{(f S2), f S2 /} 2 rate digital color difference signals _{C R (f S2 / 2)} , C B (f S2 / 2) a plurality of rate conversion ratios n / m is a second configurable to generate a A solid-state imaging device comprising a digital arithmetic unit. 5. The second digital operation unit includes a 2f _S1 generated by the first digital operation unit.
For the rate digital luminance signal Y (2f _S1 ),
It functions as a Nyquist filter for the clock rate of f _S2 and functions as a digital luminance signal Y of 2 f _S1 rate.
A filter outputting (2f _S1 ) and a digital luminance signal Y of 2f _S1 rate supplied through the filter.
A rate conversion filter for performing a rate conversion process of 2f _S1 → f _{S2 with} respect to (2f _S1 ), wherein the characteristics of the filter are fixed and the rate conversion ratio of the rate conversion filter can be freely set. Item 4. The solid-state imaging device according to item 4. 6. The second digital operation unit is the f generated by the first digital operation unit.
Each signal Y (2 at the input data rate associated with the _S1 rate
For f _S1 ), (f _S1 ), and C _B (f _S1 ), f
_{S2, f S2 / 2, f} S2 / 2 of functions as the Nyquist filter for the clock rate, _{2f S1} rate of the digital luminance signal Y _{(2f S1),} respectively _{f S1} rate digital color difference signals _C R _(f S1), _{C B} (f
_S1 ) and a signal Y (2) supplied through the filter.
f _S1 ), C _R (f _S1 ), and C _B (f _S1 ),
2f _S1 → for digital luminance signal Y (2f _S1 )
The rate conversion process of f _S2 is performed to obtain the digital color difference signal C
_{For R} (f _S1 ), C _B (f _S1 ) , f _S1 → f _S2
5. The solid-state image pickup device according to claim 4, wherein the solid-state image pickup device comprises a rate conversion filter that performs a / 2 rate conversion process, the characteristics of the filter are fixed, and the rate conversion ratio of the rate conversion filter can be set freely. 7. The signals Y (2f _S1 ), C _R (f _S1 ), C of the input data rate related to the f _S1 rate generated by the first digital operation unit.
The solid-state imaging device according to claim 1 or 4, further comprising a digital-analog conversion unit that converts _B (f _S1 ) into an analog signal and outputs an analog luminance signal and an analog color difference signal.