JP3128998B2 - Digital camcorder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a charge coupled device (CCD).
The present invention relates to a digital camcorder that generates digitized image data from an imaging signal obtained by a solid-state image sensor such as a CCD image sensor formed by a Charge Coupled Device, and records and reproduces the digital image data. In particular, it converts a data clock of the generated image data. The present invention relates to a digital camcorder having a rate conversion function.

[0002]

2. Description of the Related Art Generally, in a solid-state imaging device using a solid-state image sensor having a discrete pixel structure such as a CCD image sensor as an image pickup means, the solid-state image sensor itself is a sampling system, so It is known that an aliasing component from a spatial sampling frequency is mixed in an imaging signal due to the above. Conventionally,
By providing a birefringent optical low-pass filter in the imaging optical system and suppressing the high-band component of the baseband component of the imaging signal, the Nyquist condition of the sampling system using the solid-state image sensor is satisfied, Of the baseband component is prevented from being generated.

In a color television camera device for picking up a color image, a two-panel type image pickup device for picking up three primary color images by a solid-state image sensor for picking up a green image and a solid-state image sensor provided with a color coding filter for red and blue pixels. 2. Description of the Related Art A solid-state imaging device and a multi-plate solid-state imaging device such as a three-plate solid-state imaging device that captures three primary color images using individual solid-state image sensors have been put to practical use.

Further, as a technique for improving the resolution in the multi-plate solid-state imaging device, a solid-state image sensor for capturing a green image is used only for a half of a spatial sampling period of a pixel for a red image. There is known a spatial pixel shifting method in which a solid-state image sensor for capturing a blue image is shifted. By employing this spatial pixel shifting method, a high resolution exceeding the limit of the number of pixels of the solid-state image sensor can be realized in the analog-output multi-chip solid-state imaging device.

Also, D-1 and D-2 standards have been standardized as standards for professional digital video tape recorders used in broadcasting stations and the like, and digital video related equipment conforming to these standards has been standardized. Digital interfaces are also needed for color television camera devices.

Here, in the D-1 standard which is a standard of 4: 2: 2 digital component video signal, the sampling frequency is set to the horizontal frequency f in the NTSC system.
_{13.5M which} is 858 times _{H (NTSC)} and 864 times the horizontal frequency f _{H (PAL)} in the PAL system.
Hz, and can be locked at an integral multiple of the horizontal frequency in either method. Further, in the D-2 standard is a standard for digital composite video signal, the sampling frequency is four times the 4F _SC subcarrier being adapted to minimize beat interference between the subcarrier and sampling clocks, NTSC scheme Has a sampling frequency f _{S (NTSC)} of 14.3 MHz and a sampling frequency f _{S (PAL)} of the PAL system of 17.734 MHz.

[0007]

When a digital camcorder for recording and reproducing digital image signals conforming to the D-1 and D-2 standards as described above is to be realized, a high resolution and aliasing distortion are required. In order to obtain a good digital image signal with less image quality, the sampling rate (the number of pixels) of the solid-state image sensor used in the imaging unit is determined by the imperfections of an optical low-pass filter that is a pre-filter for the solid-state image sensor. That is,
Considering that it is difficult to achieve both good MTF characteristics and low aliasing distortion components with the optical low-pass filter, which provides only a gentle roll-off characteristic, considering the D-1 standard and D -2 standard must be higher than the sampling rate.

[0008] In addition, in consideration of digital processing such as defect correction processing for each pixel of the solid-state image sensor, and prevention of occurrence of beat disturbance with respect to the image pickup signal of the solid-state image sensor, It is desirable that the sampling rate match the sampling rate in the analog-to-digital converter for digitizing the image signal from the solid-state image sensor.

In this case, the current most standard CCD image sensor is driven at a clock rate of 14.3 MHz = f _{SC (NTSC)} , and digital processing using this CCD image sensor as an image pickup unit is performed. In the camera,
The imaging signal output from the solid-state image sensor is digitized at a clock rate of 14.3 MHz = f _{SC (NTSC)} and subjected to digital signal processing.

However, as described above, the clock rate in the D-1 standard, which is the standard of 4: 2: 2 digital component video signal, is that the luminance signal Y is 13.5 MHz and the color difference signals C _R / C _B are 6. There is a problem that it cannot be matched with a clock rate in a digital processing camera using the above-mentioned standard CCD image sensor as an imaging unit. If a CCD image sensor with a read rate of 13.5 MHz is newly manufactured to comply with the D-1 standard, there are problems in terms of cost and versatility.

[0011] In the multi-plate type digital camcorder that employs a spatial pixel shifting method in the imaging unit, unless a signal processing system that operates at twice the clock rate 2f _S1 of the CCD image sensor relative to the clock rate f _S1 , Cannot increase the resolution of analog output. In the signal processing system, after signal processing is performed at f _S1 and 2f _S1 , analog processing is performed once at f _S1 or 2f _S1 , processing is performed by an analog filter, and then digitalization is again performed at a clock rate according to the D-1 standard. Although it is conceivable, 14.3 MHz system and 13.5 MHz system
Beat interference occurs with the MHz system, causing image quality degradation.

In view of the above situation, the present invention provides a digital camcorder that records and reproduces a digital image signal of a D-1 standard clock rate or another clock rate using a standard CCD image sensor. The purpose is to provide.

It is another object of the present invention to provide a digital camcorder capable of obtaining a digital image signal of good image quality without causing a beat disturbance by using a signal processing system operating at the same clock rate as that of a CCD image sensor. I do.

Further, by adopting a spatial pixel shifting method, a high resolution analog image signal and a high MT with little aliasing distortion are obtained.
An object of the present invention is to provide a digital camcorder that can simultaneously obtain a digital image signal of F.

It is another object of the present invention to simplify the configuration of a digital camcorder.

[0016]

In order to achieve the above object, a digital camcorder according to the present invention has at least one solid-state image sensor driven at an f _S1 rate and outputs from the solid-state image sensor. An analog-to-digital converter for digitizing an image signal at an f _S1 rate of a predetermined phase; and operating at a clock rate related to the f _S1 rate to obtain at least a digital luminance from the image data digitized by the analog-to-digital converter. A signal Y and two digital color difference signals C _R and C _B
, A digital luminance signal Y of data related to the f _S1 rate and two digital color difference signals C _R and C _B generated by the first digital operation unit. a signal processing unit, the rate in both directions between the recording and reproducing unit to be interfaced with a clock rate related to f _S2 rate, as data rate associated with the data rate and the f _S2 rate associated with the f _S1 rate A data rate connected to the first digital operation unit, the signal processing unit, and the recording / reproducing unit, the data rate being related to the f _S1 rate generated by the first digital operation unit; Signals Y, C _R , C
_B is a signal Y, at a data rate related to the _fS2 rate.
C _R, and converted into C _B is supplied to the recording and reproducing unit, related signal in data rate associated with the f _S2 rates supplied from the recording reproduction unit Y, C _R, and C _B to the f _S1 Rate signal Y of the data rate, and converts C _R, the C _B is characterized in that comprising a second digital processing unit supplying to the signal processing unit.

Further, the digital camcorder according to the present invention, in the recording mode, the first digital luminance signal Y and two digital color difference signals C _R generated by the digital processing unit, the C _B via the signal processing unit The signal Y, C _R at the data rate related to the f _S2 rate reproduced by the recording / reproducing unit in the reproducing mode is supplied to the recording / reproducing unit via the second digital operation unit. , C _B are supplied to the signal processor via the second digital processing unit, and is characterized in that the reproduction signal through the signal processing unit is output.

Further, the digital camcorder according to the present invention generates a digital luminance signal Y (2f _S1 ) at a rate of 2f _{S1 in} the recording mode, and the second digital arithmetic unit generates the digital luminance signal Y (2f _S1 ). 2f _S1
→ It is characterized by including the above-mentioned first digital operation unit for performing the rate conversion processing of f _S2 .

Further, in the digital camcorder according to the present invention, the f supplied from the recording / reproducing section in the reproducing mode.
_S2 rate of the digital luminance signal Y (f _S2) with respect to f _S2
→ It is characterized by including the above-mentioned second digital operation unit for performing 2f _S1 rate conversion processing.

Further, in the digital camcorder according to the present invention, the f supplied from the recording / reproducing section in the reproducing mode.
_S2 rate of the digital luminance signal Y (f _S2) with respect to f _S2
→ It is characterized by including the above-mentioned second digital operation unit for performing 2f _S2 rate conversion processing.

Also, in the digital camcorder according to the present invention, the signal processing section includes a digital-to-analog conversion section, and in a recording mode, the digital luminance signal Y of 2f _S1 rate generated by the first digital operation section.
(2f _S1 ) is converted into an analog signal and output. In the reproduction mode, 2f _S1 generated by the second digital operation unit is output.
The digital luminance signal Y (2f _S2 ) at the _S2 rate is converted into an analog signal and output.

Further, the digital camcorder according to the present invention, when the recording mode, the digital luminance signal Y (2f _S1), respectively f _S1 rate digital color difference signals C _R (f _S1) of the 2f _S1 rate, C _B (f _S1 ), And the digital luminance signal Y (2f
Performs rate conversion processing 2f _S1 → f _S2 relative to _S1), digital color difference signals C _R (f _S1), the rate conversion processing substantially f _S1 → f _S2 / 2 relative to C _B (f _S1) And a second digital operation unit for performing the above operation.

Further, the digital camcorder according to the present invention performs the rate conversion processing of f _S2 → 2f _{S1 on} the digital luminance signal Y (f _S2 ) of the f _S2 rate in the reproduction mode, and performs the f _S2 / 2 rate conversion. Digital color difference signal C _R (f _S2 /
2), f _S2 / 2 → f substantially with respect to C _B (f _S2 / 2)
It is characterized by including the above-mentioned second digital operation unit for performing the rate conversion processing of _S1 .

Further, the digital camcorder according to the present invention performs a rate conversion process of f _S2 → 2f _{S2 on} the digital luminance signal Y (f _S2 ) at the f _S2 rate in the reproduction mode, and performs the f _S2 / 2 rate conversion. Digital color difference signal C _R (f _S2 /
2), f _S2 / 2 → f substantially with respect to C _B (f _S2 / 2)
It is characterized by including the above-mentioned second digital operation unit for performing the rate conversion processing of _S2 .

Also, in the digital camcorder according to the present invention, the signal processing section includes a digital-to-analog converting section, and in the recording mode, the digital luminance signal Y of 2f _S1 rate generated by the first digital calculating section.
(2f _S1) and f _S1 rate digital color difference signals C _R (f
_S1 ) and C _B (f _S1 ) are converted to analog and output. In the reproduction mode, the digital luminance signal Y (2f _S2 ) of the 2f _S2 rate generated by the second digital arithmetic unit and f (2f _S2 ) are output.
_S2 rate digital color difference signals C _R (f _S2 ), C _B (f
_S2 ) is analogized and output.

Further, in the digital camcorder according to the present invention, in the recording mode, the signals Y (2f _S1 ), C _R (f _S1 ), C _R (f _S1 ) generated by the first digital arithmetic unit are generated.
_B (f _S1 ) operates at a clock rate of 2 f _S1 , f _S1 , f _S1 , functions as a Nyquist filter for clock rates of f _S2 , f _S2 / 2, f _S2 / 2, and 2 f _S2 , a filter operating at a clock rate of f _S2 , f _S2 and exhibiting the same frequency characteristics as in the recording mode, and each signal Y (2f _S1 ) and C _R (f _S1 ) supplied through the filter during the recording mode for C _B (f _S1), 2f the digital luminance signal Y (2f _{S1) S1}
→ Perform the rate conversion process of f _S2 and
_R (f _S1 ) and C _B (f _S1 ) are substantially f _S1 → f _S2
The second digital arithmetic unit includes a rate conversion filter for performing a rate conversion process of / 2, and the filter is shared between the reproduction mode and the recording mode.

The digital camcorder according to the present invention is characterized in that the signal processing unit includes a third digital operation unit that operates at a clock rate related to the f _S1 rate.

Further, in the digital camcorder according to the present invention, a digital luminance signal Y to the outside is 2 at a node between the second digital operation section and the recording / reproducing section.
The digital color difference signals C _R and C _B at a clock rate of f _S2
Are provided with digital interfaces each having a clock rate of f _S2 / 2.

[0029]

In the digital camcorder according to the present invention, f _S1
An image signal output from at least one solid-state image sensor driven at a rate is digitized by an analog-to-digital converter at a f _S1 rate of a predetermined phase, and at least a digital signal is obtained from the image data digitized by the analog-to-digital converter. The luminance signal Y and the two digital chrominance signals C _R and C _B are generated by a first digital operation unit that operates at a clock rate related to the f _S1 rate. In addition, the second digital operation unit calculates f
Has a function of performing bidirectional rate conversion between the data rate associated with associated data rate and f _S2 rate to _S1 rate, related to the f _S1 rates generated by the first digital processing unit Signals Y and C at the selected data rate
Supplies _R, signal Y in data rate associated with the f _S2 rates C _B, C _R, the recording and reproducing unit are converted into C _B, also associated with the f _S2 rates supplied from the recording reproducing unit signal Y of the data rate, and supplies C _R, a C _B signal Y in data rate associated with the f _S1 rate, C _R, to the signal processing unit are converted into C _B. Further, the recording and reproducing unit is interfaced with a clock rate related to f _S2 rate, performs signal in data rate associated with the f _S2 rate Y, C _R, the recording and reproducing of C _B.

A digital camcorder according to the present invention
In the recording mode, the first digital arithmetic unit
Digital luminance signal Y and two digital signals
Color difference signal C_R, C_BIs output via the signal processing unit.
And via the second digital operation unit
Supply to the recording / playback unit, and in the playback mode, the recording / playback unit
F reproduced by_S2Data rate associated with rate
Signal Y, C_R, C _BIn the second digital operation unit
Through the signal processing unit, and through the signal processing unit.
And outputs a reproduction signal.

Also, in the digital camcorder according to the present invention, in the recording mode, the first digital operation section generates a digital luminance signal Y (2f _S1 ) of the 2f _S1 rate, and the second digital operation section generates the digital luminance signal Y (2f _S1 ). The rate conversion processing of 2f _S1 → f _S2 is performed on the digital luminance signal Y (2f _S1 ).

Further, in the digital camcorder according to the present invention, in the reproduction mode, the digital luminance signal Y (f _S2 ) of the f _S2 rate supplied from the recording / reproducing unit is subjected to f
The rate conversion processing of _S2 → 2f _S1 or f _S2 → 2f _S2 is performed by the second digital arithmetic unit.

In the digital camcorder according to the present invention, in the recording mode, the signal processing section converts the 2f _S1 rate digital luminance signal Y (2f _S1 ) generated by the first digital operation section into a digital-to-analog signal. Unit, and outputs the analog signal. In the reproduction mode, 2f generated by the second digital arithmetic unit is output.
The digital luminance signal Y (2f _S2 ) of the _S2 rate is converted into an analog signal by the digital-to-analog converter and output.

Further, in the digital camcorder according to the present invention, in the recording mode, the first digital arithmetic unit performs the 2f _S1 rate digital luminance signal Y (2f _S1 ).
And a digital color difference signal C of f _S1 rate respectively.
_R (f _S1), to generate a C _B (f _S1), the second digital processing unit performs the rate conversion processing 2f _S1 → f _S2 with respect to the digital luminance signal Y (2f _S1), digital color difference signal C _R (f _S1), performs substantially the f _S1 → rate conversion processing f _S2 / 2 relative to C _B (f _S1).

Further, in the digital camcorder according to the present invention, the playback mode, the above by the second digital processing unit, rate conversion processing f _S2 → 2f _S1 against f _S2 rate of the digital luminance signal Y (f _S2) It was carried out, f _S2 / 2 rate digital color difference signals _{C R (f S2 / 2)} , C B (f
_S2 / 2) performs rate conversion of substantially f _S2 / 2 → f _S1 respect.

Further, in the digital camcorder according to the present invention, the playback mode, the above by the second digital processing unit, rate conversion processing f _S2 → 2f _S2 relative to f _S2 rate of the digital luminance signal Y (f _S2) It was carried out, f _S2 / 2 rate digital color difference signals _{C R (f S2 / 2)} , C B (f
_S2 / 2) performs rate conversion of substantially f _S2 / 2 → f _S2 respect.

Further, in the digital camcorder according to the present invention, the signal processing unit, the recording mode of the digital luminance signal Y (2f _S1) and f _S1 rate of 2f _S1 rates generated by the first digital processing unit The digital color difference signals C _R (f _S1 ) and C _B (f _S1 ) are converted into analog signals by a digital-to-analog conversion unit and output. In the reproduction mode, the 2f _S2 rate digital luminance signal Y generated by the second digital calculation unit is used. (2f _S2 ) and f _S2
Rate digital color difference signals C _R (f _S2 ), C
_B (f _S2 ) is converted into an analog signal by a digital-to-analog converter and output.

In the digital camcorder according to the present invention, the second digital operation section operates at a clock rate of 2f _S1 , f _S1 , f _{S1 in} the recording mode, and is generated by the first digital operation section. Each of the signals Y (2f _S1 ), C _R (f _S1 ), and C _B (f _S1 ) functions as a Nyquist filter with respect to a clock rate of f _S2 , f _S2 / 2, f _S2 / 2. A filter operating at a clock rate of 2f _S2 , f _S2 , and f _S2 and exhibiting the same frequency characteristics as in the recording mode is shared between the reproduction mode and the recording mode. In the recording mode, the filter is used by the rate conversion filter. For each of the signals Y (2f _S1 ), C _R (f _S1 ), and C _B (f _S1 ) supplied via the digital luminance signal Y (2f _S1 ), 2f _S1
→ Perform the rate conversion process of f _S2 and
_R (f _S1 ) and C _B (f _S1 ) are substantially f _S1 → f _S2
/ 2 rate conversion processing.

Further, in the digital camcorder according to the present invention, the signal processing section performs signal processing by a third digital operation section that operates at a clock rate related to the f _S1 rate.

Further, in the digital camcorder according to the present invention, the second digital operation section uses a digital interface to output a digital luminance signal Y of 2
The digital color difference signals C _R and C _B at a clock rate of f _S2
Are each interfaced at a clock rate of f _S2 / 2.

[0041]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a digital camcorder according to the present invention will be described below in detail with reference to the drawings. A digital camcorder according to the present invention is configured, for example, as shown in FIG.

The digital camcorder shown in FIG.
The imaging signal obtained by the imaging unit 1 is digitized to
The present invention is applied to a digital camcorder that records as image data conforming to the I.1 standard, and an analog-to-digital conversion in which three primary color image pickup signals R, G, and B obtained by an image pickup section 1 are supplied via an analog signal processing section 2. Part 3,
A first digital operation unit 4 to which each color image data R, G, B digitized by the analog / digital (A / D) conversion unit 3 is supplied, and a digital luminance generated by the first digital operation unit 4 A recording section for storing and reproducing image data conforming to the D1 standard, including a second digital operation section 5 and a signal processing section 6 for analog output to which a signal Y and two digital color difference signals C _R and C _B are supplied; The reproduction unit 7 is connected to the second digital operation unit 5.

The image pickup section 1 separates image pickup light incident from an image pickup lens (not shown) via an optical low-pass filter into three primary color light components by a color separation prism, and captures three primary color images of a subject image. It comprises CCD image sensors 1R, 1G and 1B.

In this embodiment, the three CCD image sensors 1R, 1G, and 1B employ a spatial pixel shifting method to capture a green image.
In contrast, CCD image sensors 1R and 1B for red image capturing and blue image capturing are shifted from each other by ず ら of the spatial sampling period τ _s of pixels.

It should be noted that the present invention is not limited to a digital camcorder having a three-chip image pickup unit employing the spatial pixel shifting method as in this embodiment, but may be applied to a single-chip or two-chip image pickup unit or space. The present invention can also be applied to a digital camcorder having an imaging unit of another imaging method such as a three-plate imaging unit that does not employ the pixel shifting method.

The three CCD image sensors 1R, 1
G and 1B are generated at a f _S1 rate by a drive clock CK (f _S1 ) generated by a timing generator (TG) 9 based on a 2 f _S1 rate clock CK (2 f _S1 ) provided by a voltage controlled oscillator (VCO) 8. Driven.

Here, the three CCD image sensors 1R, 1G, and 1B have f _S1 = 910f _H , C in EIA.
In the CIR, the number of pixels is selected so that imaging charges are read at a rate of f _S1 = 912 f _H. Then, the oscillation frequency of the VCO 8 is set to 2f _S1 , and the TG 9 generates the drive clock CK of the f _S1 rate obtained by dividing the clock CK (2f _S1 ) by １ ／.
(F _S1 ), the three CCD image sensors 1R,
1G and 1B are driven.

The CCD image sensors 1R, 1G, 1
Each color imaging signal R read out from B at f _S1 rate
(F _S1 ), G (f _S1 ), and B (f _S1 ) are supplied to the analog signal processing unit 2.

The analog signal processing unit 2 includes a correlated double sampling (CDS) processing circuit 21R, 21G, 21B and a level control circuit 22.
R, 22G, and 22B, and performs correlated double sampling processing on each of the color image pickup signals R, G, and B read out from the CCD image sensors 1R, 1G, and 1B at the f _S1 rate. , 21G, 21
B, and level control such as white balance and black balance is performed by the level control circuits 22R, 22G, and 22B.

The A / D converter 3 to which the color imaging signals R (f _S1 ), G (f _S1 ), and B (f _S1 ) obtained by the imaging unit 1 are supplied via the analog signal processing unit 2 is used. , Three A / D converters 3R, 3G, each having a 10-bit word length,
3B. Each of these A / 8 converters 3R, 3G, 3B
Include the respective color image pickup signals R (f _S1 ), G (f _S1 ), B
Drive clock having a predetermined phase equal f _S1 rate to the sampling rate of _{(f S1) CK (f S1} ) is the TG
9. Then, the analog-digital converter unit 3, the A / D converter 3R, 3G, by 3B, the f _S1 rates of each color imaging signals _{R (f S1), G (} f
_S1), B (the f _S1) and digitized at f _S1 rates predetermined phase by the driving clocks CK (f _S1), the respective color image pickup signals _{R (f S1), G (} f S1), B (f S1 ) Each digital color signal R having the same signal spectrum as the spectrum
(F _S1 ), G (f _S1 ) and B (f _S1 ) are formed.

Each of the A / D converters 3R, 3G,
As the 3B, a word having a word length of about 12 to 14 bits may be used as necessary.

Then, each color image data R (f _S1 ) of the f _S1 rate digitized by the A / D converter 3 is obtained.
G (f _S1 ) and B (f _S1 ) are supplied to the first digital operation section 4.

The first digital operation unit 4 comprises a first digital process processing circuit 41 and a second digital process processing circuit 42.

The first digital process processing circuit 4
1 is the drive clock CK (f) supplied from the TG 9
_S1 ), the A / D converter 3 operates at the _fS1 rate.
Digital color signals R (f _S1 ), G (f
_S1 ) and B ( _fS1 ) are detected by detecting various correction signal levels, and for example, white balance control data, black balance control data, black shading correction data, white shading correction data, defect correction data, and the like are stored in the memory 43. D / A converters 44R, 44G, 4 for each color signal.
4B, and is fed back to the level control circuits 22R, 22G, 22B of the analog signal processing unit 2 to perform image processing such as black-and-white balance control, shading correction, and defect correction.

The memory 43 is composed of an SRAM, and a battery 45 is connected as a backup power supply.

As described above, in this embodiment, the CCD
Each color image pickup signal R (f _S1 ), G (f _S1 ), B (f) read from the image sensors 1R, 1G, 1B at the f _S1 rate.
Each color imaging data R obtained may f _S1 rates _S1) and digitized at f _S1 rate the A / D converter 3
Since (f _S1 ), G (f _S1 ), and B (f _S1 ) are obtained, the first digital process processing circuit 41 is operated at the f _S1 rate to obtain an image in pixel units such as shading correction and defect correction. Processing can be performed.

Further, the second digital process processing circuit 42 is provided with the first digital process processing circuit 4.
The digital color signals R, G, and B that have undergone image processing in units of pixels are subjected to image enhancement processing, pedestal addition, non-linear processing such as gamma and knee processing, and linear matrix processing. Digital color signals R (f _S1 ), G (f _S1 ), B
Digital luminance signal Y (2f _S1) and two digital color difference signals C _R (f _S1) from (f _S1), to produce a C _B (f _S1).

Here, the second digital process processing circuit 42 is supplied with the clock CK (2f _S1 ) of the 2f _S1 rate from the VCO 8 and the TG 9
Supplies a driving clock CK (f _S1 ) of the f _S1 rate, and these clocks CK (2 f _S1 ) and CK
(F _S1 ) is used as a master clock to perform a well-known high-resolution process corresponding to the spatial pixel shifting method in the imaging unit 1, and obtains the digital color signals R (f _S1 ),
G (f _S1), from B (f _S1), generating a 2f _S1 rate of the digital luminance signal Y (2f _S1), each of f _S1 rate digital color difference signals C _R (f _S1), a C _B (f _S1) I do.

The master clock CK (2
f _S1 ) and CK (f _S1 ) are also supplied to a synchronization signal generator (SG) 11 that forms various synchronization signals such as a horizontal synchronization signal HD and a vertical synchronization signal VD.

Further, the second digital operation unit 5 includes:
and performs bidirectional rate conversion between signals in data rate associated with the signal and f _S2 rate related data rate f _S1 rate, the recording mode is generated by the first digital processing unit 4 The signals Y (2f _S1 ), C _R (f _S1 ) of the data rate related to the above f _S1 rate,
C _B signal data rate of (f _S1) associated with the f _S2 rate _{Y (f S2), C R} (f S2 / 2), C B (f S2 /
The signal Y (f _S2 ), C _R (f) at the data rate related to the f _S2 rate supplied from the recording / reproducing unit 7 is supplied in the reproducing mode.
_S2 / 2) and C _B (f _S2 / 2) are converted into signals (2f _S1 ), C _R (f _S1 ), and C _{B of} the data rate related to the f _S1 rate.
(F _S1 ) and converted into the analog output signal processing unit 6
To supply.

The second digital operation unit 5 comprises a rate conversion circuit 50Y for a luminance signal and a rate conversion circuit 50C for a color difference signal.

Further, a digital interface 13 for an external device is provided between the second digital operation unit 5 and the recording / reproducing unit 7, and the second digital operation unit 5 operates in the external input mode. Digital return signals Y (f _S2 ), C _R (f _S2 /) at a data rate related to the f _S2 rate input from the digital camera control unit (D-CCU) 14 via the digital camera adapter (D-CA) 15 2), C _B
(F _S2 / 2) is converted into signals Y (2f _S1 ), C _R (f _S1 ), and C _B (f _S1 ) of the data rate related to the f _S1 rate, and the signal processing section 6 for analog output is converted. It can be supplied to.

In this embodiment, the signal processing section 6 for analog output is provided with a data rate related to the f _S1 rate generated by the first digital operation section 4 or the second digital operation section 5. Signal Y (2
f _S1 ), C _R (f _S1 ), and C _B (f _S1 ), and functions as an analog interface. The digital / analog (D / A) conversion unit 61 and the analog encoder 62
Consists of

[0064] The D / A converter 61 are respectively three D / A converters 61Y, 61C _R, 61C _B and postfilter 61PFY, 61PFC _R, consists 61PFC _B.

In the D / A converter 61, the digital luminance signal Y (2f _S1 ) at the 2f _S1 rate is converted to the D / A signal.
The sampling carrier component is removed by a post filter 61Y which is converted into an analog signal by the converter 61Y and functions as a Nyquist filter, and is supplied to the analog encoder 62. Further, the digital color difference signals C _R (f _S1 ) and C _B (f _S1 ) of the f _S1 rate are respectively obtained by the above D
/ A converter 61C _R, is analog by 61C _B,
The sampling carrier components are removed by post filters 61PFC _R and 61PFC _B each functioning as a Nyquist filter.
Supplied to

[0066] Further, the analog encoder 62 is an encoder conforming to the usual NTSC or PAL, component signal Y, C _R, C _B and outputs the composite signal CS, the monitor signal is supplied to the view finder 16 It has a function to output _YVF .

The analog encoder 62 is configured, for example, as shown in FIG.

In the analog encoder 62, the two analog color difference signals C _R and C _B supplied from the D / A converter 61 are respectively supplied to a low-pass filter 63.
C _R, is band-limited to a predetermined band (fc ≒ 1 MHz) by 63C _B, the signal combiner 64C _R, burst flag BF is supplied to the modulator 65 after being added by 64C _B. The modulator 65 outputs the analog color difference signal C _R ,
The quadrature two-phase subcarrier SC is modulated by C _B to generate a modulated chroma signal C _OUT .

On the other hand, the analog luminance signal Y supplied from the D / A converter 61 is
After the amount of delay due to C _R and 63 C _B is compensated for by the delay circuit 66, a synchronizing signal and a setup signal are added by the signal combiner 67, so that the specified luminance signal Y
_OUT . The luminance signal Y _OUT thus obtained
The resolution is improved by digital processing according to the spatial pixel shifting method described above, and aliasing distortion is reduced.

Then, the luminance signal Y _OUT and the modulated chroma signal C _OUT are mixed by the signal mixer 68 to generate a composite signal CS _OUT .

The luminance signal Y _OUT is obtained by converting a character signal from the character generator 69 into a signal mixer 7.
After being mixed by 0, it is output as the monitor signal Y _VF via the switching circuit 71. The switching circuit 71 includes a return signal RET input from the outside and the luminance signal Y.
_Switch to _OUT .

Here, the analog output signal processing unit 6 is replaced by a third digital operation unit operating at a clock rate related to the f _S1 rate, as shown in FIG. Using a digital encoder 73, the digital luminance signal Y _OUT , digital composite signal CS _OUT , and digital monitor signal Y _VF generated by the digital encoder 73 are converted into analog signals by D / A converters 74Y, 74CS, and 75Y _VF , respectively. 74PFY, 74PFC
S, 75PFY It may be configured to output via VFY _VF .

[0073] Further, in this embodiment, the second digital processing unit 5, bidirectional rate conversion between signals in data rate associated with the signal and f _S2 rate in data rate associated with f _S1 Rate In principle, in the recording mode, the digital luminance signal Y of the 2f _S1 rate is used.
(2f _S1 ) is converted to the digital luminance signal Y of f _S2 rate.
While rate conversion (f _S2), f _S1 rate digital color difference signals C _R (f _S1), respectively, C _B (f _S1) and f _S2 / 2 rate digital color difference signals C _R (f _S2 /
2), the rate is converted to C _B (f _S2 / 2), and the digital luminance signal Y (f _S2 ) of the f _S2 rate is converted to 2 in the reproduction mode.
while rate conversion f _S1 rate of the digital luminance signal Y (2f _S1), respectively f _S2 / 2 rate digital color difference signals _{C R (f S2 / 2)} , C B and (f _S2 / 2) f _S1
Rate digital color difference signals C _R (f _S1 ), C
_B (f _S1 ). In order to simplify the configuration of each of the rate conversion circuits 50Y and 50C, the digital luminance signal Y of the f _S2 rate is used in the reproduction mode.
(F _S2) of 2f _S2 rate of the digital luminance signal Y (2f
While rate conversion _S2), the digital color difference of f _S2 / 2 rate signals _{C R (f S2 / 2)} , C B (f S2
/ 2) is the digital color difference signal C of the f _S2 rate.
_The rate is converted to _R (f _S2 ) and C _B (f _S2 ).

The clock of the D / A converter 61 is also switched to 2f _S2 , f _S2 , f _S2 in the reproduction mode. Even in this case, f _S1 and f _S2 are fairly close frequency, post-filter 61PFY of the D / A conversion unit 61, 61PFC _R, 61PFC _B can be shared without switching characteristics.

As for the word length, the signals Y, C _R ,
For C _B , about 10 bits are sufficient, but for the signals Y, C _R , and C _B supplied to the second digital operation unit 5,
It is desirable to set one or two more bits in consideration of rounding in the rate conversion circuit.

Therefore, in this embodiment, the first digital operation unit 4 uses the 11-bit signals Y, C _R , C _B
, And the upper 10-bit signals Y, C
_R, and C _B are supplied to the D / A converter 61. Then, in the second digital operation unit 5, two to three
An operation with more bits is performed, and rounded to 10 bits at the final stage.

Next, specific examples of the rate conversion circuit 50Y for a luminance signal and the rate conversion circuit 50C for a chrominance signal constituting the second digital operation section 5 will be described.

The rate conversion circuit 50Y for the luminance signal
Is a half-band filter 51Y, as shown in FIG.
A rate conversion filter 52Y, a rounding circuit 53Y, a delay compensation circuit 54Y, a zero insertion circuit 55Y, and first to sixth switching circuits 56Y _{1 to} 56 for switching input and output thereof.
It is constituted by Y _6.

In the recording mode, the rate conversion circuit 50Y, as shown in FIG.
Switching circuit 56Y ₁ ~~56Y ₆ of is set.

That is, in the recording mode, the digital luminance signal Y (2f _S1 ) of the 2f _S1 rate generated by the first digital operation section 4 is input to the half-band filter 51Y, and the rate conversion filter 52Y and the rounding process are performed. circuit 53Y, by being passed through the delay compensating circuit 54Y in this order, f _S2 rate of the digital luminance signal Y (f
_S2 ).

The half band filter 51Y has a 2f
_For the digital luminance signal Y (2f _S1 ) of the _S1 rate,
It has an output data rate of 2f _S1 and a pass band of f _S2 , and has the characteristic of functioning as a Nyquist filter for the f _S2 rate. In this embodiment, 0 ± 0.1 d
B (〜5.75 MHz), <−12 dB (〜6.75 M)
Hz), <−40 dB (8.0 MHz).

The rate conversion filter 52Y is
2 supplied via the half-band filter 51Y
Among the higher-order carrier components included in the digital luminance signal Y (2f _S1 ) of the f _S1 rate, 1 to n−1 are suppressed.
The rate conversion filter 52Y includes an equalization filter that operates at the 2f _S1 rate and compensates for attenuation in the band of the half-band filter 51Y.

The digital luminance signal Y of the f _S2 rate obtained by the rate conversion filter 52Y is obtained.
(F _S2 ) is obtained after the scaling processing, clip processing, and round processing are performed in the round processing circuit 53Y.
The delay compensation circuit 54Y compensates for the delay with the color difference signal channel and outputs the result.

Here, the rate conversion circuit 50Y for a luminance signal in this embodiment is, in principle, 2 m at a frequency having a relationship of f _S2 = f _S1 · n / m where m and n are positive integers.
n, for example, EIA / CCIR
As shown in Table 1, a plurality of rate conversion ratios can be variably set, and the apparatus operates in a plurality of modes, as shown in Table 1, in order to support a system in which a plurality of f _S1 rates exist depending on the number of pixels of the CCD image sensor. .

[0085]

[Table 1]

The rate conversion circuit 50Y needs to change the characteristics and operation of the rate conversion corresponding to each mode. However, since the half-band filter 51Y has close values of f _{S1 in} each mode, the half-band filter 51Y may have a common characteristic. Conversion filter 52Y
Only change the characteristics and operation.

In the reproduction mode, the first to sixth switching circuits 56Y _{1 to} 46Y ₆ are set in the rate conversion circuit 50Y for luminance signals as shown in FIG.

[0088] That is, the reproduction mode, it said recording f _s2 rate reproduced by the reproduction unit 7 of the digital luminance signal Y (f _s2) is supplied to the delay compensation circuit 54Y, been a delay compensation of the color difference signal channels Is supplied to the half band filter 51Y via the zero insertion circuit 55Y.

[0089] The zero inserter circuit 55Y, by inserting 0 data between each sample, and upconverts the f _s2 rate digital luminance signal Y and (f _s2) to 2f _s2 rate. Further, the half-band filter 51Y
Is the reproduction mode, with respect to the 2f _s2 rate digital luminance signal Y (f _s2), by suppressing odd-order carrier components, functions as an up-rate conversion filter f _s2 → 2f _s2.

The half-band filter 51Y
2f _s2 rate digital luminance signal Y obtained by
(F _s2), in the rounding circuit 53Y, scaling or clipping, is rounding process is performed to output. In the reproduction mode, the rate conversion filter 62Y is not used.

The rate conversion circuit 5 for the color difference signal
7, a multiplexer / demultiplexer (MPX / DMPX) 51C, a half band filter 52C, a rate conversion filter 53C, a rounding circuit 54C, and a zero insertion circuit 55C, as shown in FIG. or it is constituted by a fourth switching circuit 56C ₁ ~56C _4.

In the recording mode, the rate conversion circuit 50C, as shown in FIG.
The switching circuit 56C ₁ ~56C ₄ is set.

That is, in the recording mode, the first
F generated by the digital operation unit 4_S1Rate Day
Digital color difference signal C_R(F_S1), C_B(F_S1) Is the above MP
X / DMPX51C, 2f_S1Rate of
Digital point-sequential color difference signal C _R/ C_B(2f_S1As)
The rate is input to the half-band filter 52C and
Conversion filter 53C, rounding circuit 54C, delay compensation circuit
55C in order, f_S2Rate Day
Digital point sequential color difference signal C_R/ C_B(F_S2) To rate conversion
Is done.

The half-band filter 52C has a 2f
_S1 rate digital point-sequential color difference signal C _R / C _B (2f
_S1 ) has an output data rate of 2f _S1 and a pass band of f _S2 , and has a characteristic of functioning as a Nyquist filter for the f _S2 rate.

The rate conversion filter 53C is
2 supplied via the half-band filter 52C
f _S1 rate digital point-sequential color difference signal C _R / C _B (2
f _S1 ), among the higher-order carrier components included in ₁ to n−
Suppress one. This rate conversion filter 53C has 2f
Operating at the _S1 rate, the half-band filter 52C
And an equalizing filter for compensating for the attenuation in the band.

[0096] Then, the rate converting filter 53C by obtained f _S2 rate digital dot sequential color difference signal C
_R / C _B (f _S2 ) is output after being subjected to scaling processing, clipping processing, and rounding processing in the rounding processing circuit 53Y.

Here, the rate conversion circuit 50C for the color difference signal in this embodiment is, like the rate conversion circuit 50Y for the luminance signal, in principle, f _S2 = f _S1 where m and n are positive integers. 2m → n at the frequency of n / m
A plurality of rate conversion ratios can be variably set in order to correspond to a system in which a plurality of f _S1 rates exist depending on the number of pixels of an EIA / CCIR or a CCD image sensor, and operate in a plurality of modes. It has become.

In the rate conversion circuit 50C for the color difference signal, it is necessary to change the characteristics and operation of the rate conversion corresponding to each mode.
Since f _S1 is a close value in each mode, common characteristics may be used, and only the rate conversion filter 53C changes the characteristics and operation.

[0099] The playback mode, the rate converting circuit 50C _R / C _B for the color difference signals, as shown in FIG. 9, the first to fourth switching circuits 56C ₁ ～56C ₄ is set.

That is, in the reproduction mode, the digital point-sequential color difference signals C _R / C _B (f _S2 ) of the f _S2 rate reproduced by the recording / reproduction unit 7 are supplied to the half-band filter 52C via the zero insertion circuit 55C. Supplied.

[0102] The 0-insertion circuit 55C, by inserting 0 data between each sample, and upconverts the f _s2 rate digital dot sequential color difference signal C _R / C _B a (f _S2) to 2f _s2 rate. Further, in the reproduction mode, the half-band filter 52C suppresses odd-order carrier components of the digital point-sequential color difference signals C _R / C _B (f _S2 ) at the _2fs2 rate so that _fs2 →
It functions as a _2fs2 up-rate conversion filter.

The half-band filter 52C
The _2fs2 rate digital point-sequential color difference signals C _R / C _B (f _S2 ) obtained by the above are subjected to scaling processing, clipping processing and rounding processing in the rounding processing circuit 53C, and then simultaneously processed by the MPX / DMPX 51C. reduction is f _S1 rate digital color difference signals C _R (f _S1), C
It is output as _B (f _S1 ).

In the reproduction mode, the rate conversion filter 63Y is not used.

[0104] Thus, the rate converting circuit 50C for color difference signals, f _S1 rate digital color difference signals C _R (f
_S1 ) and C _B (f _S1 ) can be handled as digital point-sequential color difference signals C _R / C _{B at a} rate of 2f _{S1 to} reduce the scale of hardware, and have the same characteristics for two color difference signals. Can be performed.

In this embodiment, at the output stage of the luminance signal channel of the second digital process circuit 42 in the first digital operation section 4, a delay compensation circuit 42DLY is provided for the luminance signal channel. I have.

[0106] The delay compensation circuit 42DLY is intended to compensate for the delay of each low-pass filter 63C _R, 63C _B to the analog encoder 62 in the signal processing unit 6 for the analog output components from the signal processing section 6 signals Y, C _R, when using only C _B is
Each post filter 61PFY of the D / A converter 61,
When the composite signal CS or Y / C is used without using the component signals Y, C _R , and C _{B, it} is used for compensating for the delay amount of the 61 PFC _R and 61 PFC _B. each low-pass filter 63C _R, so that the delay compensation for the delay amount of 63C _B, the delay amount is set.

[0107] Note that the post filter 61PFY and postfilter 61PFC _R, the difference in delay amount between 61PFC _B, are those Do small as about 1 or 2 clock cycles of the usual f _S1 rate, can be corrected anywhere processing system.

Further, in this embodiment, each low-pass filter 63C _R , 6 in the analog encoder 62 is used.
The delay amount of the 3C _B and DL _LPF, the delay compensating circuit 66
Is set to DL ₀ , the delay amount of the delay compensation circuit 42DLY provided at the output stage of the luminance signal channel of the first digital arithmetic unit 4 is set to DL _1, and the rate conversion for the luminance signal is performed. The delay amounts of the half-band filter 52Y, the rate conversion filter 53Y, and the delay compensation circuit 55Y in the circuit 51Y are DL ₂ , DL ₃ , and DL, and the half-band filter 53C and the rate conversion filter 54 in the rate conversion circuit 51C for the color difference signal.
In the recording mode, DL ₁ + DL ₂ + DL ₃ + DL = DL ₄ + DL _{5 In the} reproducing mode, the respective delay amounts of C are DL ₄ and DL _{5 so} that DL ₂ + DL ₀ = DL ₄ + DL _LPF. It has been set.

Here, the substantial processing rate of the rate conversion circuit 51C for the color difference signal is lower than that of the rate conversion circuit 51Y for the luminance signal, and DL ₂ <DL ₄ , DL ₃ <
A DL _5.

Further, the _2fs1 rate digital luminance signal Y (2) generated by the first digital
The f _s1) as an example of a specific operation of the rate converting circuit 50Y for the luminance signal to be converted to f _s2 rate digital luminance signal Y (f _s2), the rate of f _s2 = 18f _s1 / 19 i.e. 19 → 9 The conversion ratio will be described with reference to a spectrum diagram shown in FIG. 10 and a time chart shown in FIG.

That is, in the recording mode, the digital luminance signal Y (2f _s1 ) [band: 0 to 2 f _s1 rate of the spectrum as shown in FIG. f _s1 ] in the luminance signal rate conversion circuit 50Y in FIG.
The band is limited to the Nyquist frequency for the f _s2 rate by the half-band filter 51Y having the characteristics shown in FIG.
Figure 10 of the spectrum as shown in (C) 2f _s1 rate digital luminance signal Y (2f _s1) [band: 0 to F _s2
/ 2] to the rate conversion filter 52Y.

[0112] That is, for example, the Nyquist digital luminance signal composed of sample sequences of 2f _s1 rate as shown in (A) {a _n} in FIG. 11 Y (2f _s1) is for the f _s2 rate by the half band filter 51Y The band is limited to the frequency and supplied to the rate conversion filter 52Y.

[0113] In the rate converting filter 52Y, with respect to the sample sequence {b _n} of 2f _s1 rate inputted, as shown in (B) of FIG. 11, between the respective sample 9 were aliquoted,
The point where the sample <b _m > exists (indicated by ○ in FIG. 11B) is the original sample {b _n }, and the sample <b _m >
There Insert the sample zero point does not exist [indicated by & in (B) of FIG. 11] is converted into 9 × 2f _s1 = 18f _s1 rate sample sequence {b _p}. Then, the impulse response Δh of the rate conversion filter also expressed at the _18fs1 rate
_p} and by taking a convolution between the 18f _s1 rate sample sequence {b _p}, to generate an interpolated sample sequence of 18f _s1 rate. Note that FIG. 11 (B) shows the imaginary interpolated sample sequence by the rate converting filter 52Y in ×, is shown f _s2 rate of the output sample sequence of {c _n} in ◎.

The rate conversion filter 52Y
As it is defined in the FIG. 10 (D), k × 18f s1
± f _c (k: integer) is a pass band, and other g × 1
8f _s1 ± f _c: have the property of the blocking band (g integer), the half-band above 2f supplied from the filter 51Y _s1 rate digital luminance signal Y for (2f _s1) of FIG. 10 (C) 2f _s1 shown in, 4f _s1 ~16f _s1
The surrounding _2fs1 sampling carrier components are suppressed.

[0115] Thus, the 2f _s1 rate digital luminance signal Y (2f _s1), as shown in (E) of FIG. 10, the digital luminance signal Y (18f that are up-rate converted to 9-fold 18f _s1 rate _s1 ).

[0116] band characteristic of the 18f _s1 rate digital luminance signal Y (18f _s1) has a Nyquist characteristic of f _s2 rate defined by the half band filter 51Y.

[0117] Here, 18f _s1 rate filtering intended hypothetical, in fact, is the output sample sequence of f _s2 rate was downsampled signals 18f _s1 rate every 19 samples {c _n}.

[0118] Thus, convolution of the impulse response of the 18f _s1 rate {h _p} and 18f _s1 rate sample sequence {b _p} is when the sample sequence {b _p} is non-zero samples {b _m} since only may be executed, for _{example, c 0 = h -9 · b} 1 + h 0 · b 0 + h 9 · b -1 c 1 = h -8 · b 3 + h 1 · b 2 + h 10 · b 1 c _{2 = h -7 · b 5 +} h 2 · b 4 + h 11 · b 3 c 3 = h -6 · b 7 + h 3 · b 6 + h 12 · b 5 c 4 = h -5 · b 9 + h 4 · b _{8 c 5 = h -4 · b} 11 + h 5 · b 10 c 6 = h -12 · b 14 + h -3 · b 13 + h 6 · b 12 c 7 = h -11 · b 16 + h -2 · b 15 + H ₇ · b ₁₄ c ₈ = h _-10 · b ₁₈ + h _-1 · b ₁₇ + h ₈ · b ₁₆ ··· This calculation can be performed at, for example, the f _S1 rate or the f _S2 rate.

Here, in the rate conversion operation by the rate conversion circuit 50Y, what is important in characteristics is the following first to third requirements.

First requirement: The above half band filter 5
2f _s1 rate digital luminance signal Y supplied to 1Y
(2f _s1 ) [(A) in FIG. 10] and the digital luminance signal Y (18) virtually up-converted by the rate conversion filter 52Y to a nine-fold 18 _fs1 rate.
f _s1 ) The characteristics in the band of 0 to fc in (E) of FIG. 10 are the same, that is, the characteristics of the half-band filter 51Y ((B) in FIG. 10) and the rate conversion filter 52Y. 0 of the characteristic of the product with the characteristic [(D) in FIG. 10]
To fc can be approximated to 1.

[0121] The second requirement: the 18f _s1 rate up rate conversion by digital luminance signal Y (18f _s1)
2f of fc~ [the (E) 10] of (18f _s1 -fc)
That the _s1 sampling carrier component is sufficiently suppressed, that is, the product of the characteristic of the half-band filter 51Y (FIG. 10B) and the characteristic of the rate conversion filter 52Y (FIG. 10D). Characteristic fc-(18f
_s1- fc) can be approximated to 0, especially the characteristics of the rate conversion filter 52Y [(D) in FIG. 10] 2f
_{s1 to} 16f When _s1 becomes 0 and the input is DC, the output becomes (α
2f _s1 -βf _s2 ) component is not generated, and the characteristics of the half band filter 51Y (FIG. 10B) and the characteristics of the rate conversion filter 52Y [FIG.
1f _s2 ~18f _s2 of the product of the characteristics of the (D)] 0 is that it is sufficiently suppressed.

Third Requirement: Rate Conversion Filter 52
Digital luminance signal Y which has been converted up rate virtually 9 times 18f _s1 rate in Y (18f _s1) [1
0 (E)] is to set the filter characteristic of the rate conversion circuit 50Y so that the frequency characteristic near fc is within the specified range.

In the rate conversion circuit 51 of this embodiment, the first and second requirements are achieved by first passing the digital luminance signal Y (2f _s1 ) of the _2fs1 rate through the half-band filter 51Y. The third requirement can be effectively achieved by the rate conversion filter 52Y. Furthermore, since the half-band filter 51Y is a fixed coefficient FIR filter, the circuit scale can be reduced by using various filter design methods. Also,
Since the rate conversion filter 52Y is a variable coefficient filter, it requires a multiplier. However, as shown in FIG. 10D, the characteristics of the rate conversion filter 52Y are moderate in roll-off characteristics and the restrictions on the stop band are small. Configuration is very easy.

For example, the impulse response {h _p } of the rate conversion filter 52Y is {1, 3, 6, 10, 15, 21, 28, 35, 43, 49, 54, 57, 58, 57,.・｝
/ 78 and the 24th order, and the rate conversion filter 52Y can be configured with three multipliers. The coefficient word length is also 6 in this case.
It becomes a bit, and the coefficient generator and the multiplier can be simplified.

The rate conversion filter 52Y of the rate conversion circuit 51 is configured, for example, as shown in FIG.

The rate conversion filter 52 shown in FIG.
Specific examples of Y executes the operations in f _S2 is output rate, 2f _s1 rate sample sequence from {b _n} be one that generates a f _S2 rate sample sequence {c _n}, 4 Stage shift register 151, data rearranging circuit 152,
Latch circuits 153A, 153B, 153C, three coefficient generators 154A, 154B, 154C, multiplier 155
A, 155B, 155C, an adder 156, and a latch circuit 157.

In this rate conversion filter 52Y,
A sample sequence {b _n } at a rate of _2fs1 shown in FIG. 13A is serially input to the shift register 151. The shift register 151 is operated by 2f _s1 rate clock CK (2f _s1), sequentially delays the sample sequence {b _n} of the 2f _s1 rate. Then, one clock delay output [FIG. 13 (B)], two clock delay output [FIG. 13 (C)] of the sample sequence {b _n } obtained by the four-stage shift register 151, 3
The clock delay output [(D) in FIG. 13] and the 4-clock delay output [(E) in FIG.
52 are input in parallel at a rate of _2fs1 .

The data rearrangement circuit 152 outputs a one-clock delayed output of the sample sequence {b _n }, which is input in parallel at a rate of _2fs1 from the shift register 151,
The clock delay output, the 3-clock delay output, and the 4-clock delay output are rearranged at the rate f _s2 , and three types of sample sequences {b _n } _A ,
｛B _n ｝ _B , ｛b _n ｝ _C [(F), (G),
(H)]. Then, each sample sequence {b} of the f _s2 rate generated by the data rearranging circuit 152
_n ｝ _A , ｛b _n ｝ _B , ｛b _n ｝ _C
Multipliers 154A, 1 via 3A, 153B, 153C
54B and 154C.

The above-mentioned coefficient generators 155A, 155
B and 155C sequentially generate three types of multiplication coefficients A _COEF , B _COEF , and C _COEF used in the above-described calculation, respectively, at the f _s2 rate. That is, the coefficient generators 155A and 155
B, 155C, the coefficient generator 155A is the first term multiplication coefficient A _COEF {h _-9 , h _-8 ,
h _-7 , h _-6 , h _-5 , 0, h _-12 , h _-11 , h _-10 ｝ [(I) in FIG. 13] are sequentially supplied to the multiplier 154A, and the coefficient generator 155B The second term multiplication coefficient B _COEF h ₀ ,
_{h 1, h 2, h 3} , h 4, h -4, h -3, h -2, h -1}
[(J) in FIG. 13] is sequentially supplied to the multiplier 154B, and the coefficient generator 155C further multiplies the third term multiplication coefficients C _COEF ｛h ₉ , h ₁₀ , h ₂ , h ₁₁ , h ₁₂ , 0, h _5, h
₆ , h ₇ , h ₈ ｝ [(K) in FIG.
4C.

Further, each of the multipliers 154A, 154
B, 154C are the latch circuits 12A, 12B, 1
2C latch output, that is, the data rearranging circuit 1
52, each sample sequence {b _n } _A , {b _n } _B , {b _n } _{C of} the f _s2 rate, and each multiplication coefficient A _COEF supplied from each of the coefficient generators 155A, _155B , _155C . A multiplication process of multiplying B _COEF and C _COEF in parallel is sequentially performed at the f _s2 rate. These multipliers 154A,
Each of the multiplied outputs by 154B and 154C is
56.

Then, the adder 156 adds the multiplication outputs from the multipliers 154A, 154B, 154C, thereby obtaining a sample sequence {c _n } of the f _S2 rate shown in FIG. _{c 0 = h -9 · b 1} + h 0 · b 0 + h 9 · b -1 c 1 = h -8 · b 3 + h 1 · b 2 + h 10 · b 1 c 2 = h -7 · b 5 + h 2 _{· b 4 + h 11 · b} 3 c 3 = h -6 · b 7 + h 3 · b 6 + h 12 · b 5 c 4 = h -5 · b 9 + h 4 · b 8 c 5 = h -4 · b 11 _{+ h 5 · b 10 c 6} = h -12 · b 14 + h -3 · b 13 + h 6 · b 12 c 7 = h -11 · b 16 + h -2 · b 15 + h 7 · b 14 c 8 = h - Calculate ₁₀ · b ₁₈ + h ₋₁ · b ₁₇ + h ₈ · b ₁₆ .

The sample sequence {c _n } of the f _S2 rate generated from the sample sequence {b _n } of the 2f _s1 rate in this way passes through the latch circuit 157 as shown in FIG. Output sequentially.

Here, the multiplication coefficients A _COEF , B _COEF , and C _COEF used in the above-described arithmetic processing are, as shown in this specific example,
In the case of f _s2 = 18 f _s1 / 19, the coefficient generator 155 needs to appear cyclically every 9 clocks of f _s2.
A, 155B, and 155C can be easily configured by a shift register, for example, as shown in FIG.

The coefficient generator 155 shown in FIG. 14 includes cascaded first to third shift registers 161, 16
2, 163 and these shift registers 161, 16
A first switch circuit 164 for switching the clocks of 2,163 and a second switch circuit 165 for switching the output
And a control circuit 166 for controlling the operation of each of the switch circuits 164 and 165.

The first to third shift registers 16
1, 162, 163, each clock input terminal is selectively connected to the first or second clock input terminal 160A, 160B via the first switch circuit 164. Further, the data input terminal of the first shift register 161 is connected to the data output terminal of the first shift register 161, the data output terminal of the second shift register 162 via the second switch circuit 165, The data output terminal of the third shift register 163 or the coefficient data input terminal 160C is selectively connected. Then, the first shift register 161 includes:
This is a six-stage shift register whose data output terminal is connected to the coefficient data output terminal 155C. The second shift register 162 is a three-stage shift register. Further, the third shift register 163
Is a 24-stage shift register.

Here, the first clock input terminal 16
The clock CK (f _S2 ) at the f _S2 rate is supplied to 0A, and the load clock LDCKI is supplied to the second clock input terminal 160B from a system controller (not shown). The coefficient data input terminal 160C is supplied with coefficient data COEFI from a system controller (not shown). Further, the control circuit 166 is supplied with a horizontal synchronizing signal HD from the synchronizing signal generator 11 and a mode signal MODEI from a system controller (not shown).

Then, in this coefficient generator 155,
Each of the switch circuits 164 and 165 is provided with a mode signal MODEI supplied from a system controller (not shown).
Is controlled by the control circuit 166 as follows.

That is, the first switch circuit 164
Selects the load clock LDCKI supplied from the system controller to the camera startup, during normal operation, selects the f _s2 rate clocks CK (f _s2).

Further, the second switch circuit 165 includes:
When the camera is started, the coefficient data COEFI supplied from the system controller is selected, and during normal operation, the output data of the first to third shift registers 161, 162, and 163 are selected according to the operation mode. In the case of mode 1, the first shift receiver 16
1 is selected, and in the case of mode 2, the output data of the second shift register 162 is selected.
In the case of mode 3, the output data of the third shift register 163 is selected.

In the coefficient generator 155 having such a configuration,
When the camera is started, coefficient data COEFI required for rate conversion at a desired rate conversion ratio is supplied from the system controller to the data input terminal of the first shift register SR1 via the second switch circuit 165, By the load clock LDCK, synchronous writing is performed to the required number of stages in the first to third shift registers 161, 162, and 163, and coefficient data COE having a desired rate conversion ratio is obtained.
FI is stored in the first to third shift registers 161, 16
2,163.

During a normal operation, the first to third shift registers 16 according to the operation mode are set.
Coefficient data COEF set to 1,162,163
By cyclically at f _s2 rate by the I clock CK (f _s2), it is possible to output the multiplication coefficient COEF necessary for rate conversion at the desired rate conversion ratio in real time.

That is, in mode 1, the coefficient data COEFI set in the first shift
The by cyclically at f _s2 rate by the clock _{CK (f s2), f s2} = 12f s1 / 13 That is, to output the multiplication coefficient COEF necessary for rate conversion at the rate conversion ratio of 13 → 6.

In the case of mode 2, the first and second modes
By cyclically at f _s2 rate by the Shifutoreshijita 161 and 162 to the set coefficient data COEFI the clock CK (f _s2), the rate conversion at f _s2 = 18f _s1 / 19 That is, the rate conversion ratio of 19 → 9 The necessary multiplication coefficient COEF is output.

[0144] Further, by cyclically at f _s2 rate by the clock CK (f _s2) to the first to third shift registers 161, 162 and 163 to the set coefficient data COEFI in the case of mode 3, f _s2 = 33f _s1 / 35 that is, to output the multiplication coefficient COEF necessary for rate conversion at the rate conversion ratio of 70 → 33.

As shown in FIG. 15, the coefficient generator 155 may include a random access memory 171, an address control circuit 172, a control circuit 173, and the like.

In the coefficient generator 155 shown in FIG. 15, the control circuit 173 performs the following control operation according to a mode signal MODEI supplied from a system controller (not shown).

That is, when the camera is started, the address control circuit 172 is controlled so as to generate a write address in accordance with a load clock LDCK supplied from a system controller (not shown), and write control of the random access memory 171 is performed. In addition, at the time of normal operation, f _s2 rate of the clock CK (f
The address control circuit 172 is controlled so as to generate a read address according to _s2 ), and read control of the random access memory 171 is performed.

The random access memory 17
When the camera is started, coefficient data COEFI necessary for rate conversion at a desired rate conversion ratio is written into the control unit 1 via the control circuit 173 from a system controller (not shown). At the time of normal operation, in accordance with the operation mode, the set in a random access memory 171 coefficient data COEFI clock CK (f _s2)
Is repeatedly read at the rate f _s2 , and the multiplication coefficient COE required for rate conversion at a desired rate conversion ratio in real time
F is output via the latch circuit 174.

As described above, the rate conversion circuit 50C for color difference signals in this embodiment converts the digital color difference signals C _R (f _S1 ) and C _B (f _S1 ) of the f _S1 rate to 2f _S1.
Rate digital point-sequential color difference signals C _R / C _B , and f _s2 = 18 f _s1 / 19, that is, 19
The operation when the rate conversion ratio is 9 is shown in FIGS.
As shown in the time chart of FIG. 7, similarly to the above-described rate conversion circuit 50Y for a luminance signal, in principle, m and n are positive integers, and a frequency of 2 m has a relationship of f _S2 = f _S1 · n / m. → Perform rate conversion of n.

The rate conversion filter 53C of the rate conversion circuit 50C for color difference signals can have the same configuration as the rate conversion filter 52Y of the rate conversion circuit 50Y for luminance signals, as shown in FIG. , Four-stage shift register 251, data rearranging circuit 252, latch circuits 253A, 253B, 253C, three coefficient generators 254A, 254B, 254C, and multipliers 255A, 255
55B, 255C, adder 256, and latch circuit 257
It consists of.

As shown in FIG. 19, each of the coefficient generators 254A, 254B, 254C of the rate conversion filter 53C includes first to third cascaded shift registers 261, 262, 263, and First for switching clocks of shift registers 261, 262, 263
Switch circuit 264, a second switch circuit 265 for switching the output, and each of the switch circuits 264, 265
, Or a random access memory 271, an address control circuit 272, a control circuit 273, etc., as shown in FIG.

Since these operations are the same as those in the case of the above-described rate conversion filter 52Y for a luminance signal, description thereof will be omitted.

Here, as described above, for example, m = 19, n
N × 2f _s1 = mf, such as 19 → 9 rate conversion with = 9
_In the rate conversion process of _s2 , the input data string of the _2fs1 rate has a large energy at a frequency that is an integral multiple of [1 (n-1)]. Therefore, the rate conversion filter for performing the rate conversion process may be assumed to have the filter characteristic for suppressing the carrier component and higher order carrier side band components of these frequencies, with the zero point of the frequency of n × 2f _s1 a first transfer function H ₁ (z ^-1), the product H ₁ between the n × second transfer having respective zero point and below the frequency of the 2f _s1 function ^{_{H 2 (z -1) (z}} -1) × H
₂ (z ⁻¹ ) may have an impulse response of an integer coefficient given in an expanded form.

[0154] That is, it shall have at least one has a zero point, the impulse response of the integer coefficient having a zero of two at a time in the vicinity of the rate converting filter 52Y in n × 2f _s1 for the luminance signal Can be. Further, in the rate conversion filter 53C for the color difference signal, n × _fs1
Has an impulse response of an integer coefficient having at least one zero and two zeros near the zero.

Then, the first and second transfer functions H _{1 are obtained.}
(Z ^-1 ) and H ₂ (z ^-1 ) are, for example,
It is given by the formula.

[0156]

(Equation 1)

[0157]

(Equation 2)

The first transfer function H ₁ (z ⁻¹ ) is (n
-1) having the following integer coefficient, for example, H ₁ (z ^-1 ) = 1 + z ^-1 + z ^-2 + z ^-3 + z ^-4 + z ^-5 + z
^-6 + z- ⁷ + z- ⁸ . Further, the second transfer function H ₂ (z
^-1), 2 (n-1) those having the following integer coefficients, for ^{_{example, H 2 (z -1) =}} (1 + 2z -1 + 3z -2 + 4z -3 + 5z -4 + 6z -5 + 7z -6 + 8z ^-7 + 9z ^-8 + z ^-16 + 2z ^-15 + 3z ^-14 + 4z ^-13 + 5z ^-12 + 6z ^-11 + 7z ^-10 + 8z ^-9 )-(z ^-7 + 2z ^-8 + z ^-9 ) = (1 + 2z ^-1 + 3z ^-2) + 4z ^-3 + 5z ^-4 + 6z ^-5 + 7z ^-6 + 7z ^-7 + 7z ^-8 +7 ^-9 + 7z ^-10 + 6z ^-11 + 5z ^-12 + 4z ^-13 + 3z ^-14 + 2z ^-15 + z ^-16 The rate conversion filter is
It becomes a 3n-th order integer coefficient and has characteristics as shown in FIG.
The above z ^-1 is a unit delay operator corresponding to n × 2f _s1.

In the data string input to the rate conversion filter, only n-th actual sample exists with respect to the impulse response of the rate conversion filter. Therefore, three multipliers are required for actual convolution. good. In this way, by only operating the rate converting filter for suppressing higher-order carrier components of 2f _s1, it is possible to reduce the number of required multipliers in an actual circuit. In the vicinity of the base band, the roll-off of the amplitude characteristic becomes dull, but can be corrected in advance by a half-band filter.

In the digital camcorder having such a configuration, the image pickup signals R, G, 1B output from the solid-state image sensors 1R, 1G, 1B of the image pickup section 1 driven at the f _S1 rate.
B is converted to f
Image data R, G, B digitized at the _S1 rate and digitized by the analog-to-digital converter 3
Since at least the digital luminance signal Y and the two digital color difference signals C _R and C _B are generated by the first digital operation unit 4 operating at the clock rate related to the f _S1 rate, the image quality can be reduced without causing beat interference. And a good digital image signal can be obtained.

FIG. 22 shows the operation state of the main part in the recording mode. As shown in FIG. 22, in the recording mode, the digital luminance signal generated by the first digital operation unit 4 and related to the f _S1 rate is output. Y and the digital color difference signals C _R and C _B are converted into the above f
_The digital luminance signal Y related to the _S2 rate and two digital color difference signals C _R and C _B are converted and supplied to the recording / reproducing unit 7, and the digital luminance signal Y related to the f _S1 rate and the digital color difference signal C _R, is C _B is output via the signal processing unit 6 for the analog output. Also, as shown in FIG. 23, the operation state of the main part in the reproduction mode is as follows. In the reproduction mode, the digital luminance signal Y and digital chrominance signal C related to the f _S2 rate reproduced by the recording / reproduction section 7. _R, C _B digital luminance associated with the f _S1 rate by the second digital processing unit 5 signals Y and two digital color difference signals C _R, C _B
And output via the signal processing unit 6 for analog output.

That is, in this digital camcorder, the second digital arithmetic unit 5 has a function of bidirectionally converting the data rate between the data rate related to the f _S1 rate and the data rate related to the f _S2 rate. a digital luminance signal Y and two digital color difference signals C _R, the second digital with a C _B is output via the signal processing unit 6 that the recording mode is generated by the first digital processing unit 4 via the operation unit 5 is supplied to the recording reproduction unit 7, a signal in data rate associated with the f _S2 rate to be reproduced by the reproducing unit 7 in the reproduction mode Y, C _R, and C _B above second Digital operation unit 7
And the reproduced signal is output through the signal processing unit 6, so that the recording / reproducing unit 7 outputs a signal Y, Y of a data rate related to the f _S2 rate.
C _R, it is possible to perform recording and reproduction of C _B.

In this digital camcorder, the second digital arithmetic unit 5 is capable of setting a plurality of rate conversion ratios, and the input data rate signals Y, C _R , C C associated with the f _S1 rate. _{Since B} is converted into signals Y, C _R , and C _B of the output data rate related to the f _S2 rate, the CCD image sensors 1R, 1
Using a standard CCD image sensor as G and 1B, a digital image signal of a clock rate of D-1 standard or another clock rate can be obtained.

Further, in this digital camcorder, the first digital arithmetic unit 4 performs two operations in the recording mode.
A digital luminance signal Y (2f _S1 ) of the f _S1 rate is generated, and the digital luminance signal Y (2f _S1 ) is subjected to rate conversion processing of 2f _S1 → f _S2 by the second digital arithmetic unit 5 to reproduce the signal. In the mode, the digital luminance signal Y (f _S2 ) of the f _S2 rate supplied from the recording / reproducing unit is provided.
However, since the rate conversion processing of f _S2 → 2f _S1 or f _S2 → 2f _S2 is performed by the second digital operation unit, the configuration of the second digital operation unit can be simplified.

Also, the second digital operation unit 5
The recording mode operates at a clock rate of _{2f S1, f S1, f S1} , the first of the signals Y generated by the digital processing unit _{4 (2f S1), C R} (f S1), C
_B (f _S1 ) functions as a Nyquist filter for clock rates of f _S2 , f _S2 / 2, f _S2 / 2,
Reproduction mode the 2f _S2, f _S2, half-band filter 51Y which operates at a clock rate of f _S2 exhibits the same frequency characteristic as the recording mode, sharing the 52C in the reproduction mode and the recording mode, the recording mode, Each signal Y (2) supplied through the half-band filters 51Y and 52C by the rate conversion filters 52Y and 53C.
f _S1 ), C _R (f _S1 ), and C _B (f _S1 ), the digital luminance signal Y (2f _S1 ) is subjected to a rate conversion process of 2f _S1 → f _S2 to obtain a digital color difference signal C _R (f _S1). ),
The rate conversion process of f _S1 → f _S2 / 2 is substantially performed on C _B (f _S1 ). As described above, by sharing the half-band filters 51Y and 52C in the reproduction mode and the recording mode, the configuration of the second digital operation unit 5 can be simplified.

Further, the second digital operation unit 5
Is the signal Y of the first input data rate generated by the digital processing unit 5, C _R, with respect to C _B, 2
At output data rates of f _S1 , f _S1 , f _S1 , f _S2 , f _S2 /
2, a half-band filter 5 having a pass band of f _S2 / 2
Band limiting processing is performed by 1Y, 52C, and 2f _S1 → f _S2 , f _S1 → f by rate conversion filters 52Y, 53C.
_S2 / 2 or _{f S2 / 4, f S1 →} f S2 / 2 or performs rate conversion processing _{f S2 / 4, n × 2f} S1, n × f S1, n × f S1
(N is a positive integer) A low-order linear phase finite-length impulse response sufficient to suppress the surrounding high-order sideband components is represented by f _S2 ,
The signal is output in a form downsampled at _fS2 / 2 or _fS2 / 4, _fS2 / 2 or _fS2 / 4. Further, the passing roll-off characteristics of the rate conversion filters 52Y and 53C are compensated by the characteristics of the half band filters 51Y and 52C. Thus, the rate conversion processing can be reliably performed by the second digital operation unit 5 having a simple configuration.

In this digital camcorder, the rate conversion filters 52Y and 53C for performing the rate conversion processing on the signals band-limited by the half-band filters 51Y and 52C are nx2f _S1 , nx
f _S1 , n × f _S1 has an impulse response of an integer coefficient having at least one zero and two zeros in the vicinity thereof, and each has three multipliers 154A to 154
C, 254A to 254C.

[0168] Further, the signal Y of the first input data rate generated by the digital processing unit 4, C _R, half-band filter 51Y performs band limitation to C _B, 5
2C can be a simple one composed of the product of partial filters composed of integer coefficients.

Furthermore, in this digital camcorder,
Each of the imaging signals R, G, and B output from the solid-state image sensors 1R, 1G, and 1B disposed in the color separation optical system of the imaging unit 1 that adopts the spatial pixel shifting method is subjected to predetermined conversion by the A / D conversion unit 3. digitized by f _S1 rates phase, at least 2f _S1 rate of the digital luminance signal Y (2f _S1) and two digital color difference signals C _R of f _S1 rates respectively by the first digital processing unit 4 (f _S1), C _B (F
_S1 ), and a rate conversion process of 2m → n (m and n are positive integers) is performed by the second digital arithmetic unit 5 capable of setting a plurality of rate conversion ratios n / m, and f _S2 = f _S1 / n /
An m-rate digital luminance signal Y (f _S2 ) and a substantially f _S2 / 2 rate digital color difference signal C _R (f _S2 /
2) Since C _B (f _S2 / 2) is generated, a digital image signal with good image quality can be obtained without the occurrence of beat interference by using the spatial pixel shifting method, and aliasing distortion is small and high. An MTF digital image signal can be obtained.

Furthermore, in this digital camcorder,
Each of the signals Y (2f _S1 ), C _R (f _S1 ), and C _B (f _S1 ) generated by the first digital operation unit 4 is converted into an analog signal by the D / A conversion unit 61 of the signal processing unit 6. Luminance signal Y _OUT and analog color difference signals Y _OUT , C _ROUT , C
_{Since BOUT} is output, it is possible to simultaneously obtain a high-resolution analog image signal and a high-MTF digital image signal with little aliasing distortion. In the recording mode, the signal processing unit 6 generates the digital luminance signal Y (2f _S1 ) of the 2f _S1 rate generated by the first digital operation unit 4.
The and analog data output by the D / A converter 61, the playback mode, said second 2f _S2 rates generated by the digital processing unit 5 of the digital luminance signal Y (2
Since f _S2 ) is converted into an analog signal by the D / A converter 61 and output, a high-resolution analog luminance signal can be obtained in the recording mode and the reproduction mode.

Also, the second digital operation unit 5
The digital interface 13, the digital luminance signal Y is 2f _S2 of the clock rate digital color difference signals C _R, since the C _B is the interface at the clock rate of f _S2 / 2 respectively, 2f _S2 rate of the digital luminance signal Y (2f _S2 ) And f _S2 / 2 rate digital color difference signals C _R (f _S2 / 2) and C _B (f _S2 / 2) can be transmitted and received between external devices.

Furthermore, in this digital camcorder,
The first of the signals Y generated by the digital processing unit 4, C _R, D / A converter 61 of the C _B the signal processing section 6
A low-pass filter 6 that performs a band limiting process on an analog color difference signal in an analog encoder 62 to which an analog luminance signal and an analog color difference signal are supplied after being converted into an analog signal.
First delay compensating circuit 4 for compensating for group delay due to 3, 64
Since 2DLY is provided at the output stage of the luminance signal channel of the second digital process processing circuit 42 of the first digital operation unit 4, the imaging signals R, 1G, 1B of the imaging unit 1 by the CCD image sensors 1R, 1G, 1B are provided. G, it is possible to obtain a luminance signal Y and color difference signals C _R generated from B, and good analog image signal compensated image quality differential delay between the C _B.

In this digital camcorder, each signal Y, C _R , C _{B of} the output data rate related to the f _S2 rate generated by the second digital arithmetic unit 5
Is provided in the rate conversion circuit 50Y for the luminance signal of the second digital arithmetic unit 5, so that the CCD of the imaging unit 1
The imaging signals R by the image sensors 1R, 1G, 1B,
The luminance signal Y generated from G and B and the color difference signals C _R and C _B
And a digital image signal having good image quality can be obtained.

Further, in this digital camcorder, the second digital operation section 5 performs bidirectional rate conversion between a data rate related to the f _S1 rate and a data rate related to the f _S2 rate. A second delay compensation circuit 54Y in the external input mode.
The digital luminance signal and the digital chrominance signal of the data rate related to the f _S2 rate inputted through
_R, the f _S1 rate related data rate signals Y having a group delay equal to the group delay of the C _B, C _R, and generates a C _B, supplied to the D / A converter 61 of the signal processing section 6 Therefore, even in the external input mode, a delay difference between the luminance signal Y and the color difference signals C _R and C _B can be compensated to obtain an analog image signal with good image quality.

[0175]

According to the digital camcorder according to the present invention, an image pickup signal output from at least one solid-state image sensor driven at the _fS1 rate is digitized by the analog-to-digital converter at the _fs1 rate having a predetermined phase. At least a digital luminance signal Y is obtained from the image data digitized by the analog-to-digital converter.
And the two digital color difference signals C _R and C _B are generated by the first digital operation unit operating at the clock rate related to the above f _S1 rate, so that a digital image signal with good image quality without beat interference is generated. Obtainable. The second digital operation unit has a function of performing bidirectional rate conversion between a data rate related to the f _S1 rate and a data rate related to the f _S2 rate,
The f _S1 generated by the first digital processing unit
Rate signal of the associated data rate Y, C _R, the signal data rate and C _B relating to the f _S2 rates Y,
C _R, supplied to the recording and reproducing unit are converted into C _B, also signals in data rate associated with the f _S2 rates supplied from the recording reproduction unit Y, C _R, and C _B to the f _S1 Rate signal Y of the associated data rate, C _R, since converted to C _B is supplied to the signal processing unit, the recording unit to be interfaced with a clock rate related to f _S2 rate, associated with the f _S2 rate Data rate signal Y,
C _R, it is possible to perform recording and reproduction of C _B.

[0176] In the digital camcorder according to the present invention, when the recording mode, the digital luminance signal generated by the first digital processing unit Y and two digital color difference signals C _R, a C _B via the signal processing unit And output to the recording / reproducing unit via the second digital arithmetic unit. In the reproducing mode, the signals Y, C _R , and Y at the data rate related to the f _S2 rate reproduced by the recording / reproducing unit are output. the C _B is supplied to the signal processor via the second digital processing unit, so it outputs a reproduction signal through the signal processing unit, by the recording and reproducing unit,
The signal Y of the data rate related to the above f _S2 rate,
C _R, it is possible to perform recording and reproduction of C _B.

Also, in the digital camcorder according to the present invention, in the recording mode, the first digital arithmetic section generates a digital luminance signal Y (2f _S1 ) of the 2f _S1 rate, and the second digital arithmetic section generates the digital luminance signal Y (2f _S1 ). The digital luminance signal Y (2f _S1 ) is subjected to rate conversion processing of 2f _S1 → f _S2 , and in the reproduction mode, the digital luminance signal Y of the f _S2 rate supplied from the recording / reproduction unit
Since the rate conversion processing of f _S2 → 2f _S1 or f _S2 → 2f _S2 with respect to (f _S2 ) is performed by the second digital operation unit, the configuration of the second digital operation unit can be simplified. .

In the digital camcorder according to the present invention, in the recording mode, the signal processing section converts the 2f _S1 rate digital luminance signal Y (2f _S1 ) generated by the first digital operation section into a digital-to-analog signal. Unit, and outputs the analog signal. In the reproduction mode, 2f generated by the second digital arithmetic unit is output.
_Since the digital luminance signal Y (2f _S2 ) at the _S2 rate is converted into an analog signal by the digital-to-analog converter and output, a high-resolution analog luminance signal can be obtained in the recording mode and the reproduction mode.

In the digital camcorder according to the present invention, the second digital operation section operates at a clock rate of 2f _S1 , f _S1 , f _{S1 in} the recording mode, and is generated by the first digital operation section. Each of the signals Y (2f _S1 ), C _R (f _S1 ), and C _B (f _S1 ) functions as a Nyquist filter with respect to a clock rate of f _S2 , f _S2 / 2, f _S2 / 2. A filter operating at a clock rate of 2f _S2 , f _S2 , and f _S2 and exhibiting the same frequency characteristics as in the recording mode is shared between the reproduction mode and the recording mode. In the recording mode, the filter is used by the rate conversion filter. For each of the signals Y (2f _S1 ), C _R (f _S1 ), and C _B (f _S1 ) supplied via the digital luminance signal Y (2f _S1 ), 2f _S1
→ Perform the rate conversion process of f _S2 and
_R (f _S1 ) and C _B (f _S1 ) are substantially f _S1 → f _S2
Since the rate conversion process of / 2 is performed, the configuration of the second digital operation unit can be simplified by sharing the filter between the reproduction mode and the recording mode.

Further, in the digital camcorder according to the present invention, the second digital operation section uses a digital interface to output a digital luminance signal Y of two.
The digital color difference signals C _R and C _B at a clock rate of f _S2
Are each interfaced at a clock rate of f _S2 / 2, so that the digital luminance signal Y at the rate of 2 f _S2
(2f _S2 ) and f _S2 / 2 rate digital color difference signal C _R
(F _S2 / 2), it can be exchanged between the C _B (f _S2 / 2) external devices.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital camcorder according to the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a signal processing unit for analog output in the digital camcorder.

FIG. 3 is a block diagram illustrating another configuration example of a signal processing unit for analog output in the digital camcorder.

FIG. 4 is a block diagram showing a configuration example of a rate conversion circuit for a luminance signal in the digital camcorder.

FIG. 5 is a block diagram showing a connection state in a recording mode of the rate conversion circuit for a luminance signal.

FIG. 6 is a block diagram showing a connection state in a reproduction mode of the rate conversion circuit for a luminance signal.

FIG. 7 is a block diagram illustrating a configuration example of a rate conversion circuit for a color difference signal in the digital camcorder.

FIG. 8 is a block diagram showing a connection state in a recording mode of the rate conversion circuit for color difference signals.

FIG. 9 is a block diagram illustrating a connection state in a reproduction mode of the rate conversion circuit for a color difference signal.

FIG. 10 is a spectrum diagram showing an operation of the luminance signal rate conversion circuit.

FIG. 11 is a time chart showing an operation of the rate conversion circuit for a luminance signal.

FIG. 12 is a block circuit illustrating a configuration example of a rate conversion filter in the rate conversion circuit for a luminance signal.

FIG. 13 is a time chart showing an operation of the rate conversion filter for a luminance signal.

FIG. 14 is a block circuit showing a configuration example of a coefficient generator in the rate conversion filter for a luminance signal.

FIG. 15 is a block circuit showing another configuration example of the coefficient generator in the rate conversion filter for the luminance signal.

FIG. 16 is a time chart showing the operation of the rate conversion circuit for color difference signals.

FIG. 17 is a time chart illustrating an operation of the rate conversion filter for a color difference signal.

FIG. 18 is a block circuit illustrating a configuration example of a rate conversion filter in the rate conversion circuit for a color difference signal.

FIG. 19 is a block circuit showing a configuration example of a coefficient generator in the rate conversion filter for color difference signals.

FIG. 20 is a block circuit showing another configuration example of the coefficient generator in the rate conversion filter for color difference signals.

FIG. 21 is a characteristic diagram showing a specific example of characteristics of the rate conversion filter for a luminance signal.

FIG. 22 is a block diagram showing an operation state of a main part in a recording mode of the digital camcorder.

FIG. 23 is a block diagram showing operation states of main parts in a reproduction mode of the digital camcorder.

[Explanation of symbols]

1 ... Imaging unit 1R, 1G, 1B ... CCD image sensor 2 ... Analog signal processing unit 3 ... A / D converter 3R, 3G, 3B A / D converter 4 First digital operation unit 5 Second digital Arithmetic unit 6 Signal processing unit 7 Recording / reproducing unit 41 First digital process processing circuit 42 ... Second digital process processing circuit 42DLY... First delay compensation circuit 50Y, 50C... Rate conversion circuit 51Y, 52C. Band filter 51C MPX / DMPX 52Y, 54C Rate conversion filter 54Y ······· Second delay compensation circuit 61 ······ D / A converter 62 ······· Analog encoders 63C _R , 63C _B.・ Low pass filter 73 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Digital encoder

Claims (14)

(57) [Claims] 1. A and at least one solid-state image sensor driven at f _S1 rate, and analog-to-digital converter for digitizing an image signal at f _S1 rates predetermined phase output from the solid-state image sensor, the operating at a clock rate related to the f _S1 rate,
From the image data digitized by the analog-to-digital converter, at least digital luminance signals Y and 2
One of the digital color difference signals C _R, first and digital processing unit, the first of said f _S1 generated by the digital processing unit for generating a C _B
A signal processing unit for the digital luminance signal data related to the rate Y and two digital color difference signals C _R, is C _B is supplied, and a recording and reproducing unit to be interfaced with a clock rate related to f _S2 rate, the f _S1 A function for performing bidirectional rate conversion between a data rate related to a rate and a data rate related to the _fS2 rate, wherein the first digital arithmetic unit, the signal processing unit, and the recording / reproducing unit Connected to the first
Signal Y in data rate associated with the f _S1 rates generated by the digital processing unit, C _R, C _B and the f _S2
The signals are converted into signals Y, C _R , and C _B of the data rate related to the rate and supplied to the recording / reproducing unit. The signals Y, C _R of the data rate related to the f _S2 rate supplied from the recording / reproducing unit are converted. , digital, characterized in that by converting the C _B signal Y in data rate associated with the f _S1 rate, C _R, the C _B comprising a second digital processing unit supplying to the signal processing unit Camcorder. 2. In a recording mode, the first digital
Digital luminance signal Y generated by the
Digital color difference signal C_R, C_BThrough the signal processing unit
And outputs the second digital operation unit.
Is supplied to the recording / reproducing unit via the
The f reproduced by the recording / reproducing unit _S2Related to rates
Signals Y and C at the selected data rate_R, C_BIs the second data
The signal is supplied to the signal processing unit via a digital operation unit.
The playback signal is output via the signal processing unit
The digital camcorder according to claim 1, wherein 3. The digital camcorder according to claim 1, wherein said signal processing unit includes a digital-to-analog conversion unit. 4. In a recording mode, the first digital operation section performs a 2f _S1 rate digital luminance signal Y (2
generates f _S1), a digital camcorder according to claim 1, wherein said second digital processing unit, characterized in that perform rate conversion processing 2f _S1 → f _S2 with respect to the digital luminance signal Y (2f _S1) . 5. In the reproduction mode, the second digital operation section performs a rate conversion process of f _S2 → 2f _{S1 on} the digital luminance signal Y (f _S2 ) of the f _S2 rate supplied from the recording / reproduction section. 5. The digital camcorder according to claim 4, wherein the digital camcorder is operated. 6. In the reproduction mode, the second digital operation section performs a rate conversion process of f _S2 → 2f _{S2 on} the digital luminance signal Y (f _S2 ) of the f _S2 rate supplied from the recording / reproduction section. 5. The digital camcorder according to claim 4, wherein the digital camcorder is operated. 7. The signal processing section includes a digital-to-analog conversion section. In a recording mode, the digital luminance signal Y (2f _S1 ) of the 2f _S1 rate generated by the first digital operation section is converted into an analog signal and output. 7. The digital camcorder according to claim 6, wherein in the reproduction mode, the digital luminance signal Y (2f _S2 ) of the 2f _S2 rate generated by the second digital operation section is converted into an analog signal and output. 8. In a recording mode, the first digital operation unit performs a 2f _S1 rate digital luminance signal Y (2
f _S1 ) and the digital color difference signals C _{R at the} respective f _S1 rates
(F _S1), to generate a C _B (f _S1), the second digital processing unit performs the rate conversion processing 2f _S1 → f _S2 with respect to the digital luminance signal Y (2f _S1), digital color difference 2. The digital camcorder according to claim 1, wherein a rate conversion process of f _S1 → f _S2 / 2 is substantially performed on the signals C _R (f _S1 ) and C _B (f _S1 ). 9. In the reproduction mode, the second digital operation section performs a digital luminance signal Y (f _S2 ) of f _S2 rate.
Is subjected to a rate conversion process of f _S2 → 2f _S1 , and f _S2 /
Two-rate digital color difference signals C _R (f _S2 / 2), C _B
9. The digital camcorder according to claim 8, wherein (f _S2 / 2) is substantially subjected to a rate conversion process of f _S2 / 2 → f _S1 . 10. In the reproduction mode, the second digital operation section performs a digital luminance signal Y of _fS2 rate.
(F _S2) performs rate conversion processing f _S2 → 2f _S2 respect, f _S2 / 2 rate digital color difference signals C _R (f _S2 /
2), f _S2 / 2 → f substantially with respect to C _B (f _S2 / 2)
9. The digital camcorder according to claim 8, wherein a rate conversion process of _S2 is performed. 11. The signal processing unit includes a digital-analog converter, the recording mode, the first 2f _S1 rates generated by the digital processing unit digital luminance signal Y (2f _S1) and f _S1 rate The digital color difference signals C _R (f _S1 ) and C _B (f _S1 ) are converted into analog signals and output. In the reproduction mode, the 2f _S2 rate digital luminance signal Y generated by the second digital operation unit is used.
(2f _S2) and f _S2 rate digital color difference signals C _R (f
_11. The digital camcorder according to claim 10, wherein _S2 ) and C _B (f _S2 ) are converted into analog signals and output. 12. In the recording mode, the second digital operation unit generates the signals Y (2f _S1 ), C _R (f _S1 ) and C _R generated by the first digital operation unit.
_B (f _S1 ) operates at a clock rate of 2 f _S1 , f _S1 , f _S1 , functions as a Nyquist filter for clock rates of f _S2 , f _S2 / 2, f _S2 / 2, and 2 f _S2 , a filter operating at a clock rate of f _S2 , f _S2 and exhibiting the same frequency characteristics as in the recording mode, and each signal Y (2f _S1 ) and C _R (f _S1 ) supplied through the filter during the recording mode for C _B (f _S1), 2f the digital luminance signal Y (2f _{S1) S1}
→ Perform the rate conversion process of f _S2 and
_R (f _S1 ) and C _B (f _S1 ) are substantially f _S1 → f _S2
11. The digital camcorder according to claim 10, comprising a rate conversion filter for performing a rate conversion process of / 2, wherein said filter is shared between a reproduction mode and a recording mode. 13. The digital camcorder according to claim 5, wherein the signal processing unit includes a third digital operation unit that operates at a clock rate related to the f _S1 rate. 14. The second digital processing unit and the recording digital luminance signal Y is digital color difference signals C _R at the clock rate of 2f _S2 to the node to external between reproduction unit, C _B, respectively f _S2 / 2 The digital camcorder according to claim 1, further comprising a digital interface having a clock rate of: