JP3506920B2 - Method for preventing contention of storage of all instruction trace data in secondary storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer,
Processor, electronic exchange, workstation, etc.
Central processing unit (hereinafter abbreviated as CPU)
All instruction trace data stored in the secondary storage device
And secondary depending on the operating system being traced
All instruction trace data to prevent contention for storage
The present invention relates to a method for preventing contention of data in a secondary storage device. [0002] 2. Description of the Related Art Generally, evaluation is performed for the purpose of performance evaluation or the like.
The program of the target operating system (the operating
All applications running on the rating system
For tracing all instructions, including
Of the instruction group (excluding programs, omitted below), the CPU
Information about all the instructions to be executed (the
Contents, instruction length, register change status, changed register
The contents of the program and other management units for the program as needed
Information such as thread information) immediately before execution of one instruction
Is called an all-instruction trace.
Traces the information collected by the trace into all instruction trace data.
Say ta. The above program is a function (from the program
Called program with one entrance)
Program (call triggered by interrupt, etc.)
This is a program that is normally
Not executed), and all instruction traces
And all of them are traced (only functions
A trace that only traces all instructions is called an all-instruction trace.
I don't know). A CP having a single-step interrupt function
In the full instruction trace under U, the function
Set the trace flag of the CPU to ON in advance and interrupt
For processing only, the trace flag of the CPU
Is turned on, etc., the CPU is instructed immediately before the execution of one instruction.
Cause a single-step interrupt
Has been done. CPU is the operating system to be evaluated
Every time immediately before executing one instruction of the system, the CPU wakes up.
Using a single-step interrupt
Is a single-step interrupt handler for all instruction traces
Control to the program and the program traces all instructions
Collects data and temporarily stores it in all instruction trace data buffers.
To the interrupt source.
Turn, and after returning, the CPU executes the interrupted instruction.
Executes one instruction, and after the execution, executes the next instruction
Just before, a single-step interrupt
The operating system to be evaluated.
All of the instructions executed in the system
A full instruction trace of the instruction is performed. At that time all instruction tray
Source data buffer has a limited fixed size
However, the total amount of all instruction trace data is
Tens of memory depending on the operating logic of the
Since it usually reaches several gigabytes to several gigabytes,
All the instruction trace interrupts described above can be performed on the data in the buffer as appropriate.
By storing the processing program in the secondary storage device,
Avoid buffer overflow. The secondary storage device generally requires high speed.
The tape drive or hard disk drive.
Place. Meanwhile, the operating system being evaluated
Also generally a single step interrupt for all instruction traces
Secondary of the same type as the secondary storage used by the processing program
An operating system that uses one or more storage devices
Is executing an instruction to input / output to / from the secondary storage device
Sometimes, single-step interrupt processing for all instruction traces
Management program must perform all these instruction traces.
(Traces that do not do this are all instruction traces.
Do not call it a source). In that case, the operating system
The input / output processing performed by the system is as follows:
Processing of single-step interrupt processing program
The processing is different from the processing. (A) The operating system has input and output
CPU is operating system while
Request input / output for effective use in other processes
Operation of the operating system programs
Any other operating that wants to stop and use the CPU
Instructions for the system program, if any
(Otherwise I / O is
During this time, the CPU is not used effectively). That
Issue I / O instructions and complete the I / O
The processing that performs the processing is a separate processing, and the latter is generally
Realized by interrupt processing that runs when an interrupt occurs
It is. (B) On the other hand, a single step
In the input / output processing of the
While output is being performed, the CPU completes its input / output.
Until another program in the operating system
System instructions must not be executed. Because the operation
All the instructions of the program executed by the operating system
Must be traced, single for all instruction trace
The step interrupt processing program is performing input / output.
Operating system instructions are executed during
And the execution of that instruction causes a single-step interrupt
Occurs, a single step for all instruction traces
The interrupt processing program has not completed its own processing.
Nevertheless, once again to execute operating system instructions
Therefore, it will be called, and the subsequent processing will be performed normally.
And the execution of the instruction
If a single-step interrupt does not occur,
Is not collected as all instruction trace data.
You. Therefore, a single step interrupt for all instruction traces
I / O processing of the data processing program enters and exits the secondary storage device
If you issue a force command,
Perform a loop inside and wait for its completion. That
Until I / O is completed, single instruction trace for all instructions
Step interrupt processing program returns to interrupt source
No, and normal (except for emergency processing that is urgent)
Is also prohibited. This is because the singles for all instruction traces
Step interrupt processing program inputs / outputs to / from secondary storage device
While the operating system is in secondary storage
That no new I / O commands are issued to the device.
Means that the operating system is secondary storage
Singles for all instruction traces while
Step interrupt processing program enters / exits to secondary storage
It is possible to do force. Accordingly, a single step for tracing all instructions is
Interrupt processing program completes I / O to secondary storage
While waiting in a loop for
Input and output for the system may be completed. On the spot
Single-step interrupt processing for all instruction traces
The program will issue itself if it does not handle its completion
Cannot receive completion of input / output (hardware
Unless a previously completed one is processed,
Hold the data in the input / output device and report it to the CPU.
Absent). Processing its completion means that all instruction
Source single-step interrupt processing program
The secondary storage device of the rating system must be processed.
Means you have to. It goes against (B) above
You. Therefore, in the prior art, they are avoided.
To do so, one of the following methods was used. (1) Although all instruction tracing is performed completely,
IR of secondary storage used by operating system
Q number (channel number for computers larger than the embodiment)
Below) and single step division for all instruction traces
Number of the secondary storage device used by the embedded processing program
All instruction traces by using a separate object
Single-step interrupt processing program for secondary storage
Operate to the same IRQ number while inputting / outputting to / from the device.
Completion of input / output of the secondary storage device of the rating system
Make it impossible to happen. (2) I / O interrupt processing and the like
Do not race. This allows a single instruction trace for all instructions
The step interrupt processing program is
Ensure that I / O processing for the stem does not interfere
(This is equivalent to not doing a full instruction trace). [0011] SUMMARY OF THE INVENTION
In (2), all executed instructions to be evaluated
Cannot be traced for accurate performance evaluation.
I can't. Further, in the above (1), the following problem is encountered.
was there. For example, as in an IBM compatible personal computer,
When it is necessary to keep the cost of the stem itself low
Means that there are only two secondary storage devices and they are the same IR
Being connected under the Q number is a rare
And not in that case the operating system and the whole life
Instruction trace single-step interrupt processing program
Must use the same IRQ number. That
In some cases, the conventional technology depends on the operating system.
Traces all instructions, including access to secondary storage
Can't do it. The present invention has been made in view of the above,
The goal is that the operating system
Secondary storage to be used and single instruction for all instruction traces
Secondary storage used by the interrupt processing program
Traces all instructions even if they exist under the same IRQ number
2 of all instruction trace data that can be executed without shield
To provide a storage contention prevention method for secondary storage
You. [0015] Means for Solving the Problems To achieve the above object,
Therefore, the present invention described in claim 1 provides a central processing unit in an information processing apparatus.
The arithmetic unit traces all instructions and traces all instructions.
Data is everythingFirstWhen stored in secondary storage
The operating system being traced
Same as aboveSecondIf using secondary storage,
Even if these secondary storage devices are under the same IRQ number,
Without troubleTheir secondaryStorage in the storage device is performed
Operating system to achieveSecond
During input / output to / from the secondary storage device,All instruction tray
The single-step interrupt processing program
The central processing unitOf all instruction trace dataFirst2
Suppressing output to the secondary storage device;Output is suppressed
ToDuring the period, All instruction trace single step division
The central processing unit is assigned by the
Interrupt pending display indicating that an interrupt has occurred in the interrupt disabled state.
Loop until you standOperating system
Not to execute instructions other than the input / output instructions; and
BCompletion of operating system input / output completion processing
Is detected, and when this is detected, all instruction trace dataFirst
The gist is to start output to the secondary storage device. In the first aspect of the present invention, the operation
Rating systemSecondI / O to secondary storage
While you go,All instruction trace single step division
The central processing unit isAll instructions
Trace dataFirstSuppress output to secondary storage
ThatOutput is suppressedDuring the period, Trace all instructions
Central performance with single-step interrupt processing program
The arithmetic unit indicates that an interrupt has occurred while interrupts are disabled.
Loop until the interrupt pending bit is setOperate
Command other than the input / output instructions of the
Not toBOperating system input and output
Completion processing completion is detected.
DataFirstStarting output to secondary storage
Even if the secondary storage device is under the same IRQ number,
Without troubleSecondaryCan be stored in a storage device.
Wear. [0017] DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing an embodiment of the present invention.
First, the concept and outline of the present invention will be described. [0018] At the root of the above problems in the prior art
This is because the operating system is performing I / O.
IRQ number that is the same as the IRQ number of the secondary storage device
Is a single-step interrupt processing program for tracing all instructions.
The point where the program starts I / O to the secondary storage device
is there. Therefore, single step split for all instruction traces
Description under the IRQ number used by the embedded processing program
Operating system is performing I / O to storage
Single step interrupt processing for all instruction traces
The program suppresses the issue of I / O instructions to the secondary storage device.
Stops, the I / O being executed is completed, and the interrupt processing ends.
At that point, issue the suppressed I / O instruction.
No. In this case, the completion interrupt of the I / O being executed is interrupted.
All the instruction trace data of the processing
Cannot be output to the secondary storage device until the
Must be able to be stored on the buffer. Therefore, the battery
The size of the web must be large enough.
In the embodiment of the present invention, the size of the buffer
Is 5MB, all instruction trace data per instruction
Is 50 bytes on average, so 100Kstep interrupt
Can store trace data for all instructions in the
There is no title. During the suppression of the I / O, the
Input / output of the corresponding secondary storage device of the operating system
When another program other than the processing runs, the buffer is
Single step for all instruction traces.
The interrupt processing program loops and operates
Waiting for the input and output of the
Return to the operating system and
Until the operating system completes the interrupt processing.
Operating system without starting output to storage device
When the completion of the interrupt processing of the secondary storage device is detected,
Start output to all. Incidentally, in a high-performance information processing system, etc.
The CPU is the bottleneck for the performance limit of the system
Never been designed so that the operating system
I / O to the secondary storage device used will be a bottleneck
Is not designed. In that case, all instruction trace routines
IRQ number to which the secondary storage device to be used is connected
Under the operating system
Secondary storage device and IRQ usage by its input / output "
Is designed to have a low usage rate, usually less than 30%
You. In systems with such high performance designs,
Is executed in one input / output processing to the secondary storage device.
The number of instructions is at most a few kilosteps,
The large multiplex input / output number is a number input / output at most. Therefore,
The operating system performs input and output, as in
During execution, single-step interrupt processing for all instruction traces
Management program inhibits I / O to secondary storage device
In the meantime, the secondary storage of the operating system
Unless running processes other than those related to the device,
Buffer size must be 5 MB or more as in the embodiment
No problem as long as the buffer overflows
Will not be disabled). In the present invention, as described above,
Instruction trace single-step interrupt processing program
IRQ number that is the same as the IRQ number of the secondary storage device used by
Entering the operating system into the secondary storage device
Allow output, but enter the operating system
During output, a single step for all instruction traces is performed.
Input / output to the secondary storage device
Instruction issuance, and the operating system
Other than those associated with that input / output of the system.
Do not perform the input / output completion processing
Secondary storage of all instruction traces immediately after system execution
By starting input / output to the
Single step interrupt processing program is secondary storage device
When executing I / O to the IRQ number,
Reports the completion of an I / O other than the "I / O being executed"
And trace all instructions
Is implemented without buffer overflow.
And enable. Next, an embodiment of the present invention will be described with reference to the drawings.
explain about. FIG. 1 is a perspective view of an embodiment of the present invention.
Prevention of contention for storing instruction trace data in secondary storage
It is a block diagram showing composition of a device which performs a method. Same figure
The embodiment shown in the figure has a single-step interrupt function.
CPU 1 (for example, INTEL Pentium), interrupt system
Your chip 2 (eg INTEL 8259), operating
Secondary storage device 3 for the system (for example, IDE primer
Lee HD, device number 0, IRQ number 14), all instructions
Secondary storage device 4 for trace data (for example, IDE
Candiary HD, device number 1, IRQ number 14),
And a memory 5. Memory 5 is an operating
Processing program 5 for secondary storage device for storage system
0, input / output of secondary storage device for operating system
Function 51, Other Information for Operating System
52, single-step interrupt processing for all instruction traces
Output of secondary storage for program 53, trace of all instructions
Function 54, buffer 5 of secondary storage for all instruction traces
5 and other information 56 for full instruction tracing
are doing. First, a single-step interrupt function is provided.
The CPU 1 executes the interrupt control chip 2 and the signal line.
And whether or not there is an interrupt from the chip,
Chip status information, etc.
Outputs information such as notification of completion of interrupt reception to the chip
it can. The CPU 1 has 2 for the operating system.
Secondary storage 3, secondary storage for all instruction trace data
4 and a memory 5 connected by a bus.
Read and write information to and from these devices and memories
Noh. Next, the flowcharts shown in FIGS.
The operation of the embodiment shown in FIG. 1 will be described with reference to FIG.
You. FIG. 2 shows a secondary storage device for an operating system.
Is a flowchart showing the procedure of the input / output function 51 of FIG.
FIG. 3 shows the allocation of the secondary storage device for the operating system.
Flowchart showing the procedure of the embedding processing program 50
Figure 4 shows a single step split for all instruction traces.
Showing a partial procedure of the embedded processing program 53
Figure 5 shows a single step for tracing all instructions.
A part of the procedure of the interrupt processing program 53 following FIG.
FIG. 6 is a flowchart showing the procedure for tracing all instructions.
Flowchart showing the procedure of the output function 54 of the secondary storage device
It is. Now, the other for the operating system
The program in the information 52 of the
I / O for writing data to the secondary storage device 3 for the system
O event (set of data to request processing)
Operating system as parameters.
Calls the input / output function 51 of the secondary storage device for the
At the time of the secondary storage device 3 for the operating system
For example, there is no running I / O event for
explain. At that time, the system
Status [CPU trace flag is ON, all instruction traces
External variable for all instructions is in execution (ON)
Numbers are visible from everywhere, so where they exist
In this embodiment, all of the external variables
Other information 56 for the command trace)]]
All instruction trays in other information 56 for instruction trace
All internal counters for the Secondary storage for operating system
When called, the input / output function 51
CPU 1 having a step-up interrupt function performs the steps shown in FIG.
Attempt to execute the instruction of S100 (* 1). At this time,
Since the trace flag is ON, the CPU 1
A step interrupt has occurred and is about to be executed at that time.
The address of the instruction that was
Stack area in other information 52 (hereinafter referred to as stack
Area (abbreviated as area)
After the lag is set to OFF (the above processing is a general
"CPU1 with single-step interrupt function"
CPU function for single-step interrupts
4), single-step interrupt for all instruction traces in FIG.
Control is passed to the processing program. In FIG. 4, at step S300, the cash register
The stacker is evacuated to the stack area, and the
Check during execution of all instruction traces, YES
In step S303, all the instruction trace buffers are full.
Check if there is a bug, here, unless there is a bug in the system
No, all instruction traces are executed in step S305.
Data is collected and stored in the secondary storage for all instruction traces.
The buffer 5 is stored in the buffer 5 in step S306.
5 instruction data is stored in 512 bytes
Check that the size is equal to or larger than
Click. The trace data of all instructions is, on average, one instruction.
Since the information is about 50 bytes, step S306
Is less than one-tenth, so
In many cases, the step will be NO. In case of NO
Correspond to steps S400, S402, S404 and FIG.
And the checks in S406 are performed. In this case, it
Instructions interrupted by single-step interrupt processing
Is the above (* 1), and in the flowchart,
Since it is the instruction of step S100, step S40
0, S402, S404 and S406
Of these, only step S400 is YES, and step S400
At 401, other information 56 for tracing all instructions
External variable “Secondary storage device write-protection count”
Is added to "1", resulting in 1. Then,
In step S408, the registers and the like are restored, and step S408 is executed.
By issuing an IRET instruction at 409,
Return to the interrupt source of (* 1).
Trace flag is restored to the state just before the interrupt.
You. In this case, return to ON). This "secondary storage device write inhibit count"
Is a secondary storage device for the operating system.
Interrupt processing program 50, operating system
Other interrupt handling in other information 52 for the system
Programs, input / output functions and operating systems
The input / output function 51 of the secondary storage device for the
Or input / output to / from other devices (omitted in FIG. 1)
Is set to a value other than 0.
Issuance of a series of I / O instructions to the system device (on the way,
For output processing to secondary storage device for all instruction trace data
So no overruns occur
Exists, and if not 0, all instruction trace data
Is suppressed from being output to the secondary storage device. Returning to the interrupt source of (* 1), the CP
U executes only one instruction in step S100 of FIG.
You. Here, in step S100, the designated IR
Q number designated device number (in this embodiment, the operating
There is only one secondary storage device for the
Queue = fixed (RQ = 14, device number = 0)
(In other information 52 for the operating system)
Check if there is an / O event. Not here
Therefore, the process proceeds to the next step S103, where the CPU
Attempting to execute the instruction of S103 (* 2)
Since the trace flag is ON,
A step interrupt is generated and all instruction trace
The steps after step S300 of the single-step interrupt processing are executed.
Is performed. In this case, the secondary storage device write inhibit count
Is set to 1, so the step
S300, S301, S303, S305 were executed
Then, in step S306, the buffer has 512 bytes or more.
If all the instruction trace data of
Since 07 is NO, step S308 is executed.
(The output function of the secondary storage device for all instruction traces calls
Will not be). Steps S400 and S40
2, (S404 and S406) also check (*
Since the addresses of 2) are all NO, all instruction trays
The single-step interrupt processing program for
In step S305, all instruction trace data are collected and
Output to the secondary storage device just by storing it in the
In step S408, the registers and the like are recovered, and
Interrupt source (* 2) by IRET instruction in step S409
Return to When returning to the interrupt source, the process proceeds to step S103.
For certain operations, multiple instructions are executed,
Single-step interrupt occurs for instruction
(* 3) is the same as (* 2) above, in step S305.
Collect all instruction trace data and store in buffer
And output to the secondary storage device.
In step S408, the registers and the like are recovered, and in step S4
At 09, the process returns to the interrupt source (* 3) by the IRET instruction. Next, the CPU 1 issues a command in step S104.
Attempt to execute the order (* 4)
Step interrupt occurs, and step S3
05, all the instruction trace data are collected and step S30
6 is YES, NO in step S307, and
No in step S400 and no in step S402
However, in step S404,
YES because it corresponds to the instruction of step S104,
In step S405, the external variable “secondary storage device state
The state is set to 1 (* 10), and step S406 is N
In step S408, steps S408 and S409 are executed.
Then, it returns to the interrupt source (* 4). At the interrupt source (* 4), step S10
4 are executed and the operating system is executed.
I / O instruction to secondary storage device is issued for stem
However, in those single-step interrupts,
As in the case of (* 2), in step S305,
Just collect trace data and store it in buffer
Without calling the output function of the secondary storage device.
At step S408, the registers and the like are recovered, and the process proceeds to step S408.
At 409, the process returns to the interrupt source (* 4) by the IRET instruction. Next, the return of step S105 of FIG.
Single step interrupt when an instruction is about to be executed
In step S305, all the instruction trace data
Just collect data and store it in the buffer, and secondary storage
Step S40 without calling the output function of the device.
2, but in step S402, the interrupted instruction
Address matches step S105 in the flowchart.
Therefore, in step S403, writing to the secondary storage device is performed.
The prohibition counter is decremented by one and returns to zero. Therefore, step
After step S409, the interrupt source R in step S105
After the ETURN instruction is executed, the operation shown in FIG.
Of input / output function of secondary storage device for operating system
Operating system programs that are
Immediately before the “instruction to be executed when executed” (*
In the single step interrupt generated in 5),
Steps S300, S301, S303, S305, S3
When steps S06 and S307 are sequentially executed, step S307 is executed.
Of the "secondary storage device write inhibit counter" is zero
If the check is YES, the entire life is determined in step S308.
The output function (Fig. 6) of the secondary storage device for
Will be The output relation of the secondary storage device for tracing all instructions
The number (FIG. 6) is stored in the secondary storage device in step S500.
It is checked whether the position is 0 or not.
0) is set to 1 so that the answer is NO and the step
Go to S509, check in step S509, YE
It becomes S. Therefore, the process goes to step S510,
The interrupt pending chip for the interrupt control chip 2
Issue an instruction to read the IRQ14
By checking if the reservation bit is set
Access to the secondary storage for the operating system
Check if the force is completed. Note that this function
Runs as an extension of single-step interrupt processing
Single-step interrupt processing is disabled
When the operation of the secondary storage device is completed,
If no interrupt occurs, the above interrupt is suspended instead.
A bit stands. The interrupt occurs only for a single
Step interrupt processing returns, and the return source
When a program instruction that is not
You. These are general basic processing related to interrupt processing.
It is a logical concept (common sense). The interrupt pending bit must be set
Entering and exiting secondary storage for operating system
Since the force has not been completed, execute step S510 again.
Until the interrupt pending bit is set (operating
Until the input / output of the secondary storage device for the storage system is completed)
Loop. Secondary storage for operating system
When the input / output of the device is completed, the interrupt pending bit is set.
Therefore, the determination in step S510 becomes YES, and the processing in step S5
Then, in step S511, the operating
In order for the system to complete the I / O,
Set the storage device state to 2 and go to step S507
Return by executing RETURN instruction.
Go to Step S400 of Step 4. Step S400, S4
02, S404 and S406 are all NO
Then, after steps S408 and S409, the above (* 5)
Return to the interrupt source. Here, the operating system
The secondary storage for the operating system of FIG.
Immediately after returning from the input / output function
Normally it is necessary to drive with interrupts disabled, so for a while
Driving in interrupt disabled state during (several tens steps)
Then, release the interrupt prohibition. Therefore, when the vehicle is driven in the interrupt disabled state,
While the single-step interrupt
Returns all instruction trace data in step S305.
After collecting and storing in the buffer, in step S308,
The output function of the secondary storage device for tracing all instructions (Fig. 6)
The function is called, but the state of the secondary storage device is 2.
State, so that steps S500, S509, S512
Is executed, and YES is determined in the step S512.
Return without doing anything (* 11). Therefore,
In single-step interrupt processing of
In step S305, all the instruction trace data are collected and
Perform processing only to store in the buffer. In the above, depending on the operating system,
The interrupt system is disabled, the operating system
I / O of the secondary storage device for the system is in the interrupt pending state.
Interrupt, a completion interrupt occurs, and the CPU
CPU trace (by general CPU1 function)
The flag is set to OFF, and the operating system shown in FIG.
Of the interrupt processing program for the secondary storage device of the system
The control is passed to step S200. In step S200, a register or the like is used.
And all instruction traces are executed in step S201.
Check if it is running. Here, it is YES
Therefore, step S202 is executed, and step S203
Subsequent instructions may cause a single-step interrupt
Then, the trace flag of the CPU is turned ON. Note that this
The instructions of steps S200 to S202 are all instructions
Present on operating systems without tracing
do not do. Therefore, the instructions are
Although it is in the interrupt processing of
Source program, and the target of all instruction traces
No effect on performance evaluation even if traced
Do not give. Next, the instruction of step S203 is executed.
Shortly before (* 12), a single-step interrupt
Occurs and a single step split for all instruction traces in Figure 4
Control passes to the embedded processing program. In the program,
Steps S301 and S303, similarly to the above (* 11).
Is executed, and in step S305, all the instruction trace data
Are collected and stored in a buffer, and steps S306, S3
07 and S308, and called in step S308.
The output function of the secondary storage device for all instruction traces is (2
Return without doing anything (because the secondary storage device status is 2)
However, the processing of steps S400 to S406
Thus, only step S400 is a step in the flowchart.
Since the instruction in step S203 is detected,
In step S401, the secondary storage device write inhibit counter
1 is added, the value of the counter becomes 1, and step S4
08, return to interrupt source (* 12) via S409
I do. Upon return, the operating system
The interrupt processing program of the secondary storage device for the system
Steps S203, S204, S205, S206, S20
7, the instructions of S209 are executed, and steps S204 to S209 are executed.
Immediately before executing each instruction in step S209.
Step interrupt occurs, at which time the secondary storage
The device write inhibit counter is 1, and the
The dress is checked in steps S400 to S406.
Because it does not match with the
Single-step interrupt processing program
S300, S301, S303, S305, S306,
S307, S400, S402, S404, S406,
The operation is performed in the order of S408 and S409, and substantially, step S3
05 collects all instruction trace data and stores in buffer
(* 13). Next, the execution of the instruction in step S210 is performed.
In the single step interrupt just before
Single-step interrupt processing for all instruction traces in Figure 5
The program includes steps S300, S301, S30
3, S305, S306, S307, S400, S40
The processing up to S404 is the same as (* 13) above.
However, in step S406, the address of the instruction
-Instruction in step S210 of the chart (operating
Of I / O completion processing to / from the secondary storage device of the storage system
Detection), and since the secondary storage device state = 2,
If the answer is YES, the process proceeds to step S407 and the secondary storage
Is set to 3 and the secondary storage for all instruction traces is set.
Call the output function (FIG. 6). Output relation of the secondary storage device for all instruction traces
The number is 2 when the control is passed and the secondary storage state is 3.
Therefore, steps S500, S509, S512, S51
Step 3 is executed, and the step S513 switches to the secondary storage device state.
After setting 0, go to step S501,
501 is the content written in all instruction trace buffers
Of the 512 bytes part (for all instruction tracing)
Issue an I / O command to output to the next storage device (device number = 1)
And the input / output is completed in step S502 (the
Issue an input command for inputting the status of the device, and
Is not busy and IRQ number = 14
Interrupt pending bit is not set)
Wait in a loop, and then go to steps S503 and S5
05 and S506 are performed. Step S506
If there is still data in the buffer,
S501, S502, S503, S505, S506
Execute repeatedly. Step S504 and step S504
Step S508 is an abnormal process, which is normally executed.
There is no. [0044] As described above, according to the present invention,
Secondary storage used by the operating system and all
Single-step interrupt processing program for instruction trace
The secondary storage device used by the system is under the same IRQ number.
If the input / output to the former is in progress,
The start of force is deterred and during the deterrence
Other than operating system related programs
The rating system program is not executed, and
The above input of the running operating system is completed.
At the time of its completion, the secondary
Input to the storage device starts, so the buffer overflows.
The input and output of both above are executed without inconsistency
Execution and execution of all instruction traces
Should include any interrupt handling performed on the
Can be performed for all instructions.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of an apparatus for implementing a method of preventing contention storage of all instruction trace data in a secondary storage device according to an embodiment of the present invention. FIG. 2 is a flowchart showing a procedure of an input / output function of a secondary storage device for an operating system in the embodiment shown in FIG. 1; FIG. 3 is a flowchart showing a procedure of an interrupt processing program of a secondary storage device for an operating system in the embodiment shown in FIG. 1; FIG. 4 is a flowchart showing a part of a procedure of a single-step interrupt processing program for tracing all instructions in the embodiment shown in FIG. 1; FIG. 5 is a flowchart showing a part of the single-step interrupt processing program for tracing all instructions in the embodiment shown in FIG. 1, which is subsequent to FIG. 4; FIG. 6 is a flowchart showing a procedure of an output function of a secondary storage device for tracing all instructions in the embodiment shown in FIG. 1; [Description of Signs] 1 CPU having a single step interrupt function 2 Interrupt control chip 3 Secondary storage device for operating system 4 Secondary storage device for all instruction trace data 5 Memory 50 Interrupt processing of secondary storage device for operating system Program 51 Input / output function of secondary storage device for operating system 52 Other information for operating system 53 Single step interrupt processing program for tracing all instructions 54 Output function of secondary storage device for tracing all instructions 55 Secondary for tracing all instructions Storage buffer 56 Other information for full instruction trace

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Claims (1)

(57) [Claim 1] When a central processing unit in an information processing apparatus traces all instructions and all the instruction trace data are stored in a first secondary storage device, the traced operating systems of the same type
When using the second secondary storage device, also their secondary storage device is in a subordinate same IRQ number, without any trouble, they
While the operating system is performing input / output to / from the second secondary storage device, all instruction trace
The central processing unit is
DOO is, arresting the output to the first secondary storage of all instruction trace data, the period during which suppresses output, before
All instruction trace single step interrupt processing program
The CPU causes the central processing unit to disable interrupts.
Until the interrupt pending bit indicating that an interrupt has occurred
Loop that does not run any other instructions for the input and output of the operating system, and detects the completion of the completion process input and output in O Pereti <br/> ring system, first of all the instruction trace data on the detected time All instructions stored conflict prevention method of the secondary storage device of the trace data, characterized in that to start the output of the secondary storage device.