GB2261537A - Computer - Google Patents

Abstract

A computer includes a central processing unit (200), a peripheral input/output device (215 and 216) and a system controller (204). The system controller (204) comprises first means arranged to identify an input/output instruction which is received from the central processing unit (200) and second means for executing the instruction and providing a ready signal to relieve the central processing unit (200) while the instruction is executed by the second means of the system controller (204). The system controller may also be used to control refresh operations in relation to a dynamic RAM module, and may also duplicate 110 write instructions in such a memory so that future 110 read operations may be replaced by a faster access to the information in the DRAM. <IMAGE>

Description

COMPUTER The present invention relates to a computer having improved performance on input/output (I/O) operations and memory management.

According to a first aspect of the invention, there is provided a computer which includes a central processing unit, a peripheral input/output device and a system controller connected between the central processing unit and the input/output device by means of system buses, the system controller comprising first means arranged to identify an input/output instruction, which is received from the central processing unit via a command bus and an address bus of the system bus, as being of a predetermined type, and second means for executing the instruction so identified and providing a ready signal to relieve the central processing unit while the instruction is executed by said second means of the system controller.

Preferably, said first means of the system controller is provided by a system bus controller controlling the output system bus of the system controller and comprises a comparator for comparing the command data and address data of a said input/output instruction, the system bus controller receiving the output of the comparator and the command data of a said input/output instruction.

According to a second aspect of the invention, there is provided a computer which includes a central processing unit, dynamic memory and a system controller incorporating a memory refresh controller for the dynamic memory and connected between the central processing unit and the dynamic memory, the memory refresh controller including a refresh address counter providing a memory address for future memory refresh by the memory refresh controller, wherein the system controller further includes a comparator for comparing the current memory address accessed by the central processing unit and the current memory address provided by the refresh address counter, the refresh address counter being arranged to skip its current memory address if determined by the comparator to be corresponding to the current memory address accessed by the central processing unit.

Preferably, the dynamic memory is arranged in sequential groups of every 32 bytes of memory elements in such a manner that all the memory elements of a particular group will be refreshed simultaneously in a single refresh operation by the memory refresh controller.

According to a third aspect of the invention, there is provided a computer which includes a central processing unit, dynamic memory and a system controller .incorpprating a memory refresh controller for the dynamic memory and connected between the central processing unit and the dynamic memory, wherein the system controller includes means for identifying instructions issued by the central processing unit and to be executed not involving the dynamic memory, and the memory refresh controller is arranged to perform simultaneous memory refresh in response to detection by said means of such an instruction.

Preferably, the system controller includes counter means for inhibiting the memory refresh controller against refreshing the dynamic memory above a predetermined frequency.

According to a fourth aspect of the invention, there is provided a computer which includes a central processing unit, dynamic memory, a system controller connected between the central processing unit and the dynamic memory, and a peripheral input/output device, the system controller including means arranged to detect a write instruction for the input/output device and in response to write the same write data into the dynamic memory for future reference by the central processing unit upon issuing the input/output device an equivalent read instruction which is to be replaced by the reference to the dynamic memory for the same data.

Preferably, the system controller is arranged to take over a said input/output write instruction from the central processing unit and to provide a ready signal to relieve the central processing unit while the input/output instruction is executed by the system controller.

The invention will now be more particularly described, by way of example only, with reference to the accompanying drawings, in which: Figure 1 is a block diagram showing the general system configuration of a conventional computer; Figure 2 is a flow chart showing a typical I/O operation of the conventional computer of Figure 1; Figure 3 is a timing diagram showing the I/O operation illustrated in Figure 2; Figure 4 is a block diagram showing the general system configuration of an embodiment of a computer in accordance with the invention; Figure 5 is a block diagram showing the detailed general configuration of a system controller incorporated in the computer of Figure 4; Figure 6 is a flow chart showing a typical I/O operation of the computer of Figure 4, involving the use of the system controller of Figure 5; and Figure 7 is a timing diagram showing the I/O operation illustrated in Figure 6.

Referring firstly to Figure 1 of the drawings, there is shown the general system configuration of a conventional computer. The computer system includes a CPU (central processing unit) 100, a system bus controller 104 connected to the CPU 100 by COMMAND bus 101 and READY line 113, an address latch 105 connected to the CPU 100 by address bus 102, and a data latch 106 connected to the CPU 100 by data bus 103. On the output sides of the bus controller 104, the address latch 105 and the data latch 106, there are provided system bus 110 including READY line 114, address bus 111 and data bus 112, respectively. The computer system further includes internal memory and peripheral devices which are both connected to the CPU 100 via the control, address and data buses 110, 111 and 112 as shown in Figure 1.

The internal memory is provided by DRAM (dynamic random access memory) 107 which forms the main memory for storing temporary data such as computer programs, and by EPROM (erasable programmable read-only memory) 108 which is used to store permanent data such as system control programs, etc. The peripheral devices are connected to the various buses 110, 111 and 112 via an I/O processor 109, and include external data storage devices 115 such as floppy disc drives and hard disks and I/O devices 116 such as monitor, keyboard and printer.

The operation of the I/O processor 109, particularly of integrated circuit type, requires intervention of the CPU 100 for initialisation and job allocation and has to be continuously monitored by the CPU 100. In general, the CPU 100 does not contain any data/instructions, and therefore has to retrieve data/instructions from the storage devices 115 or other parts of the computer system through the I/O processor 109 and subsequently place the retrieved data/instructions in the DRAM 107 before data processing and/or instruction execution can proceed.

Figures 2 and 3 show the interaction between the CPU 100 and the I/O processor 109 during an I/O operation. The CPU 100 fetches an I/O instruction, from say the DRAM 107, which is then passed from the COMMAND bus 101 onto the system bus 110 by the system bus controller 104. In response, the I/O processor 109 begins to execute the I/O instruction until the execution is completed. As soon as the job is finished, the I/O processor 109 will inform the CPU 100 by a READY signal firstly appearing at the READY line 114 and subsequently transferred to the READY line 113 by the system bus controller 104.

The I/O system, particularly the storage devices 115 and the I/O devices 116, operates at a speed significantly lower than that of the CPU 100. As a result, the CPU 100 has to remain idle over a significant period during I/O operations. This adversely affects the speed performance of the overall computer system.

It is common general knowledge that dynamic memory, such as the DRAM 107, requires periodic refreshing, otherwise the content therein will be lost. Memory refresh is accomplished by reading and/or writing a certain address of the DRAM 107. Each address represents one row of memory elements. In a typical DRAM chip, there are 1024 rows of 1024 memory elements. Accordingly, each refresh operation will refresh 1024 memory elements simultaneously in one row, and it will takes 1024 refresh operations to refresh the entire chip.

Memory refresh is undertaken by a memory refresh controller 117 which is triggered by a free running timer 118 periodically. During a memory refresh operation, the refresh controller 117 will put the CPU 100 into an idle condition by means of a HOLD signal and take control of the relevant buses over from the CPU 100. Refresh operations are generally slow and thus take up precious CPU time.

Each time when the CPU 100 accesses the DRAM 107 for reading program instructions and/or reading or writing data, the corresponding portion of the DRAM 107 is automatically refreshed by the CPU access action. The memory refresh controller 117 operates periodically and sequentially through the address of the memory, and thus will not take into account of the incidental memory refresh incidentally accomplished by CPU access.

Referring now to Figure 4, in which there is shown the general system configuration of an embodiment of a computer according to the invention, with parts common to those of the conventional computer system of Figure 1 designated by the corresponding numerals increased by 100. In the improved computer system, there is provided a system controller (SYSC) 204 replacing the system bus controller 104, address latch 105, data latch 106 and memory refresh controller 117 of the conventional system. The system controller 204 is connected between the CPU 200 and all the remaining parts of the computer system for greater controllability.

Figure 5 shows the detailed configuration of the system controller 204 which includes a system bus controller 236.

The COMMAND bus 201 via an instruction decoder 230 is connected to the system bus controller 236 directly as well as via a comparator 231 which has two inputs. To the other input of the comparator 231, the incoming address bus 202 is connected via a local storage 232. The incoming address bus 202 is also connected to an address latch 233 whose output constitutes the outgoing address bus 211 of the system controller 204. The incoming data bus 203 is connected to two data latches 234 and 235. The output of the data latch 234 constitutes the outgoing data bus 212 of the system controller 204. An output 222 of the system bus controller 236, another output 220 of the address latch 233 and the output 221 of the data latch 235 are all connected to the DRAM 207 for writing into the DRAM 207 data retrieved through an I/O operation from the storage devices 215 or I/O devices 216.

The remaining parts of the system controller 204 is responsible for memory refresh, and is formed by a bus transceiver 252, a comparator 238, a refresh controller 237, a refresh address counter 239 and a discrepancy counter 251. The comparator 238 has three inputs, with the first input connected via bus 240 to the output of the instruction decoder 230, the second input connected via the bus transceiver 253 to the output 220 of the address latch 233, and the third input connected to an output of the refresh address counter 239. The output of the instruction decoder 230 is also connected to an input of the refresh controller 237 via the bus 240. The refresh address counter 239 has another output 254 connected to the output 220 of the address latch 233.

The refresh controller 237 is connected with the system bus controller 236 by bus 245, and has another input connected to the output of the comparator 238. The output of the refresh controller 237 is connected to the input of the refresh address counter 239. The discrepancy counter 251 is connected to the refresh controller 237 by a pair of opposite direction buses 246 and 250.

The operation of the system controller 204 is best illustrated in Figure 5. Insofar as the CPU 200 is concerned, it operates in the same manner as the CPU 100 of the conventional computer system, namely being in a ready or reset state (Box A), fetching a new instruction (Box Bj and executing the same (Box C) until a READY signal is asserted (Box D) and returning to the reset state (Box A).

Once the CPU 200 starts to execute a new instruction, the instruction will be decoded by the instruction decoder 230 of the system controller 204. The decoder result will then be fed, with the address given by the CPU 200 via the local storage 232, to the comparator 231 in order for the comparator 231 to determine the type of instruction that is going to be executed.

The system bus controller 236 receives the decoded instruction from the instruction decoder 230 as well as the result of the comparator 230, and is programmed to respond according to the type of instruction received. In general, CPU instructions include memory read, memory write, I/O read, I/O write, interrupt service and intra-processor operations such as hold, halt, lock or processor extension services. The system bus controller 236 classifies (Box E) these instructions into the following four types: Type I that can be taken over by the system controller 204 (Box F), Type II - SIMD (single instruction multiple data) operation being possible (Box G), Type III - memory refresh with refresh conditions met (Box H), and Type IV - those for which the CPU 200 has to wait for completion of execution (Box I).

Type I instructions include I/O write operations for which the CPU 200 does not require any data from the storage devices 215 or I/O devices 216 upon completion of instruction execution, such as I/O write to display card memory. When such a type of instruction is detected, the system bus controller 236 will execute the instruction (Box J) in place of the CPU 200 and wait for an READY signal to be asserted by the storage devices 215 or I/O devices 216, and will immediately assert a READY signal at line 213 (Box J) in order to relieve the CPU 200 from waiting for the job to be finished so that it can proceed, for example, to fetch and execute the next instruction.

The taking-over operation of the system controller 204 is illustrated by the timing diagram shown in Figure 7. It can be seen that a READY signal is asserted for the CPU 200 at line 213 immediately after the I/O processor 209 has commenced the I/O write operation under the control of the system controller 204 which then waits for the READY signal at line 214 upon completion of the task.

Reference is now made to the Type II instructions. When the system controller 204 takes over an I/O write operation from the CPU 200, the system bus controller 236 will also write the same data into an appropriate address of the DRAM 207 through buses 220, 221 and 222 (Box K).

It is well known that a CPU executes one task at a time, generally known as single instruction single data (SISD) system, in that only one item of data is processed per instruction. The duplication of data in the DRAM 207 while the system controller 204 executes an I/O write operation, as described above, will effectively turn the computer system into a SIMD system.

The CPU 200 is occasionally required to read back the data that it has previously written into the storage devices 215 or I/O devices 216. When such an I/O read operation is to be executed later by the CPU 200, the system bus controller 236 will determine through the comparator 231 and the address latch 233 whether the equivalent data is already available in the DRAM 207. If so, the data will be retrieved from the DRAM 207 through the buses 220, 221, 222 and 203 instead of from the identified storage device 215 or I/O device 216. In effect, this arrangement will transform a CPU I/O read operation into a DRAM read operation which takes considerable less time to complete.

Concerning Type III instructions, certain CPU tasks may be accomplished without the involvement of the DRAM 207, and these tasks include interrupt acknowledges, I/O reads, I/O writes, and memory reads from pre-defined regions not of the DRAM 207, such as the EPROM 208 or system buffers. As soon as the system controller 204 identifies such CPU instructions, it will initiate a memory refresh upon the DRAM 207 (Box L).

Taking the interrupt acknowledge operation as an example, the CPU 200 may be interrupted from normal execution by certain devices, such as the I/O devices 216, for service.

After the CPU 200 is interrupted, it will issue an interrupt acknowledge signal to the interrupting device and then undergo a pre-defined sequence of operations, such as preserving its current status and access certain I/O locations for information. During this sequence of operations, which is well known in the art, there is a portion of time during which the DRAM 207 is left idle and available for refresh (Box H) to be undertaken by the system controller 204 (Box L). In this regard, parallel operation is achieved as a result of a single CPU instruction execution.

Where the current CPU instruction is determined to be falling within Type IV, i.e. those for which the CPU 200 has to wait for completion of execution, such as I/O reads, the system controller 204 will simply pass the instruction onto the appropriate storage device 215 or I/O device 216 and wait for a READY signal (Box I) to be asserted externally on the READY line 214 upon completion of execution of the instruction.

It is understood that the system controller 204 at Box I will also be waiting for a READY signal internally generated upon completion of the operation represented by the relevant Box J, K or L.

Insofar as the operation of the peripheral devices, namely the storage devices 215 and I/O devices 216, is concerned, it comprises waiting for (Box M), executing (Box N) and finishing execution of (Box O) an I/O operation, that being the same as in the conventional computer system.

The CPU 200 normally accesses instructions from the DRAM 207 through the memory address in an ascending sequential manner. Each CPU access to the DRAM 207 involves reading from and/or writing into the same part of the DRAM 207, and therefore will simultaneously refresh that part of the DRAM 207. However, the CPU access sequence does not normally coincide with the memory refresh sequence.

Reference is now made to the parts 237 to 239 and 251 and 252 of the system controller 204 shown in Figure 5. The refresh controller 237 performs normal periodical memory refresh of the DRAM 207. The refresh address counter 239 keeps track of the next memory address to be refreshed.

The bus transceiver 252 feeds the current CPU access address to the comparator 238 for comparison with the next memory address to be refreshed. If there is a coincidence between the two addresses, the comparator 238 will inform the refresh controller 237 which will in turn instruct the refresh address counter 239 to skip the prevailing memory refresh address for the next one as that part of the DRAM 207 corresponding to the prevailing memory refresh address will be automatically refreshed through execution of the impending CPU access.

According to statistical analysis, an ordinary computer program has a very high likelihood of accessing instruction from the DRAM 207 within 64 address locations from that of the previous CPU access. The refresh address counter 239 is arranged, in this particular embodiment, to place the refresh address in a sequence of every 32 bytes (memory address locations), as illustrated by the following map:

CPU DRAM ACCESS ROW COLUMN ADDRESS ADDRESS 0000 00 00 : : : 0031 00 31 0032 01 00 : : : 0063 01 0063 31 0064 02 0064 00 : : : C0 Ri 00 : : : C31 Ri 31 C32 Ri+1 00 C64 Ri+2 00 : : : When the CPU 200 accesses memory address in the range of C0-C3l, the corresponding row Ri of the DRAM address locations will be refreshed automatically, whereas the row Ri+l of the DRAM address locations will likewise be refreshed with CPU access to memory address from C32 to C63.The partitioning of the DRAM 207 in this manner will maximise the probability of the memory refresh address matching or coinciding with the CPU access address, in that both addresses will effectively be synchronised once there has been a prior instance of coincidence between them.

Thus the number of normal periodical memory refresh operations to be performed by the refresh controller 237 on its own account, taking up precious CPU time, is kept to a minimum.

It is known that each row of DRAM elements must be refreshed within a certain period of time. However, refreshing of each DRAM element row should not be carried out unnecessarily too frequently in order to reduce supply power swings as each refresh operation will draw a relatively large current from the power source. The discrepancy counter 251 is provided to safeguard against too frequent memory refresh operations performed under the control of the system controller 204 in an untimed manner, such as when handling Type III instructions as described above.

The discrepancy counter 251 incorporates a free running counter based upon the system clock, whereas the refresh controller 237 has an internal counter counting according to the refresh operations performed. When the counter value of the discrepancy counter 251 exceeds that of the refresh controller 237 by 16, the refresh operation of the refresh controller 237 will be inhibited by the discrepancy counter 251 until the counter value of the discrepancy counter 251 advances to reduce the difference between the two counter values to below 16, whereupon the refresh controller 237 is permitted again to perform fresh operations.

The invention has been given by way of example only, and various modifications of and/or alterations to the described embodiment may be made by persons skilled in the art without departing from the scope of the invention as specified in the appended claims.

Claims (8)

1. A computer including a central processing unit, a peripheral input/output device and a system controller connected between the central processing unit and the input/output device by means of system buses, the system controller comprising first means arranged to identify an input/output instruction, which is received from the central processing unit via a command bus and an address bus of the system bus, as being of a predetermined type, and second means for executing the instruction so identified and providing a ready signal to relieve the central processing unit while the instruction is executed by said second means of the system controller.

2. A computer as claimed in claim 1, wherein said first means of the system controller is provided by a system bus controller controlling the output system bus of the system controller and comprises a comparator for comparing the command data and address data of a said input/output instruction, the system bus controller receiving the output of the comparator and the command data of a said input/output instruction.

3. A computer including a central processing unit, dynamic memory and a system controller incorporating a memory refresh controller for the dynamic memory and connected between the central processing unit and the dynamic memory, the memory refresh controller including a refresh address counter providing a memory address for future memory refresh by the memory refresh controller, wherein the system controller further includes a comparator for comparing the current memory address accessed by the central processing unit and the current memory address provided by the refresh address counter, the refresh address counter being arranged to skip its current memory address if determined by the comparator to be corresponding to the current memory address accessed by the central processing unit.

4. A comparator as claimed in claim 3, wherein the dynamic memory is arranged in sequential groups of every 32 bytes of memory elements in such a manner that all the memory elements of a particular group will be refreshed simultaneously in a single refresh operation by the memory refresh controller.

5. A computer including a central processing unit, dynamic memory and a system controller incorporating a memory refresh controller for the dynamic memory and connected between the central processing unit and the dynamic memory, wherein the system controller includes means for identifying instructions issued by the central processing unit and to be executed not involving the dynamic memory, and the memory refresh controller is arranged to perform simultaneous memory refresh in response to detection by said means of such an instruction.

6. A computer as claimed in claim 5, wherein the system controller includes counter means for inhibiting the memory refresh controller against refreshing the dynamic memory above a predetermined frequency.

7. A computer including a central processing unit, dynamic memory, a system controller connected between the central processing unit and the dynamic memory, and a peripheral input/output device, the system controller including means arranged to detect a write instruction for the input/output device and in response to write the same write data into the dynamic memory for future reference by the central processing unit upon issuing the input/output device an equivalent read instruction which is to be replaced by the reference to the dynamic memory for the same data.

8. A computer as claimed in claim 7, wherein the system controller is arranged to take over a said input/output write instruction from the central processing unit and to provide a ready signal to relieve the central processing unit while the input/output instruction is executed by the system controller.