GB9124237D0 - Computer - Google Patents

Computer

Info

Publication number
GB9124237D0
GB9124237D0 GB919124237A GB9124237A GB9124237D0 GB 9124237 D0 GB9124237 D0 GB 9124237D0 GB 919124237 A GB919124237 A GB 919124237A GB 9124237 A GB9124237 A GB 9124237A GB 9124237 D0 GB9124237 D0 GB 9124237D0
Authority
GB
United Kingdom
Prior art keywords
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB919124237A
Other versions
GB2261537A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TECHFUL INTERNATIONAL Ltd
Original Assignee
TECHFUL INTERNATIONAL Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TECHFUL INTERNATIONAL Ltd filed Critical TECHFUL INTERNATIONAL Ltd
Priority to GB9124237A priority Critical patent/GB2261537A/en
Publication of GB9124237D0 publication Critical patent/GB9124237D0/en
Publication of GB2261537A publication Critical patent/GB2261537A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1636—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
GB9124237A 1991-11-14 1991-11-14 Computer Withdrawn GB2261537A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB9124237A GB2261537A (en) 1991-11-14 1991-11-14 Computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9124237A GB2261537A (en) 1991-11-14 1991-11-14 Computer

Publications (2)

Publication Number Publication Date
GB9124237D0 true GB9124237D0 (en) 1992-01-08
GB2261537A GB2261537A (en) 1993-05-19

Family

ID=10704646

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9124237A Withdrawn GB2261537A (en) 1991-11-14 1991-11-14 Computer

Country Status (1)

Country Link
GB (1) GB2261537A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0691616A1 (en) * 1994-07-08 1996-01-10 Advanced Micro Devices, Inc. RAM and ROM control unit
US5873114A (en) * 1995-08-18 1999-02-16 Advanced Micro Devices, Inc. Integrated processor and memory control unit including refresh queue logic for refreshing DRAM during idle cycles

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4060849A (en) * 1975-10-28 1977-11-29 Compagnie Internationale Pour L'informatique Cii-Honeywell Bull Data input and output controller
US4783739A (en) * 1979-11-05 1988-11-08 Geophysical Service Inc. Input/output command processor
US4901232A (en) * 1983-05-19 1990-02-13 Data General Corporation I/O controller for controlling the sequencing of execution of I/O commands and for permitting modification of I/O controller operation by a host processor
US4939644A (en) * 1983-05-19 1990-07-03 Data General Corporation Input/output controller for controlling the sequencing of the execution of input/output commands in a data processing system
CA1228677A (en) * 1984-06-21 1987-10-27 Cray Research, Inc. Peripheral interface system

Also Published As

Publication number Publication date
GB2261537A (en) 1993-05-19

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)