JP3506919B2 - Timer control method when tracing all instructions - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer,
Processor, electronic exchange, workstation, etc.
Central processing unit (hereinafter abbreviated as CPU)
To control the timer when tracing all instructions.
I do. [0002] 2. Description of the Related Art Generally, evaluation is performed for the purpose of performance evaluation or the like.
The program of the target operating system (the operating
All applications running on the rating system
For tracing all instructions, including
Of the instruction group (excluding programs, omitted below), the CPU
Information about all the instructions to be executed (the
Contents, instruction length, register change status, changed register
The contents of the program and other management units for the program as needed
Information such as thread information) immediately before execution of one instruction
Is called an all-instruction trace.
Traces the information collected by the trace into all instruction trace data.
Say ta. The above program is a function (from the program
Called program with one entrance)
Program (call triggered by interrupt, etc.)
This is a program that is normally
Not executed), and all instruction traces
And all of them are traced (only functions
A trace that only traces all instructions is called an all-instruction trace.
I don't know). A CP having a single-step interrupt function
In the full instruction trace under U, the function
Set the trace flag of the CPU to ON in advance and interrupt
For processing only, the trace flag of the CPU
Is turned on, etc., the CPU is instructed immediately before the execution of one instruction.
Cause a single-step interrupt
Has been done. [0004] The CPU is the operating system to be evaluated.
Each time immediately before executing one instruction of the system,
CPU uses a single-step interrupt
Single-step interrupt processing program for instruction trace
Control to the program, and the program
Data and collectively call the all-instruction trace data buffer.
Store in the memory area and return to the interrupt source.
After returning, the CPU issues one instruction to the interrupted instruction.
Instruction, and after the execution, execute the next instruction
Immediately before, a single-step interrupt occurs as described above.
The operating system to be evaluated.
All the instructions to be executed in the instruction group of the system program
Are traced. Trace all instructions
The data buffer has a limited fixed size,
The total amount of all instruction trace data is the operating
Tens of megabytes depending on the operating logic of the
Since it is common for the size to reach several gigabytes,
All the instruction trace interrupt processing of the above data
By storing the program in the secondary storage device,
Make sure that the file does not overflow. The secondary storage
Since high speed is generally required for the
Or a hard disk drive. On the other hand, the operating system is
For programs that run on the rating system
Provides a timer control function. Its timer control machine
Noh is a hardware timer (for example, of INTEL 82378)
Use the system timer inside. In particular,
The timer periodically raises an interrupt to the CPU,
Interrupt processing program
Call the timer processing routine and
Inside the software in the operating system
Update the value of the timer, and based on the update result,
Performs timer-related processing. However, the above-mentioned all-instruction trace is executed.
Then, every time one instruction of the operating system is executed,
Collect all trace data and all instructions collected as appropriate
Trace data must be output to secondary storage
And interrupts are prohibited between them.
For this reason, while performing the full instruction trace,
The rating system ensures that all instruction traces are
Operates at about 1 / 5000th the speed of the case without
Result. As a result, if no action is taken, the operating
From the viewpoint of the switching system, the timer is relatively 50
It appears to be operating 00 times faster, and as a result
Instruction trace data is mostly trace data of timer processing.
Data is occupied by the
Source data cannot be obtained. As a countermeasure, a system timer is periodically set.
It is sufficient if the typical interrupt interval can be increased by 5000 times.
The regular interrupt interval of the system timer is 10ms
ec and the timer specification is 50
It does not allow setting to 00 times. For example, currently
The most used timer is in INTEL 82378
System timer, which can be set
The maximum value of the interval is 54.924 msec. Therefore, in the prior art, those problems are
The following method was used to avoid the problem. (1) Timer interrupt processing program,
And its extension (the interrupt processing program
The program that is called from the
Not be traced (do not collect all instruction trace data).
No). Specifically, when an interrupt occurs, the CPU
Turns off the trace flag of CPU and interrupts
Pass control to the processing program,
At the top of the interrupt processing program, [All instruction
Source (external variable) is ON] CPU trace file
Set the lag to ON to continue all traces
However, in the timer interrupt processing program,
By not turning on the CPU trace flag at the beginning
The interrupt handling program and its extensions
Do not collect trace data for all instructions of the running routine.
No. (2) Thailand in the operating system
For all programs that use the
Stop using the timer function or request the timer function
Is changed to be 5000 times. Conventionally, the above method is
System, when the timer is low on the system
And was used only for system error handling
(All instruction traces are performed for performance evaluation.
Performance evaluation focuses on the evaluation of normal processing under high load.
Is a reasonable method (because there is) and there are no problems
Was. [0013] However, in recent years,
In various operating systems, the timer
System that uses the
I have. In evaluating the performance of such systems,
All traces including all instruction trace data of
Data acquisition is essential, and traditional methods
There is a problem that they cannot be realized. The present invention has been made in view of the above,
The goal is to get the operating system
The timer processing function is controlled by the external variable
It is possible to drive at a specified frequency, and
All trace data including the execution of
Timer control method when tracing all instructions
To provide. [0015] Means for Solving the Problems To achieve the above object,
Therefore, the present invention described in claim 1 provides a central processing unit in an information processing apparatus.
The operation unit traces all instructions, and this trace target
Operating systems periodically interrupt
Use the rub timer and the operating
If the processing of the scanning system is also subject to
If this periodic interrupt occurs, a timer interrupt
The process adds 1 to the timer counter which is an external variable,
Completion of interrupt processing for this interrupt
Notify, but call, timer
Perform full instruction trace for immer interrupts, and
The counter is cleared to 0 when the value of the counter is an external variable.
Only when the timer running frequency value has been reached,
Timer interrupt, Interrupt in interrupt disabled state
Represent occurrenceIf the interrupt is pending, trace all instructions
Data is stored only in the buffer.
The gist is to suppress output to the next storage device. According to the first aspect of the present invention, the operation
The timer processing function of the
It is possible to drive at the frequency of 1 / min
And including the execution of timer interrupt processing at that frequency
All collected trace data. [0017] DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing an embodiment of the present invention.
First, a timer control method at the time of tracing all instructions according to the present invention
Will be described. (1) As an external variable for tracing all instructions
A variable called timer running frequency is set, and the necessary frequency
Degree (in the embodiment, 5000;
Is set in advance (the setting method is not specified; outside)
You can keep them as part constants,
And may be set internally to the variable). (2) External variables for tracing all instructions
And set a variable called timer counter and set it to 0 in advance
(The setting method is not specified.) (3) Control when a timer interrupt occurs
The top of the timer interrupt processing program to be passed
Then, 1 is added to the timer counter, and the result is
Check whether it is more than the timer running frequency,
(A) If the check result is NO, E
Issued an I / O instruction to send OI (interrupt end)
Then, by issuing an IRET instruction,
Processing ends (return to the interrupt source. In this case, the timer processing
Process routine is not called and the timer interrupt
Grams are not fully traced. (Emission of EOI is actually
Although it is necessary in the embodiment, the connected interrupt control
This may not be necessary if the device is sophisticated. Less than
Omitted below). (B) If the check result is YES, the timer
-Clear counter to 0 and set CPU trace flag to O
After setting to N, same as the conventional timer interrupt program
EOI (End of interrupt) sent to timer
Call the timer processing routine, and the routine
At the time of turn, issue IRET command
To end the interrupt processing (conventional timer allocation).
Program that operates as an extension program
All programs run with the probability of timer running frequency
And all instructions are traced). (4) Single step for tracing all instructions
The interrupt processing program is a buffer for all instruction traces.
Data in the instruction trace secondary storage device as appropriate,
In units of one block (512 bytes in the embodiment)
Output, each time immediately before writing each block, a timer
Check if there is an interrupt pending
If there is only a hold, skip the processing after the output routine.
Return to return to the secondary storage device.
Suppress output. This allows timer interrupt processing
Is greatly increased by output to the secondary storage device for all instruction traces
Realize that you will not be delayed. In this case,
Instruction single-step interrupt processing program interrupts
Interrupt after returning to the source with an IRET instruction
Timer interrupt occurs when the
You. In this case, the output to the secondary storage device is performed as described above.
The part where the force is suppressed is when the timer interrupt occurs
At this point, the interrupt pending bit is turned off,
For tracing all instructions immediately after completion of Immer interrupt processing
When running the single step interrupt processing program,
Output to the secondary storage device. The buffer should not overflow.
Make it large enough (in the embodiment, 5MB is no problem
Did not.) (5) All instructions single step interrupt processing
Management program (prevents hardware overrun, etc.
In the past, the entrance and interruption of interrupt processing
Detect immediately before the execution of the instruction at the end address of the processing, and
During the period, all instruction trace data is stored in the secondary storage device.
Is controlled not to be output to the buffer (only stored in the buffer)
However, the same control applies to timer interrupt processing.
(In the conventional processing, the timer interrupt
Was not the target of the
Dress all instructions single step interrupt processing program
Because he is not conscious). As described above, the operating system
Timer processing routine traces all instructions
Time when not running, when not running
It is possible to run with a relative time relationship almost close to
Timer interrupt processing and
Trace data of all instructions of the program
Data can be obtained. In the present invention, as described above,
External variable called timer driving frequency and timer counter
An external variable is provided, and the timer counter is
Counts up when the timer periodically raises an interrupt.
If the result is higher than the timer driving frequency,
The conventional timer interrupt processing and its extension
Call programs that run on and live them all
And if it is less than the timer driving frequency,
Operates with conventional timer interrupt processing and its extensions
Do not call the program to be made, and all the instructions
No tracing, and secondary storage for all instruction traces
Timer interrupt pending detected in device output routine
To appropriately execute the timer interrupt processing, and
Instruction single-step interrupt processing program
Be aware of the entrance and exit addresses of the
By appropriately suppressing the output of instruction trace data,
It is possible to trace all instructions of conventional timer processing.
In addition to the traditional timer related processing,
Instruction tracing is performed when all instruction tracing is performed.
Drive at the same frequency as the relative driving frequency when not
To make things possible. For example, measuring the execution time of a program
If you get the timer value at the beginning and end of the program,
The execution time is measured from the difference,
Measurement value when all instruction tracing is not performed,
Command, and obtain the measured value when the
Adjust the value of "Timer Frequency" so that
If all instruction traces are performed,
"Timer frequency" minutes compared to not racing
The system operates at the low speed of 1
Run at about the same relative frequency as when no tracing was done.
And trace all instructions at that time
Data can be collected. Next, an embodiment of the present invention will be described with reference to the drawings.
About timer control method when tracing all instructions
I will tell. FIG. 1 is a diagram illustrating an entire instruction tray according to an embodiment of the present invention.
Shows the configuration of the device that implements the timer control method at the time of
It is a block diagram. The embodiment shown in FIG.
CPU 1 having a step interrupt function (for example, INTEL
Pentium), interrupt control chip 2 (for example, INTEL 82
59), system timer 3 (for example, in INTEL 82378)
System timer), for all instruction trace data
Secondary storage device 4 (for example, IDE secondary HD, I
RQ number 15), and a memory 5. memory
5 is a timer interrupt processing for the operating system.
Management program 50, other for operating system
Information 51, single-step interrupt for all instruction traces
Processing program 52, secondary storage for all instruction traces
Output function 53, all instruction trace secondary storage device
File 54 and other information 55 for the full instruction trace.
I remember. First, a single-step interrupt function is provided.
The CPU 1 executes the interrupt control chip 2 and the signal line.
And whether or not there is an interrupt from the chip,
Chip status information, etc.
Output information such as notification of the completion of interrupt reception to the
Wear. Further, the CPU 1 has a system timer 3,
Storage device 4 and memory 5 for command trace data
Connected by a bus, and
And information can be read and written. memory
The information in 5 is the timer assignment for the operating system.
Embed processing program 50, other information 51, and
Single step interrupt used for all instruction traces
Processing program 52, an output function 53 of the secondary storage device,
Secondary storage buffer 54 and other information 55
It is composed of Next, the flowcharts shown in FIGS.
The operation of the embodiment shown in FIG. 1 will be described with reference to FIG.
You. Figure 2 shows the timer assignment for the operating system.
Is a flowchart showing the procedure of the embedding processing program 50.
Yes, Figure 3 shows a single step interrupt for all instruction traces
Showing a part of the procedure of the only processing program 52
Figure 4 shows a single step split for all instruction traces.
3 shows a part of the procedure of FIG.
FIG. 5 is a flow chart showing the procedure for tracing all instructions.
Flowchart showing the procedure of the output function 53 of the secondary storage device
It is. Now, the system timer 3 is periodically interrupted.
Through the IRQ number 0 of the interrupt control chip 2
Raised to CPU1 with single-step interrupt function
An example will be described. At that time, the system is alive
Command trace execution status [CPU trace flag is O
N (1), in other information 55 for tracing all instructions
The external variable for all instruction trace
"Medium" is ON] and other information 55 for tracing all instructions
Variable "timer count" for tracing all instructions in the
The contents of counters such as “Timer” are 0, and “Timer running frequency” is
5000. These values are set in advance by some method
Have been. In general, the system timer starts from IRQ number 0
Interrupt request for single-step interrupt function
CPU1 (hereinafter abbreviated as CPU1)
At this time, if the CPU 1 is not in the interrupt disabled state (* 0),
CPU1 turns off the trace flag inside CPU1.
And the address of the instruction that was about to be executed at that time
Is stored in the stack, and the CPU 1 executes the operation shown in FIG.
Interrupt processing program 50 for operating system
Is transferred to the instruction of step S100. As shown in FIG.
System timer interrupt processing program 50
Is passed, the minimum required level is saved in register 1
Additional information for operating systems, such as registers
Stack area 51 (hereinafter abbreviated as stack area).
(Step S100), and the external variables “all instructions”
Check whether the contents of "Trace in progress" is ON
(Step S101). In this case, YES
Add 1 to the external variable “timer counter” (this
In this case, the result is 1) (step S102).
The result is the content of the external variable “Timer running frequency” (this
Check if it is 5000 or more (step
S103), since the result is NO in most cases,
In the case of, the end of the interrupt is notified to the interrupt control chip 2.
EOI is sent (step S104), and
In recovery 1 of the register etc., the contents of the register etc.
(A) (Step S105), and issue an IRET instruction.
(Step S106). As a result, interrupt processing
And returns to the interrupt source (step S106).
In general, when the trace flag of CPU1 is interrupted
The state at the time is returned by the CPU 1. The above steps S100 to S10
The operation of 6 is that when a timer interrupt occurs,
Just add 1 to the timer counter and those
No trace of all instructions is performed. This behavior is
Then, the value of the timer running frequency (50
00) until the number of interrupts occurs
It is repeated every time a jam occurs. Here, the value of the timer counter is now
Value of the immersion driving frequency −1 ”(that is, 4999).
Sometimes, assuming that a timer interrupt occurs,
The following operations different from the above are performed. First, in step S100, a register or the like is deleted.
Evasion 1 is performed, and all instructions are traced in step S101.
Check whether it is in the middle and the result is YES.
In step S102, 1 is added to the timer counter.
In step S103, the result is 5000.
Check whether the running frequency is 5000 or more.
Step S107, since the result is YES.
To reset the timer counter to 0, and
The source flag is set to ON (step S108),
In step S109, an instruction for saving 2
Attempt to execute (* 1). At this time, the CPU 1
Trace flag is set to ON.
A step interrupt occurs and attempts to execute at that time.
The address of the instruction
The stack area in the other information 51 (hereinafter referred to as the stack area)
Area (abbreviated as area)
After lag is set to OFF, for all instruction traces in Figure 3
The control is controlled by the single-step interrupt processing program 52.
Cross (the above processing is a single step interrupt function
To single-step interrupt of CPU1 "having
This is a general function of a CPU that operates. In FIG. 3, at step S200, the cash register
The stacker is evacuated to the stack area, and the
Check during execution of all instruction traces, YES
In step S203, all the instruction trace buffers are full.
Check if there is a bug, here, unless there is a bug in the system
No, all instructions are traced in step S205.
Collect data and back up all instruction trace secondary storage
And stored in the buffer 54 in step S206.
All stored instruction trace data is 512 bytes or less
Check if it is above. The trace data of all instructions has an average of one instruction.
Since the information is about 50 bytes, step S206
Is less than one-tenth and the majority
In this case, step S206 is NO. NO place
In this case, step S300 and step S302 in FIG.
Is performed. In this case, those things
Of the instruction that was interrupted in the single-step interrupt processing
Is the above (* 1), and corresponds to step S in the flowchart.
Step S300 and step S300.
Of the check in step S302, only step S300
YES, and in step S301, all instruction
The external variable “secondary storage” in the other information 55 for the source
1 is added to the "device write inhibit counter" and the result is
Becomes 1. Thereafter, in step S304, the number of times the register
And an IRET instruction is issued in step S305.
By doing so, it returns to the interrupt source of (* 1) above (that
At this time, the trace flag is
Return to the previous state. In this case, return to ON). This "secondary storage device write inhibit count"
Is a timer interrupt for the operating system.
Processing program 50 for the operating system
Other interrupt processing programs in other information 51
RAM or I / O function is secondary storage or other device
(Omitted in FIG. 1)
To the device for the operating system.
Issuing a series of I / O instructions (on the way,
Data output to the secondary storage device for data
Exists to prevent overrun, and 0 or more
When it is outside, all instruction trace data is stored in the secondary storage device.
Output is suppressed. Returning to the interrupt source of (* 1), the CP
U1 executes only one instruction in step S109 of FIG.
Since the CPU trace flag is ON,
From the next instruction in step S109,
Each instruction up to the instruction immediately before the step is executed one after another.
To execute (* 2), just before the execution of each instruction,
A single-step interrupt occurs,
In this case, a single step for tracing all instructions in FIG.
Step S200 and subsequent steps of the interrupt processing are executed. This
In the case of, the secondary storage device write inhibit counter is set to 1.
Are performed, steps S200, S201, S20
After Steps S205 and S205 have been executed, in Step S206
All instruction trace data of 512 bytes or more
However, since step S207 is NO, step S207
208 (secondary storage for full instruction trace)
Output function is never called). Also,
Then, check in steps S300 and S302.
The addresses in (* 2) above are all NO
So single-step interrupt handling for all instruction traces
In step S205, the program executes the all instruction trace data.
Just collect data and store it in the buffer, and secondary storage
Without outputting to the device, the registration is performed in step S304.
Data, etc., and execute an IRET instruction in step S305.
Return to interrupt source (* 2). Next, the CPU 1 proceeds to step S112.
After executing the previous instruction, execute the instruction of step S112
(* 3), and at that time,
Step S200, S
Steps S201 and S203 are executed.
Instruction trace data is collected, and Y is determined in step S206.
ES, NO in step S207, and step
No is obtained in S300, but in step S302,
Since it corresponds to the instruction of step S112 in the flowchart,
YES, and in step S303, the secondary storage device
The write-inhibit counter is decremented by 1 and returns to 0. Follow
After steps S304 and S305, the interrupt source
After the instruction of step S112 is executed, the next instruction
(Step S112 is usually a plurality of instructions
Therefore, the second instruction in step S112 is
Single step that occurs at (* 4) just before execution
In the interruption, steps S200, S201, S2
03, S205, S206, S207
At the time, the “secondary storage device write inhibit
Is "0" in the check to see if it is zero.
In step S208, the secondary storage device for tracing all instructions is output.
The force function (FIG. 5) is called (* 5). The output relation of the secondary storage device for all instruction traces
The number (FIG. 5) is the IRQ number 0 in step S400.
Has an interrupt pending (the next timer interrupt occurs
Whether or not the interrupt control chip 2
Issue an I / O instruction to read the interrupt pending state,
Check by checking its status, here,
Immediately after a timer interrupt occurs (in this embodiment,
The interrupt interval is 10 msec),
Since there is no stay, the process proceeds to step S401. In step S401, one block (one block)
Lock is 512 bytes), and all instruction trace data
Issue an input / output command to output the contents of the buffer to the secondary storage device.
Run. In this case, the buffer contains at least one
All instruction trace data related to timer interrupts
The amount is about 6 blocks on average (experience value)
is there. Then, in step S402, the writing is completed.
[I / O command is issued to input the status of the device.
The status of the device is not busy (input / output),
And the interrupt pending bit is set at IRQ number = 15.
Status (Complete interrupt by issuing the above I / O instruction
In a loop).
Check that it is completed normally in step S403.
And update the buffer management information ("All instructions
Length of data in trace data buffer "
Perform processing such as subtracting the output completion from the information).
(Step S405) In step S407, all instruction trays
512 bytes or more data in the data buffer
Check if there is. In this case, at least five blocks remain.
Therefore, the process returns to step S400 and returns to step S4.
Steps S00 to S407 are repeated for the remaining blocks. in this case,
Output to secondary storage device is sequential access
[Almost no head movement (seek)]
The total time of the output of these six blocks is calculated by the timer
Since it is smaller than the insertion interval (10 msec), step S4
YES at 00 (the next timer interrupt occurs
Interrupt pending). Then
Go to step S408 and return to the caller of this function
I do. The return is the instruction next to the above (* 5).
Therefore, the process proceeds to step S300, and
Since step S302 is NO, step S30
4, via S305, the above (* 4) is
Turn. This IRET instruction causes the CPU to
Return to the state of (* 4) above.
The second and subsequent instructions of S112 are executed, and all instruction trays are executed.
Is continued. From the above timer interrupt, the timer
When the time of the periodic interrupt interval (10 msec) has elapsed
Is one of the following (A), (B) and (C).
You. (A) “At that time, a single
An instruction other than the step interrupt processing program is being executed.
And interrupts are not disabled ”,
When execution of the instruction is completed, a timer interrupt occurs and
The same processing as after (* 0) is performed. (B) "At that time, a single instruction for all instruction traces
An instruction other than the step interrupt processing program is being executed.
And interrupts are disabled,
Interrupt pending bit (interrupt control
Interrupt pending bit of IRQ0, which is the internal information of loop 2)
Is turned on, and immediately after that, "Single
Until the step interrupt processing program runs (next
Interrupt pending)
Therefore, the operation at that time is described in (C) “All instruction trace
Instruction of the single-step interrupt processing program for
The operation is the same as in the case of "in line". (C) "At that time, a single for all instruction traces
Executing instruction of step interrupt processing program "
Single step interrupt for all instruction traces
Since the processing program runs without interrupts, the timer
-The interrupt pending bit of the interrupt turns on and
For example, the output function of the secondary storage device for tracing all instructions
Is called, YES in step S400
, So the function returns without doing anything,
Output to the command trace secondary storage device is suppressed. Follow
Therefore, by executing all instruction traces,
Until the instruction to execute is executed, the suppression continues.
At time (A), the timer interrupt is processed,
As described above, the timer interrupt processing has been completed.
At this point, output to the secondary storage device for all instruction traces resumes
Is done. As described above, the secondary storage device for all instruction traces
Timer interrupt processing is suppressed by
Will be executed when all instruction traces are executed.
Timer interrupt processing with the same relative frequency as when not performed
And the entire timer including the timer interrupt processing
Instruction tracing can be performed. [0051] As described above, according to the present invention,
Operate without any hardware changes
The timer processing function of the
It is possible to drive at the frequency specified in
All instructions including timer interrupt processing
It will be possible to race.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of an apparatus for implementing a timer control method at the time of tracing all instructions according to an embodiment of the present invention. FIG. 2 is a flowchart showing a procedure of a timer interrupt processing program for an operating system in the embodiment shown in FIG. 1; FIG. 3 is a flowchart showing a part of a procedure of an all-instruction trace single-step interrupt processing program in the embodiment shown in FIG. 1; FIG. 4 is a flowchart showing a part of the single-step interrupt processing program for tracing all instructions in the embodiment shown in FIG. 1 subsequent to FIG. 3; FIG. 5 is a flowchart showing a procedure of an output function of a secondary storage device for tracing all instructions in the embodiment shown in FIG. 1; [Description of Signs] 1 CPU having single-step interrupt function 2 Interrupt control chip 3 System timer 4 Secondary storage device 5 for all instruction trace data 5 Memory 50 Timer interrupt processing program 51 for operating system 51 Other information 52 for operating system Single instruction interrupt processing program 53 for tracing all instructions Output function 54 for secondary storage for tracing all instructions Buffer 55 for secondary storage for tracing all instructions Other information for tracing all instructions

Claims (1)

(57) [Claim 1] A central processing unit in an information processing apparatus traces all instructions, and the operating system to be traced uses a timer that periodically generates an interrupt. In the case of this periodic interrupt, the timer interrupt process adds 1 to the external variable, the timer counter, and completes the interrupt process for this interrupt when the operating system process for To the timer, call the actual timer processing routine, perform a full instruction trace for the timer interrupt, and set the counter to 0.
Clearing is performed only when the value of the counter reaches the value of the timer running frequency which is an external variable, and when the interrupt of the timer is in the interrupt pending state indicating the occurrence of an interrupt in the interrupt disabled state, A timer control method for tracing all instructions, wherein all instruction tracing data is stored only in a buffer and output to a secondary storage device for tracing all instructions is suppressed.