JP3459234B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP3459234B2 JP3459234B2 JP2001025307A JP2001025307A JP3459234B2 JP 3459234 B2 JP3459234 B2 JP 3459234B2 JP 2001025307 A JP2001025307 A JP 2001025307A JP 2001025307 A JP2001025307 A JP 2001025307A JP 3459234 B2 JP3459234 B2 JP 3459234B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- wafer
- semiconductor substrate
- manufacturing
- treatment layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、柱状電極を有す
る半導体装置およびその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a columnar electrode and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】例えばＣＳＰ(Chip Size Package)と呼
ばれる半導体装置には、図１０に示すようなものがあ
る。この半導体装置では、シリコン等からなる半導体基
板１の上面に接続パッド２が形成され、その上面の接続
パッド２の中央部を除く部分に絶縁膜３が形成され、絶
縁膜３に形成された開口部４を介して露出された接続パ
ッド２の上面から絶縁膜３の上面の所定の箇所にかけて
再配線５が形成され、再配線５の先端のパッド部上面に
柱状電極６が形成され、柱状電極６を除く上面全体に封
止膜７が形成され、柱状電極６の上面に電解メッキまた
は無電解メッキにより酸化防止用の表面処理層８が形成
され、表面処理層８の表面に半田ボール９が形成された
構造となっている。2. Description of the Related Art For example, a semiconductor device called CSP (Chip Size Package) is shown in FIG. In this semiconductor device, the connection pad 2 is formed on the upper surface of the semiconductor substrate 1 made of silicon or the like, the insulating film 3 is formed on a portion of the upper surface except the central portion of the connection pad 2, and the opening formed in the insulating film 3 is formed. The rewiring 5 is formed from the upper surface of the connection pad 2 exposed through the portion 4 to a predetermined position on the upper surface of the insulating film 3, and the columnar electrode 6 is formed on the upper surface of the pad portion at the tip of the rewiring 5. The sealing film 7 is formed on the entire upper surface except 6 and the surface treatment layer 8 for oxidation prevention is formed on the upper surface of the columnar electrode 6 by electrolytic plating or electroless plating, and the solder balls 9 are formed on the surface of the surface treatment layer 8. It has a formed structure.
【０００３】[0003]
【発明が解決しようとする課題】ところで、上記従来の
半導体装置では、半導体基板１の下面がむき出しとなっ
ているので、外部からの静電気等に起因するノイズを半
導体基板１自体で吸収することができない場合、電気的
なノイズが発生することがあり、また回路基板等の他の
電子部品に搭載する等の各種の作業時に半導体基板１に
クラックが発生することがあるという問題があった。特
に、半導体装置の厚さを薄くするために、半導体基板１
の下面を適宜に研磨した場合には、電気的なノイズが発
生しやすく、また半導体基板１にクラックが発生しやす
い。この発明の課題は、半導体基板の下面を電気的およ
び機械的に保護することである。By the way, in the above conventional semiconductor device, since the lower surface of the semiconductor substrate 1 is exposed, the semiconductor substrate 1 itself can absorb noise due to static electricity or the like from the outside. If it is not possible, there is a problem that electrical noise may occur, and a crack may occur in the semiconductor substrate 1 during various operations such as mounting on another electronic component such as a circuit board. In particular, in order to reduce the thickness of the semiconductor device, the semiconductor substrate 1
If the lower surface of is properly polished, electrical noise is likely to occur and cracks are likely to occur in the semiconductor substrate 1. An object of the present invention is to electrically and mechanically protect the lower surface of a semiconductor substrate.
【０００４】[0004]
【課題を解決するための手段】請求項１に記載の発明に
係る半導体装置は、上面に柱状電極および該柱状電極の
上面に酸化防止用の表面処理層が形成された半導体基板
と、前記柱状電極を除く前記半導体基板の上面に形成さ
れた封止膜と、前記半導体基板の下面のみに形成された
導電性樹脂膜とを具備することを特徴とするものであ
る。
（請求項２）
請求項１に記載の発明において、前記半導体基板の上面
に接続パッドと、該接続パッドに接続された再配線が形
成され、前記柱状電極は、前記再配線のパッド部上面に
形成されていることを特徴とする半導体装置。請求項３
に記載の発明に係る半導体装置は、請求項１に記載の発
明において、前記表面処理層の表面に半田ボールが形成
されていることを特徴とするものである。請求項４に記
載の発明に係る半導体装置は、請求項１〜３のいずれか
に記載の発明において、前記半導体基板の厚さは当該半
導体基板を得るためのウエハの当初の厚さよりも薄くな
っていることを特徴とするものである。請求項５に記載
の発明に係る半導体装置の製造方法は、上面に柱状電極
を有するウエハの前記柱状電極を除く上面全体に封止膜
を形成し、前記ウエハをダイシングして半導体基板を有
する個々のチップからなる半導体装置を得る半導体装置
の製造方法において、前記ウエハの下面に導電性樹脂膜
を形成した後、前記ウエハをダイシングし、半導体基板
の下面にのみ前記導電性樹脂膜が形成された半導体装置
を得ることを特徴とするものである。請求項６に記載の
発明に係る半導体装置の製造方法は、請求項５に記載の
発明において、前記封止膜を形成した後に、前記柱状電
極の上面に酸化防止用の表面処理層を形成することを特
徴とするものである。請求項７に記載の発明に係る半導
体装置の製造方法は、請求項６に記載の発明において、
前記表面処理層を形成した後に、該表面処理層の表面に
半田ボールを形成することを特徴とするものである。請
求項８に記載の発明に係る半導体装置の製造方法は、請
求項５〜７のいずれかに記載の発明において、前記ウエ
ハの下面を研磨してウエハを薄くした後、該ウエハの下
面に前記導電性樹脂膜を形成することを特徴とするもの
である。請求項９に記載の発明に係る半導体装置の製造
方法は、請求項５〜７のいずれかに記載の発明におい
て、前記ウエハ上の前記封止膜および前記柱状電極を研
磨した後、前記ウエハの下面を研磨してウエハを薄く
し、該ウエハの下面に前記導電性樹脂膜を形成すること
を特徴とするものである。Means for Solving the Problems A semiconductor device according to the first aspect of the present invention, the columnar electrodes and the columnar electrodes on the upper surface
A semiconductor substrate having a surface treatment layer for oxidation prevention formed on the upper surface, a sealing film formed on the upper surface of the semiconductor substrate excluding the columnar electrodes, and a conductive resin film formed only on the lower surface of the semiconductor substrate. And is provided. (Claim 2) In the invention according to claim 1, the upper surface of the semiconductor substrate.
The connection pad and the rewiring connected to the connection pad.
The columnar electrodes are formed on the upper surface of the pad portion of the rewiring.
A semiconductor device characterized by being formed . Claim 3
The semiconductor device according to the invention described in ( 1 ) is characterized in that, in the invention according to ( 1 ), solder balls are formed on the surface of the surface treatment layer. According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, the thickness of the semiconductor substrate is smaller than the initial thickness of a wafer for obtaining the semiconductor substrate. It is characterized by that. According to a fifth aspect of the present invention, there is provided a semiconductor device manufacturing method, wherein a sealing film is formed on an entire upper surface of a wafer having columnar electrodes on the upper surface except for the columnar electrodes, and the wafer is diced to form a semiconductor substrate.
In the method for manufacturing a semiconductor device, which obtains a semiconductor device including individual chips, a conductive resin film is formed on the lower surface of the wafer, the wafer is diced, and the semiconductor substrate
Device in which the conductive resin film is formed only on the lower surface of the semiconductor device
It is characterized by obtaining . According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fifth aspect, after forming the sealing film, a surface treatment layer for preventing oxidation is formed on an upper surface of the columnar electrode. It is characterized by that. According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the sixth aspect,
After forming the surface treatment layer, solder balls are formed on the surface of the surface treatment layer. According to an eighth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fifth aspect, the lower surface of the wafer is polished to make the wafer thinner, and It is characterized in that a conductive resin film is formed. A method of manufacturing a semiconductor device according to a ninth aspect of the present invention is the method of manufacturing the semiconductor device according to any one of the fifth to seventh aspects, wherein after the sealing film and the columnar electrodes on the wafer are polished, The lower surface is polished to thin the wafer, and the conductive resin film is formed on the lower surface of the wafer.
【０００５】[0005]
【発明の実施の形態】図１はこの発明の一実施形態にお
ける半導体装置の断面図を示したものである。この半導
体装置では、シリコン等からなる半導体基板２１の上面
に接続パッド２２が形成され、その上面の接続パッド２
２の中央部を除く部分に絶縁膜２３が形成され、絶縁膜
２３に形成された開口部２４を介して露出された接続パ
ッド２２の上面から絶縁膜２３の上面の所定の箇所にか
けて再配線２５が形成され、再配線２５の先端のパッド
部上面に柱状電極２６が形成され、柱状電極２６を除く
上面全体に該柱状電極の上面と同一の高さの上面を有す
る封止膜２７が形成され、柱状電極２６の上面に電解メ
ッキまたは無電解メッキにより酸化防止用の表面処理層
２８が形成され、表面処理層２８の表面に半田ボール２
９が形成され、半導体基板２１の下面に導電性樹脂膜３
０が形成された構造となっている。1 is a sectional view of a semiconductor device according to an embodiment of the present invention. In this semiconductor device, the connection pad 22 is formed on the upper surface of the semiconductor substrate 21 made of silicon or the like, and the connection pad 2 on the upper surface is formed.
The insulating film 23 is formed on a portion of the insulating film 23 other than the central portion, and the rewiring 25 extends from the upper surface of the connection pad 22 exposed through the opening 24 formed in the insulating film 23 to a predetermined position on the upper surface of the insulating film 23. The columnar electrode 26 is formed on the upper surface of the pad portion at the tip of the rewiring 25, and the sealing film 27 having the same height as the upper surface of the columnar electrode is formed on the entire upper surface excluding the columnar electrode 26. A surface treatment layer 28 for oxidation prevention is formed on the upper surface of the columnar electrode 26 by electrolytic plating or electroless plating, and the solder balls 2 are formed on the surface of the surface treatment layer 28.
9 is formed, and the conductive resin film 3 is formed on the lower surface of the semiconductor substrate 21.
It has a structure in which 0 is formed.
【０００６】次に、この半導体装置の製造方法の一例に
ついて、図２〜図７を順に参照して説明する。まず、図
２に示すように、図１に示す半導体基板２１を複数個得
るためのウエハ３１の上面に接続パッド２２が形成さ
れ、その上面の接続パッド２２の中央部を除く部分に絶
縁膜２３が形成され、絶縁膜２３に形成された開口部２
４を介して露出された接続パッド２２の上面から絶縁膜
２３の上面の所定の箇所にかけて再配線２５が形成さ
れ、再配線２５の先端のパッド部上面に高さ１００〜２
００μｍの柱状電極２６が形成されたものを用意する。
なお、図２において符号３２で示す領域は、ダイシング
ストリートに対応する領域である。Next, an example of a method of manufacturing this semiconductor device will be described with reference to FIGS. First, as shown in FIG. 2, the connection pad 22 is formed on the upper surface of the wafer 31 for obtaining the plurality of semiconductor substrates 21 shown in FIG. 1, and the insulating film 23 is formed on the upper surface of the connection pad 22 except the central portion. And the opening 2 formed in the insulating film 23.
The rewiring 25 is formed from the upper surface of the connection pad 22 exposed via 4 to a predetermined position on the upper surface of the insulating film 23, and the height of 100 to 2 is provided on the upper surface of the pad portion at the tip of the rewiring 25.
The thing in which the columnar electrode 26 of 00 μm was formed is prepared.
The area indicated by reference numeral 32 in FIG. 2 is an area corresponding to the dicing street.
【０００７】次に、図３に示すように、柱状電極２６お
よび再配線２５を含む絶縁膜２３の上面全体にエポキシ
系樹脂からなる封止膜２７をディスペンサ法、スクリー
ン印刷法、トランスファモールド法等により厚さが柱状
電極２６の高さよりもやや厚くなるように形成する。し
たがって、この状態では、柱状電極２６の上面は封止膜
２７によって覆われている。次に、ウエハ３１の下面全
体にカーボンインク、銀ペースト等からなる導電性樹脂
膜３０をスピンコート法、ディスペンサ法、スクリーン
印刷法、トランスファモールド法等により形成する。Next, as shown in FIG. 3, a sealing film 27 made of epoxy resin is formed on the entire upper surface of the insulating film 23 including the columnar electrodes 26 and the rewirings 25 by a dispenser method, a screen printing method, a transfer molding method or the like. Thus, the thickness is formed to be slightly thicker than the height of the columnar electrode 26. Therefore, in this state, the upper surface of the columnar electrode 26 is covered with the sealing film 27. Next, the conductive resin film 30 made of carbon ink, silver paste or the like is formed on the entire lower surface of the wafer 31 by a spin coating method, a dispenser method, a screen printing method, a transfer molding method or the like.
【０００８】次に、封止膜２７の上面側および柱状電極
２６の上面側を適宜に研磨することにより、図４に示す
ように、柱状電極２６の上面を露出させる。次に、図５
に示すように、柱状電極２６の上面に無電解メッキまた
はスパッタ等により酸化防止用の表面処理層２８を形成
する。スパッタによる場合は、マスクを用いて柱状電極
２６上のみに形成するか或いは、全面に成膜後マスクを
形成して封止膜２７上の表面処理層を除去する。次に、
図６に示すように、表面処理層２８の表面に半田ボール
２９を形成する。図５に戻って、表面処理層２８は、均
一な厚さに形成してもよく、その場合、封止膜２７と同
一の高さでは半田ボール２９との境界面に応力が集中す
るため、柱状電極２６の上面をエッチングにより除去し
た後、表面処理層２８を形成してもよい。次に、ウエハ
３１をダイシングストリート３２に沿って切断すると、
図７および図１に示すように、個々のチップからなる半
導体装置が得られる。Next, the upper surface of the sealing film 27 and the upper surface of the columnar electrode 26 are appropriately polished to expose the upper surface of the columnar electrode 26, as shown in FIG. Next, FIG.
As shown in, the surface treatment layer 28 for oxidation prevention is formed on the upper surface of the columnar electrode 26 by electroless plating, sputtering, or the like. In the case of sputtering, a mask is used to form only on the columnar electrodes 26, or a mask is formed after film formation on the entire surface to remove the surface treatment layer on the sealing film 27. next,
As shown in FIG. 6, solder balls 29 are formed on the surface of the surface treatment layer 28. Returning to FIG. 5, the surface treatment layer 28 may be formed to have a uniform thickness. In that case, stress concentrates on the interface with the solder ball 29 at the same height as the sealing film 27. After removing the upper surface of the columnar electrode 26 by etching, the surface treatment layer 28 may be formed. Next, when the wafer 31 is cut along the dicing streets 32,
As shown in FIGS. 7 and 1, a semiconductor device including individual chips can be obtained.
【０００９】このようにして得られた半導体装置では、
半導体基板２１の下面に導電性樹脂膜３０が形成されて
いるので、半導体基板２１の下面を電気的および機械的
に保護することができる。したがって、外部からの静電
気等に起因するノイズを半導体基板１自体で吸収するこ
とができない場合でも、電気的なノイズの発生を軽減す
ることができる。また、この半導体装置を回路基板等の
他の電子部品に搭載する等の各種の作業時において、半
導体基板２１にクラックが発生しにくいようにすること
ができる。In the semiconductor device thus obtained,
Since the conductive resin film 30 is formed on the lower surface of the semiconductor substrate 21, the lower surface of the semiconductor substrate 21 can be protected electrically and mechanically. Therefore, even if the semiconductor substrate 1 itself cannot absorb noise due to static electricity from the outside, the generation of electrical noise can be reduced. Further, it is possible to prevent the semiconductor substrate 21 from cracking during various operations such as mounting the semiconductor device on another electronic component such as a circuit board.
【００１０】なお、上記実施形態では、図６に示すよう
に、半田ボール２９を形成し、この後ウエハ３１をダイ
シングストリート３２に沿って切断し、図１に示す半導
体装置を得る場合について説明したが、これに限定され
るものではない。例えば、図５に示すように、表面処理
層２８を形成し、この後ウエハ３１をダイシングストリ
ート３２に沿って切断し、図８に示す半導体装置を得る
ようにしてもよい。また、図４に示すように、柱状電極
２６の上面を露出させ、この後ウエハ３１をダイシング
ストリート３２に沿って切断し、図９に示す半導体装置
を得るようにしてもよい。In the above embodiment, the solder balls 29 are formed as shown in FIG. 6, and then the wafer 31 is cut along the dicing streets 32 to obtain the semiconductor device shown in FIG. However, it is not limited to this. For example, as shown in FIG. 5, a surface treatment layer 28 may be formed, and then the wafer 31 may be cut along the dicing streets 32 to obtain the semiconductor device shown in FIG. Alternatively, as shown in FIG. 4, the upper surface of the columnar electrode 26 may be exposed, and then the wafer 31 may be cut along the dicing streets 32 to obtain the semiconductor device shown in FIG.
【００１１】また、上記実施形態では、図３に示すよう
に、導電性樹脂膜３０を封止膜２７を形成した後に形成
する場合について説明したが、これに限らず、要は、ウ
エハ３１をダイシングする前のいずれかの工程後であれ
ばよい。また、個々のチップである半導体装置の厚さを
薄くする場合には、ウエハ３１の下面に導電性樹脂膜３
０を形成する前にウエハ３１の下面を研磨することが能
率的である。その場合には、ウエハ３１の下面を研磨し
た後でウエハ３１をダイシングする前のいずれかの工程
で、ウエハ３１の下面に導電性樹脂膜３０を形成すれば
よいが、封止膜形成時の加熱などによりウエハ３１が変
形され且つ図４に示す封止膜２７の上面側および柱状電
極２６の上面側を研磨した後ならば、ウエハ３１の下面
を研磨することによりウエハ３１を能率的に平坦化でき
るので、封止膜２７の上面側および柱状電極２６の研磨
後、半田ボール２９を形成する前が好ましい。Further, in the above-described embodiment, as shown in FIG. 3, the case where the conductive resin film 30 is formed after the sealing film 27 is formed has been described, but the present invention is not limited to this. It may be after any step before dicing. Further, when the thickness of the semiconductor device, which is an individual chip, is reduced, the conductive resin film 3 is formed on the lower surface of the wafer 31.
It is efficient to polish the lower surface of the wafer 31 before forming 0s. In that case, the conductive resin film 30 may be formed on the lower surface of the wafer 31 in any step after polishing the lower surface of the wafer 31 and before dicing the wafer 31. After the wafer 31 is deformed by heating or the like and the upper surface side of the sealing film 27 and the upper surface side of the columnar electrodes 26 shown in FIG. 4 are polished, the lower surface of the wafer 31 is polished to efficiently flatten the wafer 31. Therefore, it is preferable that the upper surface side of the sealing film 27 and the columnar electrodes 26 are polished and then the solder balls 29 are formed.
【００１２】[0012]
【発明の効果】以上説明したように、この発明によれ
ば、半導体基板の下面のみに導電性樹脂膜を形成してい
るので、半導体基板の下面を電気的および機械的に保護
することができる。特に、この発明の半導体装置の製造
方法によれば、ウエハの下面に導電性樹脂膜を形成した
後、個々のチップに分離するので、半導体装置毎に導電
性樹脂を形成する方法に比し、生産性を向上することが
できる。 As described above, according to the present invention, since the conductive resin film is formed only on the lower surface of the semiconductor substrate, the lower surface of the semiconductor substrate can be protected electrically and mechanically. . In particular, the manufacture of the semiconductor device of the present invention
According to the method, a conductive resin film is formed on the lower surface of the wafer.
After that, it is separated into individual chips, so each semiconductor device is electrically conductive.
Productivity can be improved compared to the method of forming a water-soluble resin.
it can.
【図１】この発明の一実施形態における半導体装置の断
面図。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.
【図２】図１に示す半導体装置の製造に際し、当初用意
したものの断面図。FIG. 2 is a cross-sectional view of an initially prepared item in manufacturing the semiconductor device shown in FIG.
【図３】図２に続く製造工程の断面図。FIG. 3 is a cross-sectional view of the manufacturing process following FIG.
【図４】図３に続く製造工程の断面図。FIG. 4 is a cross-sectional view of the manufacturing process following FIG.
【図５】図４に続く製造工程の断面図。FIG. 5 is a cross-sectional view of the manufacturing process following FIG.
【図６】図５に続く製造工程の断面図。FIG. 6 is a cross-sectional view of the manufacturing process following FIG.
【図７】図６に続く製造工程の断面図。FIG. 7 is a cross-sectional view of the manufacturing process following FIG.
【図８】この発明の他の実施形態おける半導体装置の断
面図。FIG. 8 is a sectional view of a semiconductor device according to another embodiment of the present invention.
【図９】この発明のさらに他の実施形態おける半導体装
置の断面図。FIG. 9 is a sectional view of a semiconductor device according to still another embodiment of the present invention.
【図１０】従来の半導体装置の一例の断面図。FIG. 10 is a sectional view of an example of a conventional semiconductor device.
２１ 半導体基板 ２２ 接続パッド ２３ 絶縁膜 ２５ 再配線 ２６ 柱状電極 ２７ 封止膜 ２８ 表面処理層 ２９ 半田ボール ３０ 導電性樹脂膜 ３１ ウエハ ３２ ダイシングストリート 21 Semiconductor substrate 22 Connection pad 23 Insulating film 25 Rewiring 26 Columnar electrodes 27 Sealing film 28 Surface treatment layer 29 Solder balls 30 Conductive resin film 31 wafers 32 Dicing Street
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 H01L 23/28 ─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 23/12 H01L 23/28
Claims (9)
に酸化防止用の表面処理層が形成された半導体基板と、
前記柱状電極を除く前記半導体基板の上面に形成された
封止膜と、前記半導体基板の下面のみに形成された導電
性樹脂膜とを具備することを特徴とする半導体装置。1. A columnar electrode on an upper surface and an upper surface of the columnar electrode
A semiconductor substrate on which a surface treatment layer for oxidation prevention is formed,
A semiconductor device comprising: a sealing film formed on the upper surface of the semiconductor substrate excluding the columnar electrodes, and a conductive resin film formed only on the lower surface of the semiconductor substrate.
導体基板の上面に接続パッドと、該接続パッドに接続さ
れた再配線が形成され、前記柱状電極は、前記再配線の
パッド部上面に形成されていることを特徴とする半導体
装置。2. The invention according to claim 1, wherein the half
Connect the connection pad to the upper surface of the conductor board and the connection pad.
Rewiring is formed, the columnar electrode is
A semiconductor device, which is formed on the upper surface of a pad portion .
面処理層の表面に半田ボールが形成されていることを特
徴とする半導体装置。3. The semiconductor device according to claim 1 , wherein solder balls are formed on the surface of the surface treatment layer.
おいて、前記半導体基板の厚さは当該半導体基板を得る
ためのウエハの当初の厚さよりも薄くなっていることを
特徴とする半導体装置。4. The semiconductor according to claim 1, wherein the semiconductor substrate has a thickness smaller than an initial thickness of a wafer for obtaining the semiconductor substrate. apparatus.
状電極を除く上面全体に封止膜を形成し、前記ウエハを
ダイシングして半導体基板を有する個々のチップからな
る半導体装置を得る半導体装置の製造方法において、前
記ウエハの下面に導電性樹脂膜を形成した後、前記ウエ
ハをダイシングし、半導体基板の下面にのみ前記導電性
樹脂膜が形成された半導体装置を得ることを特徴とする
半導体装置の製造方法。5. A semiconductor device comprising: a wafer having columnar electrodes on the upper surface thereof; a sealing film formed on the entire upper surface excluding the columnar electrodes; and dicing the wafer to obtain a semiconductor device including individual chips having a semiconductor substrate . In the manufacturing method, after the conductive resin film is formed on the lower surface of the wafer, the wafer is diced so that the conductive film is formed only on the lower surface of the semiconductor substrate.
A method of manufacturing a semiconductor device, comprising obtaining a semiconductor device having a resin film formed thereon .
止膜を形成した後に、前記柱状電極の上面に酸化防止用
の表面処理層を形成することを特徴とする半導体装置の
製造方法。6. The method of manufacturing a semiconductor device according to claim 5, wherein after forming the sealing film, a surface treatment layer for preventing oxidation is formed on the upper surface of the columnar electrode.
面処理層を形成した後に、該表面処理層の表面に半田ボ
ールを形成することを特徴とする半導体装置の製造方
法。7. The method of manufacturing a semiconductor device according to claim 6, wherein after forming the surface treatment layer, a solder ball is formed on the surface of the surface treatment layer.
おいて、前記ウエハの下面を研磨してウエハを薄くした
後、該ウエハの下面に前記導電性樹脂膜を形成すること
を特徴とする半導体装置の製造方法。8. The invention according to claim 5, wherein the conductive resin film is formed on the lower surface of the wafer after polishing the lower surface of the wafer to thin the wafer. Of manufacturing a semiconductor device.
おいて、前記ウエハ上の前記封止膜および前記柱状電極
を研磨した後、前記ウエハの下面を研磨してウエハを薄
くし、該ウエハの下面に前記導電性樹脂膜を形成するこ
とを特徴とする半導体装置の製造方法。9. The invention according to claim 5, wherein after polishing the sealing film and the columnar electrodes on the wafer, the lower surface of the wafer is polished to thin the wafer, A method of manufacturing a semiconductor device, comprising forming the conductive resin film on a lower surface of a wafer.
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|---|---|---|---|
| JP2001025307A JP3459234B2 (en) | 2001-02-01 | 2001-02-01 | Semiconductor device and manufacturing method thereof |
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| JP3459234B2 true JP3459234B2 (en) | 2003-10-20 |
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| JP3617647B2 (en) | 2002-11-08 | 2005-02-09 | 沖電気工業株式会社 | Semiconductor device and manufacturing method thereof |
| JP3618330B2 (en) * | 2002-11-08 | 2005-02-09 | 沖電気工業株式会社 | Semiconductor device and manufacturing method thereof |
| JP3602118B2 (en) * | 2002-11-08 | 2004-12-15 | 沖電気工業株式会社 | Semiconductor device |
| JP3618331B2 (en) | 2002-11-08 | 2005-02-09 | 沖電気工業株式会社 | Semiconductor device and manufacturing method thereof |
| JP4056360B2 (en) | 2002-11-08 | 2008-03-05 | 沖電気工業株式会社 | Semiconductor device and manufacturing method thereof |
| JP3888302B2 (en) * | 2002-12-24 | 2007-02-28 | カシオ計算機株式会社 | Semiconductor device |
| JP3844467B2 (en) | 2003-01-08 | 2006-11-15 | 沖電気工業株式会社 | Semiconductor device and manufacturing method thereof |
| TWI239581B (en) | 2003-01-16 | 2005-09-11 | Casio Computer Co Ltd | Semiconductor device and method of manufacturing the same |
| JP4303547B2 (en) | 2003-01-30 | 2009-07-29 | Ｎｅｃエレクトロニクス株式会社 | Semiconductor device |
| JP3929966B2 (en) * | 2003-11-25 | 2007-06-13 | 新光電気工業株式会社 | Semiconductor device and manufacturing method thereof |
| JP2005340655A (en) | 2004-05-28 | 2005-12-08 | Shinko Electric Ind Co Ltd | Method for manufacturing semiconductor device, and structure for supporting semiconductor substrate |
| WO2006008795A1 (en) * | 2004-07-16 | 2006-01-26 | Shinko Electric Industries Co., Ltd. | Semiconductor device manufacturing method |
| JP4214968B2 (en) * | 2004-08-16 | 2009-01-28 | 沖電気工業株式会社 | Semiconductor device and manufacturing method thereof |
| JP4214969B2 (en) * | 2004-08-16 | 2009-01-28 | 沖電気工業株式会社 | Manufacturing method of semiconductor device |
| JP4131256B2 (en) * | 2004-08-16 | 2008-08-13 | 沖電気工業株式会社 | Semiconductor device and manufacturing method thereof |
| JP4890827B2 (en) * | 2004-09-29 | 2012-03-07 | ローム株式会社 | Semiconductor device |
| JP5036127B2 (en) * | 2004-10-26 | 2012-09-26 | オンセミコンダクター・トレーディング・リミテッド | Manufacturing method of semiconductor device |
| JP2010251791A (en) * | 2010-06-24 | 2010-11-04 | Sanyo Electric Co Ltd | Semiconductor device and method of manufacturing the same |
| JP7430515B2 (en) | 2019-11-06 | 2024-02-13 | 株式会社ディスコ | Wafer processing method |
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