JP2000228420A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability when a chip-size package is mounted. SOLUTION: An upper electrode 12 having an upper surface of an area larger than the upper surface of a metal post 9 is provided on the upper surface of the metal post 9, and a solder ball 15 is mounted thereon. Consequently, the contact area between the solder ball 15 and the metal post 9 can be made large. Therefore, the strength against the shearing stress can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same. More specifically, the present invention relates to a technique for improving the reliability of a chip size package.
Chip Size Package is C
Also referred to as SP, it is a general term for packages equal to or slightly larger than the chip size, and is a package for high-density mounting. The present invention relates to a technique for improving the reliability of a chip size package.

[0002]

2. Description of the Related Art Conventionally, in this field, BGA (Ba
ll Grid Array), a structure with a plurality of solder balls arranged in a plane, called a fine pitch BGA.
A structure in which the G outer shape is close to the chip size is known.

Recently, there is a wafer CSP described in “Nikkei Microdevice”, August 1998, pp. 44-71. This wafer CSP is basically a CSP in which wiring or array-like pads are formed by a wafer process (pre-process) before dicing a chip.
It is expected that this technology will integrate the wafer process and the package process (post-process), thereby greatly reducing the package cost.

There are two types of wafer CSP: a sealing resin type and a rewiring type. The sealing resin type has a structure in which the surface is covered with a sealing resin, similar to a conventional package. A columnar terminal (metal post) is formed on the wiring layer on the chip surface, and the surrounding area is sealed with the sealing resin. It is a structure that hardens. When the package is mounted on a printed circuit board, stress generated due to a difference in thermal expansion from the printed circuit board is concentrated on the metal posts. In general, it is known that the longer the metal post, the more the stress is dispersed.

On the other hand, in the rewiring type, as shown in FIG.
This is a structure in which rewiring is formed without using a sealing resin. An Al electrode 52, a wiring layer 53, and an insulating layer 54 are formed on the surface of the chip 51.
Are stacked, a metal post 55 is formed on the wiring layer 53, and a solder bump 56 (also called a solder ball) is formed thereon. The wiring layer 53 is formed of
6 are used as a rewiring for arranging them on a chip in a predetermined array.

[0006] The encapsulation resin type has a metal post of 100 μm.
By increasing the length to about m and reinforcing it with a sealing resin, high reliability can be obtained. However, the process of forming the sealing resin needs to be performed using a mold in a later step, and the process becomes complicated. On the other hand, the rewiring type has an advantage that the process is relatively simple and most of the steps can be performed by a wafer process. However, there is a need to relieve stress in some way to increase reliability.

[0007]

FIG. 12 is a sectional view showing a case where the above-described chip size package 57 is mounted on a printed circuit board. The solder balls 56 are in contact with the copper electrodes 60 wired on the printed board 61. However, due to the difference in the thermal expansion coefficient between the printed circuit board and the chip size package 57, the solder ball 56 may be broken when the temperature cycle test is performed in the mounted state. In particular, it has been found that a large shear stress is generated at the interface between the solder bump 56 and the metal post 55.

The present invention has been made in view of the above problems, and has as its object to improve the stress resistance of a chip size package and to increase the reliability during mounting.

[0009]

According to the present invention, there is provided a semiconductor device comprising:
A metal electrode pad formed on a semiconductor substrate, a wiring layer connected to the metal electrode pad and extending on the surface of the semiconductor substrate, an insulating layer covering the surface of the semiconductor substrate including the wiring layer, and the insulating layer Opening, a columnar terminal formed in the opening and connected to the wiring layer, an upper electrode provided on the upper surface of the columnar terminal, and a solder ball mounted on the upper electrode. Wherein the area of the upper surface of the upper electrode is larger than the area of the upper surface of the columnar terminal.

[0010] The strength of the interface between the columnar terminal and the solder ball against the shear stress is proportional to the contact area thereof. Therefore, by providing an upper electrode having a large upper surface area on the columnar terminal and mounting a solder ball on the upper electrode, the contact area can be increased, and the strength against shear stress can be improved.

In addition, since the metal posts tend to become thinner with the miniaturization of the wiring layer, the contact area between the columnar terminals and the solder balls is reduced in the conventional metal posts. Even if the metal post itself becomes thin, the contact area can be sufficiently ensured because it has the upper electrode having a large upper surface area.

[0012]

Next, an embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG. 1, a semiconductor substrate 1 (wafer) on which an LSI having an Al electrode pad 2 is formed is prepared, and the surface of the semiconductor substrate 1 is covered with a passivation film 3 such as a SiN film. Al electrode pad 2 is L
Pad for external connection of SI.

Next, as shown in FIG. 2, a polyimide film 4 is formed on the entire surface for planarization. Then, the passivation film 3 and the polyimide film 4 on the Al electrode pad 2 are removed by etching.

Next, as shown in FIG. 3, a first plating electrode layer 5 (also called a seed layer) made of a Cu layer is formed by sputtering.

Next, a wiring layer connected to the Al electrode pad 2 is formed. This wiring layer needs to be formed to a thickness of about 5 μm in order to secure mechanical strength, and is suitably formed by using a plating method. As shown in FIG. 4, a first photoresist pattern layer 6 is formed on the first plating electrode layer 5.
Then, as shown in FIG. 5, a wiring layer 7 made of a Cu layer is formed by electroplating in a region where the first photoresist pattern layer 6 is not formed. Thereafter, the first photoresist pattern layer 6 is removed.

Next, as shown in FIG. 6, a second photoresist pattern layer 8 having an opening in a metal post formation region on the wiring layer 7 is formed. Then, a metal post 9 is formed in the opening as a columnar terminal made of a Cu layer by electrolytic plating.

Next, as shown in FIG. 7, a second plating electrode layer 10 made of a Cu layer is formed on the entire surface. And
A third photoresist pattern layer 11 is formed on the second plating electrode layer 10. Third photoresist pattern 1
1 has an opening on the metal post 9. The opening surrounds the top surface of the metal post 9 and is wider than the opening.

Then, an upper electrode 12 made of a Cu layer is formed in the opening by electrolytic plating. Upper electrode 1
A barrier layer 13 composed of a Ni layer / Au layer is further formed on the upper surface of 2. The barrier layer 10 composed of the Ni layer / Au layer may be formed by electroless plating by exposing the upper surface of the metal post 9 after resin sealing.

Next, as shown in FIG. 8, the second and third photoresist patterns 8, 11 and the second plating electrode layer 10 are removed using a resist stripper. Further, the portion under the wiring layer 7 is removed from the first plating electrode layer 5 using, for example, a mixed solution of nitric acid and acetic acid.

Thereafter, the structure formed as described above is sealed with an insulating layer 14 made of a polyimide layer or a mold resin layer. At least the upper surface of the upper electrode 12 is exposed by polishing the insulating layer 14 or the like, and the solder ball 15 is mounted and crimped on the exposed surface by using a known method such as a vacuum suction method.

The semiconductor device thus formed is
The upper electrode 12 has an upper surface area larger than the upper surface of the metal post 9. FIG. 10 is a perspective view showing portions of a metal post and a solder ball in comparison with a conventional example. As is clear from this figure, in the present invention, the contact area S 'between the solder ball 15 and the metal post 9 can be made larger than the contact area S of the conventional example. As described above, by selecting the size of the resist mask for forming the upper electrode 12, the strength against the shear stress can be optimized.

[0023]

According to the present invention, the contact area between the columnar terminal and the solder ball can be increased, the strength against shear stress can be improved, and the reliability at the time of mounting a chip size package can be improved.

Further, according to the present invention, even if the metal post itself becomes thinner due to the miniaturization of the semiconductor device, the metal post itself has an advantage that the contact area can be sufficiently ensured because the upper electrode is provided with a large upper surface area. is there.

[Brief description of the drawings]

FIG. 1 is a first sectional view showing a semiconductor device and a method for manufacturing the same according to an embodiment of the present invention.

FIG. 2 is an eighth cross-sectional view illustrating a semiconductor device and a method for manufacturing the same according to an embodiment of the present invention.

FIG. 3 is a third sectional view showing the semiconductor device and the method for manufacturing the same according to the embodiment of the present invention;

FIG. 4 is a fourth sectional view showing the semiconductor device and the method for manufacturing the same according to the embodiment of the present invention;

FIG. 5 is a fifth sectional view showing the semiconductor device according to the embodiment of the present invention and the method for manufacturing the same.

FIG. 6 is a sixth sectional view showing the semiconductor device and the method for manufacturing the same according to the embodiment of the present invention;

FIG. 7 is a seventh sectional view showing the semiconductor device and the method for manufacturing the same according to the embodiment of the present invention;

FIG. 8 is an eighth sectional view showing the semiconductor device and the method for manufacturing the same according to the embodiment of the present invention;

FIG. 9 is a ninth cross-sectional view showing the semiconductor device and the method for manufacturing the same according to the embodiment of the present invention.

FIG. 10 is a perspective view illustrating a structure of a semiconductor device according to an embodiment of the present invention.

FIG. 11 is a sectional view showing a chip size package according to a conventional example.

FIG. 12 is a cross-sectional view illustrating a mounted chip size package.

Claims (3)

[Claims] A metal electrode pad formed on a semiconductor substrate, a wiring layer connected to the metal electrode pad and extending on the surface of the semiconductor substrate, and an insulating layer covering the surface of the semiconductor substrate including the wiring layer An opening formed in the insulating layer, a columnar terminal formed in the opening and connected to the wiring layer, and an upper electrode provided on an upper surface of the columnar terminal;
And a solder ball mounted on the upper electrode, wherein the area of the upper surface of the upper electrode is larger than the area of the upper surface of the columnar terminal. A step of forming a metal electrode pad of an LSI on a semiconductor substrate; a step of forming a first insulating layer covering the metal electrode pad; a step of exposing the metal electrode pad; Forming a first plating electrode layer on the entire surface of the substrate, forming a first photoresist pattern on the first plating electrode, and forming a wiring layer connected to the metal electrode pad by electrolytic plating. Forming, removing the first photoresist pattern, forming a second photoresist pattern on the wiring layer and forming columnar terminals by electrolytic plating, and forming a second plating electrode layer on the entire surface. Forming a third photoresist pattern on the second plating electrode layer, and having an upper surface area larger than the upper surface area of the columnar terminal by electrolytic plating. Forming an upper electrode, removing the second and third photoresist patterns and the second plating electrode layer, removing an unnecessary portion of the first plating electrode, Mounting a solder ball on the upper surface of the upper electrode. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising a step of dividing the chip into chips along scribe lines of an LSI after mounting the solder balls.