JP3449362B2 - Digital image signal transmission equipment - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital image signal transmission apparatus using, for example, DCT as high efficiency coding.

[0002]

2. Description of the Related Art A digital VTR for recording a digital video signal on a magnetic tape by a rotary head is known. Since the amount of information in a digital video signal is large,
High-efficiency coding for compressing the amount of transmitted data is often adopted. Among various high efficiency coding, DC
Practical application of T (Discrete Cosine Transform) is progressing.

In the DCT, one frame image is converted into, for example, (8
X8) is converted into a block structure, and this block is subjected to cosine transform processing which is a kind of orthogonal transform. As a result, (8 × 8) coefficient data is generated. Such coefficient data is transmitted after being subjected to variable-length coding processing such as run-length coding and Huffman coding. At the time of transmission, in order to facilitate data processing on the reproducing side, a code signal, which is an encoded output, is inserted into the data area of a sync block of a certain length, and a sync signal, I
The sync block to which the D signal is added is framed.

A digital VTR using a magnetic tape,
In a disc recording device or the like using a disc-shaped recording medium, it is usual that one field or one frame of video data is recorded on a plurality of tracks. However, when a variable length output is formed as in the DCT described above, the amount of data in these predetermined periods fluctuates. Therefore, a buffering process is required to keep the amount of data in the predetermined period below the target value.

As an example, one field or a predetermined period shorter than one frame (called a buffering unit)
A buffering process has been proposed in which the data amount is controlled so that the data amount is equal to or less than a target value even in one field or one frame period as a whole. The buffering process is a process of requantizing the coefficient data of the alternating current generated in the DCT with an appropriate quantization step to suppress the amount of transmission data to be equal to or less than the target value. In the transmission data, a quantization step or a quantization number code indicating the quantization step is inserted together with the encoded data. As an example, the data amount of 5 macroblocks (buffering unit) is controlled so as to fit in the data area of 5 sync blocks.

[0006]

The five sync blocks SB1 to SB5 are not affected by the error in the same way. Further, in order to prevent the concentration of errors and the conspicuous deterioration of image quality, for example, in one frame, one or a plurality of macroblocks as a unit, the spatial position is made different from the original one, that is, Shuffling is done. When doing shuffling, we did not do shuffling considering the difference affected by the error.

Therefore, an object of the present invention is to arrange a macroblock in the central portion of the screen at a position where the influence of an error in the buffering unit is small when performing buffering in which the amount of data in a predetermined period is constant. The object of the present invention is to provide a digital image signal transmission device in which the influence of errors is reduced.

[0008]

According to a first aspect of the present invention, there is provided a digital image signal transmission apparatus, wherein a digital image signal is encoded by orthogonal transformation and variable length coding, and the encoded output is transmitted. A shuffling means for collecting a plurality of macroblocks composed of transform blocks from discrete positions in an image, and a unit of a plurality of macroblocks from the shuffling means controls the data amount of encoded output to be a predetermined value or less. Buffering means for allocating the encoded output from the buffering means to a plurality of sync blocks of a constant length, and a plurality of shuffled macroblocks in the central portion of the screen. This is a digital image signal transmission device characterized in that an object is arranged at the head of a plurality of sync blocks.

When arranging a plurality of shuffled macroblocks in a plurality of sync blocks, arranging the macroblock at the center of the screen in the leading sync block which is minimally affected by the error of other sync blocks. Can reduce the influence of errors.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. Figure 1 shows a digital VTR
2 shows a configuration of a video data processing circuit provided on the recording side. In FIG. 1, digitized video data is supplied to an input terminal indicated by 1. This video data is supplied to the blocking circuit 2. Blocking circuit 2
Then, the video data in the raster scan order is converted into the data of the structure of the (8 × 8) DCT block as illustrated in FIG. 2A.

The output of the blocking circuit 2 is supplied to the shuffling circuit 3. In the shuffling circuit 3, in order to prevent the concentration of errors and the conspicuous deterioration of image quality, the spatial position is made different from the original one in units of one or a plurality of macroblocks in one frame, for example. Processing, that is, shuffling is performed. In this example,
The shuffling unit and the buffering unit are made equal. The output of the shuffling circuit 3 is supplied to the DCT (cosine transform) circuit 4. From the DCT circuit 4, FIG.
As shown in, the coefficient data of the DC component DC and the AC components AC1 to AC63 are generated.

A macroblock is a collection of a plurality of (8 × 8) coefficient data per DCT block. For example, the component type (Y: U: V = 4:
In the case of 1: 1) video data, a total of 6 blocks of 4 Y blocks, 1 U block and 1 V block at the same position in one frame constitute one macro block. In an example of a 525/60 system such as the NTSC system, when the sampling frequency is 4 fsc (fsc: color subcarrier frequency), one frame image is (910 samples × 525 lines), and effective data in that is (720 samples × 480 lines). In the case of the component method described above, the total number of blocks in one frame is (720 × 6/4) × 480 ÷ (8
× 8) = 8100. Therefore, 8100
÷ 6 = 1350 is the number of macroblocks in one frame.

FIG. 3 shows a (30 × 45) two-dimensional array of macroblocks in one frame. Each macroblock is specified by MB [i, j]. (I = 0, 1, 2,
... 29, j = 0, 1, 2, ... 44). P
In an example of a 625/50 system such as the AL system,
It becomes a (36 × 45) two-dimensional array. Therefore, (i =
0,1,2, ... 35, j = 0,1,2, ... 4
4). The shuffling circuit 3 performs shuffling in units of macro blocks within one frame.

FIG. 4 shows an example of this shuffling.
The two-dimensional array is equally divided in the horizontal direction at intervals of 9 macroblocks to form three sub-areas. One buffering unit BU [m, n] is composed of 5 macroblocks collected from each subarea according to the following rules.
Is formed. FIG. 4 shows the five macroblocks that make up BU [0,0] in a 525/60 system.

[0015]   525/60 system (m = 0 to 29, n = 0 to 8)   BU [m, n] = MB [(m) mod.30, n]                   MB [(m + 18) mod.30, n + 9]                   MB [(m + 6) mod.30, n + 18]                   MB [(m + 24) mod.30, n + 27]                   MB [(m + 12) mod.30, n + 36]

[0016]   625/50 system (m = 0 to 35, n = 0 to 8)   BU [m, n] = MB [(m) mod.36, n]                   MB [(m + 21) mod.36, n + 9]                   MB [(m + 6) mod.36, n + 18]                   MB [(m + 27) mod.36, n + 27]                   MB [(m + 12) mod.36, n + 36]

The DC component DC of the (8 × 8) coefficient data generated in the DCT circuit 4 is supplied to the packing circuit 10, and 63 AC components AC1 to AC63 of the DC component are quantized via the delay circuit 5. Is supplied to the digitization circuit 6. As shown in FIG. 2B, the AC component coefficient data is transmitted in the order of zigzag scanning from the AC component having a lower order to the AC component having a higher order. Further, the coefficient data for this alternating current is also supplied to the estimator 7 and the activity detection circuit 8. The delay circuit 5 has a delay amount corresponding to the time required for the estimator 7 to determine an appropriate quantization number QNO.
The quantization number QNO from the estimator 7 is the quantization circuit 6,
It is supplied to the packing circuit 10.

In the quantizing circuit 6, the AC components AC1 to AC63 in the coefficient data are requantized. That is, the coefficient data for the alternating current is divided by an appropriate quantization step, and the quotient is converted into an integer. This quantization step is determined by the quantization number QNO from the estimator 7. In the case of a digital VTR, since processing such as editing is performed in units of one field or one frame, it is necessary that the amount of generated data in one field or one frame be equal to or less than the target value. The amount of data generated by DCT and variable-length coding varies depending on the pattern to be coded. Therefore, a buffering process for reducing the amount of generated data in a buffering unit shorter than one field or one frame period to a target value or less. Is done. The reason for shortening the buffering unit is to simplify the buffering circuit, such as reducing the memory capacity for buffering. In this example, 5 macroblocks are used as a buffering unit.

Further, the activity detection circuit 8 checks the amount of AC component for each DCT block, as described later,
A 2-bit activity code AT indicating the activity of the DCT block is generated. Activity means the fineness of the design. When the pattern is fine, the fact that deterioration of the image due to it is not noticeable even if rough quantization is used is used. The activity code AT is supplied to the estimator 7 and the packing circuit 10.

The output of the quantization circuit 6 is the variable length coding circuit 9
And run-length coding, Huffman coding, etc. are performed. For example, two-dimensional Huffman coding for generating a variable length code (coding output) by giving a zero run, which is the number of consecutive "0" s of the coefficient data of the code, and the value of the coefficient data to the Huffman table stored in the ROM. Is adopted.
The code signal from the variable length coding circuit 9 is supplied to the packing circuit 10. The packing circuit 10 converts the code signal into byte-width data. The output of the packing circuit 10 is supplied to the framing circuit 11. The framing circuit 10 forms data in which a code signal and an activity code AT are arranged according to the rule described later.

In the framing circuit 11, for the output of the packing circuit 10, a synchronization signal and a quantization number QN are further added.
O, ID signal, and auxiliary code AUX are added. And
From the framing circuit 11, data having a sync block structure appears. The output of the framing circuit 11 is supplied to the parity generation circuit 12, and the error correction code is encoded.

A product code is used as the error correction code, and the Reed-Solomon code is encoded with respect to the data in the horizontal and vertical directions. The error correction code in the horizontal direction is called an inner code, and the error correction code in the vertical direction is called an outer code. The inner code is applied to the data included in the data area of one sync block, and the horizontal parity PT is generated. There may be a sync block containing only vertical parity. During variable speed reproduction, the data cut out as a sync block is treated as valid, and error correction using the inner code is performed.

The output of the parity generation circuit 12 is the output terminal 1
Taken out in 3. Although not shown, this recorded data is
It is supplied to two rotary heads via a channel coding circuit and a recording amplifier and recorded on a magnetic tape.

The estimator 7 can make the generated data amount of the buffering unit (5 macroblocks) equal to or less than the target value, and determines the quantization step of a value as small as possible. Further, by referring to the activity code AT, an appropriate quantization step is determined for each DCT block. FIG. 5 shows an example of the estimator 7. Coefficient data from the DCT circuit 4 is supplied to the n quantizing circuits 201, 202, ..., 20n. These quantization circuits 201 to 20n have different quantization steps Δ1, Δ2, ..., Δ from the quantization step generation circuit 21.
n are respectively supplied. Activity code AT
Are supplied to the quantization step generation circuit 21.

The integer-divided outputs divided by the respective quantization steps are supplied to the variable-length coding circuits 221 to 22n, respectively. These variable length coding circuits 221 to 22n
Is a variable length coding circuit 9 that actually generates a variable length code.
Unlike, the variable length coded output generates code length data. Data of this code length is accumulated in the accumulation circuits 231 to 23n.
Is supplied to each. The accumulation circuits 231 to 23n have
A reset pulse is supplied from the terminal 24. Accumulation circuit 2
31 to 23n are for obtaining the amount of code signal generated in the buffering unit. In this example, a reset pulse is generated every 5 macroblocks. Accumulation circuit 231-2
The cumulative calculation force of 3n is supplied to the determination circuit 25.

The target value Am from the terminal 26 is supplied to the determination circuit 25. The outputs of the accumulator circuits 231 to 23n are compared with the target value Am, and the quantization step closest to the target value Am is determined within the range not exceeding the target value Am. Quantization number QNO is determined by this determination output, and is output to output terminal 28. This quantization number QNO is supplied to the quantization circuit 6. The quantization circuit 6 is provided with a ROM that converts a quantization number into a quantization step.

The estimator 7 is not limited to the configuration shown in FIG. 5, but various types of configurations such as a method of sequentially quantizing at different quantizing steps can be adopted. Further, not only the common quantization step is applied to the coefficient data of all orders of alternating current, but the quantization step corresponding to the order may be used. That is, the coefficient data for the alternating current is divided into a plurality of groups according to the order, and the quantization step is prepared for each of the plurality of groups. Then, when different quantization steps are used, a plurality of sets of quantization steps for a plurality of groups are prepared, quantization is performed by the plurality of sets of quantization steps, and the optimum quantization step is determined by referring to the result. It is determined.

FIG. 6 shows an example of the activity detection circuit 8. The AC terminal coefficient data AC is input to the input terminal 31.
1 to AC 63 are sequentially supplied and converted into an absolute value by the absolute value conversion circuit 32. The output of the absolute value conversion circuit 32 is the comparison circuit 3
3 and is compared with a threshold Th from the terminal 34, for example 5. The comparison circuit 33 generates an output of "1" (high level) when the absolute value of the coefficient data of the alternating current is larger than the threshold value Th. The comparison output of the comparison circuit 33 is supplied to the enable terminal of the counter 35.

A clock CK is supplied to the counter 35, and a timing signal DCSL is supplied to its clear terminal. By the timing DCSL, the counter 35 is cleared at the timing of the DC component DC of one DCT block. The counter 35 increments its content in response to the AC coefficient data whose absolute value is larger than the threshold value. Therefore, the 6 bits of the output of the counter 35 are (0
.About.63). The count value of the counter 35 is supplied to the decoder 36. The decoder 36 generates a 2-bit activity code AT at the output terminal 37.

As an example, the decoder 36 classifies so as to generate the following activity code AT. Count value is (0-10): (00) Count value is (11-18): (01) Count value is (19-25): (10) Count value is (26-63): (11)

The count value of the counter 35 represents a measure of the amount of AC component of the DCT block. Therefore, in order to control the amount of generated data, AT = 01, for example, is used as a reference.
When AT = 00 and the amount of alternating current is small, it is necessary to reduce the quantization step, and when AT = 10 and the amount of alternating current is large, it is necessary to increase the quantization step. When there are more minutes, the quantization step needs to be larger. Estimator 7 mentioned above
The quantization step generation circuit 21 receives the activity code AT and adjusts the quantization step. Thus, to adjust the quantization step,
Activity is used.

In this example, as shown in FIG. 7, buffering is performed so that code signals of 5 macro blocks are arranged in the data area of 5 sync blocks. In other words, the sync blocks SB1 to SB each having the data amount of the buffering unit (5 macroblocks) are five.
It is controlled so as to fit within the 5 data area. Also,
Within each sync block, code signals of approximately integer number, for example, approximately one macro block are arranged. The specific length of the data area of each sync block is specified in consideration of this point.

Further, two tracks are simultaneously formed on the magnetic tape by two rotary heads arranged close to each other. In the case of the NTSC system, one frame of data is recorded on ten tracks T0 to T9. Are recorded separately. The PCM audio signal is error-correction coded and recorded together with video data, or recorded in an audio data recording section provided in one track.

Since one frame consists of 1350 macroblocks, 135 macroblocks are recorded per track. Since the buffering unit is 5 macroblocks, 27 buffering units are recorded in one track. As described above, since the data amount of each video group is controlled to be equal to or slightly smaller than the target value Am, data of 135 macroblocks can be recorded on each track of a fixed length.

FIG. 8 shows the data array of one sync block in this embodiment. The length of one sync block is 90 bytes, for example. The block synchronization signal SYNC (2 bytes) is located at the beginning of the sync block, and the ID signal is located after that. This ID signal consists of a 2-byte ID signal (ID0, ID1) and a parity IDP (1 byte) for the ID signal. 77 bytes of the remaining 85 bytes are the data area, and the last 8 bytes
The byte is the parity of the inner code of the product code. At the beginning of the data area, a 1-byte quantization number QNO and an auxiliary code AUX for identifying the quantization step are located. The subsequent 75 bytes are data (variable length code or outer coding parity).

In one sync block, the code signal and each DC for one macro block (YYYY, U, V) are included.
The activity code AT and the motion flag M for the T block are inserted. The motion flag M is DCT
This is a 1-bit flag indicating the presence or absence of motion detected for each block. In FIG. 1, for simplicity, the motion detection circuit is
Omitted. When orthogonally transforming the DCT block,
The motion flag M is used to perform the intra-frame DCT when there is no motion and to perform the intra-field DCT when there is motion.

The 75-byte area is divided into four areas each having a length of d (for example, 18 bytes) and a fractional leading area. For each d, the DC component (9 bits) generated in the four DCT blocks of one macroblock is arranged, after which the motion flag M and the activity code AT are arranged. Each area having a length of d is divided into an area of a (for example, 12 bytes) and an area of d / 2 (6 bytes). As a result, eight areas are formed.

The first area is a fixed AC-H area. The area of the next length a including the DC component is AC of Y-
L-area, a / 2 length area is fixed AC-H
The area. Next, in the area of length d, AC of Y
-L area and area for DC (for example, U), motion flag M, activity code AT, and AC-L. Furthermore, the area of the next d is Y
AC-L area and fixed AC-H area, and the last d-length area is Y-AC-L area, C (for example, V) DC component, motion flag M, activity code AT, AC -It is an area for L. The AC-H components protruding from each AC-L area are packed in order from the first AC-H area. If an empty area, that is, a variable AC area, exists in the AC-L area, the protruding AC-H component is also packed therein.

The ID signal includes a frame ID, a format identification bit, 2 bits indicating the type of recording data, a sync block address, and a parity byte IDP. The frame ID is inverted for each frame. The identification bit identifies the format for the digital VTR of this embodiment and other formats such as the format of the data storage device. When this is "1", the digital VT
It means a format for R, and when it is "0", it means another format. The recording data identification bit is
Indicates the type of recorded data (video, audio, etc.). Further, the sync block address is an address that includes one frame of data and is assigned a serial number to all sync blocks that are divided and recorded in a plurality of tracks.

Further, the auxiliary code AU in the data area
X is also a kind of ID signal and has information such as the broadcast format of the video signal and the audio mode. The reason why the quantization number QNO and the auxiliary code AUX are recorded in the data area is that the error correction code relating to the data in the data area has a higher correction capability than the error correction code of the ID signal.

FIG. 8B shows another example of the sync block having the regularity of the present invention. That is, eight areas, that is, the code signal areas of the six DCT blocks forming one macroblock and the two AC-H areas are provided at intervals of d '. Therefore, in this example, the data area of one sync block is 8d '+ 2 bytes. As in the example of FIG. 6A, one of the AC-H areas is located at the head, and the DC component of each DCT block is regularly arranged. In general, the amount of code signal generated in the DCT block of Y is smaller than that generated in C of C, so the area of Y is twice as large as the area of C in the configuration of FIG. 8A.

FIG. 9 shows a more specific data structure according to the present invention. In FIG. 9, 5 sync blocks S in which 5 macroblocks forming one buffering unit are arranged.
B1 to SB5 are shown stacked vertically. The arrangement of FIG. 9 is
Similar to FIG. 8A. That is, in relation to FIG. 8A, (d = 18, a = 12). However,
Between that shown in FIG. 8A, the AC-H area is arranged before the last parity, and the recording area of the compression-coded digital audio signal is I.
The difference is that it is provided after the D area.

The data structure of FIGS. 8A, 8B and 9 described above is improved in the following points. First, since a code signal of approximately one macroblock exists in one sync block, the data reproduced in units of one sync block can be effectively used as in the variable speed reproduction. Second, A
A fixed area is provided as the C-H area.
Since these are dispersed, it is possible to reduce the ratio of the AC-H component causing an error due to a propagation error. Third, in the configuration of FIGS. 8A and 8B, the fixed AC-H area is provided before the first DC component. Therefore, the AC-H component protruding from the sync block is packed toward the front, and the possibility that the AC-H component is spread over other sync blocks can be reduced. Fourthly, since the AC-H component protruding from the sync block is packed from the head of the fixed AC-H area, the AC-H component has address information. As a result, even if there is an error in the previous sync block, the next sync block can be refreshed.

Further, as a method of arranging the code signal of one macro block in one sync block, the method shown in FIG. 8C is also possible. This has the above-mentioned first advantage, but compared to FIG. 8A, the AC-H area is not divided into two, and the AC-H area is located at the end together. As a result, there is a problem that the above-mentioned second, third and fourth advantages cannot be obtained.

An example of the framing circuit 11 for generating the data structure of FIG. 8A is shown in FIG. In FIG. 10, the packing circuit 10 in the preceding stage of the framing circuit 11 is also shown. The packing circuit 10 includes a variable length coding circuit 9
From the AC component, the length information of the code signal from the variable length code encoding circuit 41, the coefficient data of the DC component, and the activity code AT. The code signal converted into the byte width is supplied from the packing circuit 10 to the input selector 44. 42 is
It is an EOB detection circuit inserted at each block of the AC component code signal. The output signal of the detection circuit 42 is supplied to the read / write controller 43 of the RAM.

The input selector 44 has five output terminals a,
b, c, d, e, for which RAM, FIF
O and controllers 45a to 45e are connected. R
Each of the AM, the FIFO, and the controllers 45a to 45e forms data of five sync blocks corresponding to one buffering unit. These RAM, FIF
O and the controllers 45a to 45e form data having the structure of the data area shown in FIG. 8A, and the respective data are input terminals a, b, c, d, e of the output selector 46.
Is supplied to each.

The packing circuit 10, the input selector 44,
Control signals, address signals, or timing signals for the RAM, the FIFO, and the controllers 45a to 45e are given from the RAM read / write controller 43. The output selector 46 is controlled by a control signal from the framing controller 47. The output of the output selector 46 is supplied to the additional circuit 48, and the controller 4
Under the control of 7, the synchronization signal, the ID signal, the quantization number QN
O, the auxiliary code AUX is added at a predetermined position. At the output of the additional circuit 48, the data having the configuration shown in FIG. 8A is obtained.

RAM, FIFO, controller 45a ...
45e have the same configuration as each other, and in FIG.
The configurations of the AM, FIFO, and controller 45a are shown. This is the selector 51, the RAM 52, the FIFO 5
3, data combination circuit 54, barrel shifter 55, and F
Includes IFO, barrel shifter controller 56.

When the selector 51 fills the AC-L area corresponding to the code signal generated in each DCT block into the corresponding AC-L area, the code signal R is output through the output terminal f.
A code signal which is written in the AM 52 and does not fit therein is supplied to the FIFO 53 through the output terminal g. RAM5
2 is a capacity for storing 75 bytes of data and a flag W
It has a capacity for F and RB. The flag WF is a write flag indicating whether each byte has been written or has not been written, and is (1 bit × 75) data. If (WF = 0), it indicates that no writing has been performed,
If (WF = 1), it means that the writing has been completed. Flag R
B is the number of unwritten bits (1 to
It is a remaining bit flag indicating 8), and is (3 bits × 7
It is the data of 5).

The capacity of the FIFO 53 is related to the size of the AC-L area, etc.
It is selected to have a size capable of storing a code signal protruding from the area, for example, 24 bytes. This FIFO 5
A flag EF is stored in 3 separately from the one for data storage.
The flag EF indicates whether there is write data in the FIFO 53 or is empty, and is a 1-bit flag. If (EF = 0), it indicates that there is write data, and if (EF = 1), it indicates that the FIFO is empty.

The controller 56 is provided with the above-mentioned flag W.
F, RB, EF are supplied, and the controller 56 performs control for packing the code signal stored in the FIFO 53 into the empty area of the RAM 52. Specifically, the controller 56 controls the bit shifting operation of the barrel shifter 55, and the output of the barrel shifter 55 is combined with the read data of the RAM 52 in the data combining circuit 54. The output data of the data synthesizing circuit 54 is written in the same address of the RAM 52. That is, the RAM 52 performs read-after-write operation. Further, the read data of the RAM 52 is supplied to the input terminal a of the output selector 46.

RAM, FIFO, controller 45b-
45e is the above-mentioned RAM, FIFO, controller 45
It has the same configuration as a. The framing process includes first, second and third steps. The first step is to sequentially pack the code signal into the designated AC-L area. The second step is a process of packing the AC-H component protruding from each sync block in the first step into an empty area (fixed AC-H area and variable AC-H area) in the sync block.

The processing of these first and second steps is processing in which the sync block does not extend over other sync blocks. However, even after the second step, when the protruding AC-H component exists, it needs to be packed in the empty area existing in another sync block. This process is the third step. RAM, FIF to perform the third step
A bus 57 for connecting the FIFOs between the O and the controllers 45a to 45e is provided, and the transfer of data via the bus 57 is controlled by the controller 56.

In order to understand the framing circuit 11 described above, an example of its operation will be described with reference to FIGS. 11 and 12. 11 and 12 show sync block SYN.
Controllers 45a to 45 corresponding to C1 to SYNC5
e RAM1 to RAM5 and FIFO1 to FIFO5
Shows the state of. FIG. 11 shows the state when the first step is completed. That is, the packing circuit 1
It shows a state in which a code signal for an alternating current from 0 is packed in a corresponding AC-L area. RAM1 to R of FIG.
The shaded area of AM5 is an area in which data has not been written, and the FIFO1 to FIFO5 store code signals that extend from each AC-L area.

For example, FIG. 13A showing the enlarged AC-H area and the Y-AC-L area of the RAM 4 in an enlarged manner.
In FIG. 5, as indicated by the diagonal lines, the leading AC-H area and the 5th bit of the 10th byte, the 11th byte and the 12th byte of the 12 bytes of the AC-L area of Y are empty areas. Therefore, in the 1st to 9th bytes, (W
F = 1, RB = 0), and in the 10th byte, (WF
= 1 and RB = 5), and (WF = 0, RB = 8) in the 11th and 12th bytes.

In the next second step, the protruding code signal in the FIFO is packed in the empty area of the RAM of the sync block from the head AC-H area. After the processing of this second step is performed, RAM1 to RA
The contents of M5 and FIFO1 to FIFO5 are illustrated in FIG. In the case of SYNC1 and SYNC3, the code signals of FIFO1 and FIFO3 cannot be packed in the empty area, and the code signals remain in FIFO1 and FIFO3, which is (EF = 0).

On the other hand, SYNC2, SYNC4 and SY
In case of NC5, FIFO2, FIFO4 and FI
The code signal of FO5 can be packed in the empty area, and no code signal remains in FIFO2, FIFO4 and FIFO5 (EF = 1). Furthermore, regarding these SYNC2, SYNC4, and SYNC5, empty areas still remain in the RAM2, RAM4, and RAM5 as indicated by the diagonal lines. As shown in FIG. 13B, after the processing of the second step, the first AC-
5 of the 10th byte of H-area and Y-AC-L area
Bits are filled with AC-H components from FIFO4.

In the third step, FIFO1 and FI
The AC-H component remaining in FO3 is packed in the empty area of another SYNC. For example, the AC-H component remaining in the FIFO 1 is packed in the variable AC-H area of the RAM 2 indicated by the diagonal line. For example, as shown in FIG. 13C, R
6 shows a state in which 6 bits of the 11th byte of the Y variable AC-H area of AM4 are filled with variable AC-H components from another FIFO. When the third step is completed, the framing process for the 5 sync blocks is completed.

Also in the case of the data structure shown in FIG. 9, the data are packed in order by the first, second and third steps. This process need not be the same as described above. The modified process will be described. In the first step, AC-
Fill in the data for AC so that the L area is filled. In this case, if the remaining area in the AC-L area is less than 16 bits, the filling process is stopped. 16 bits is the maximum bit length of the variable length code in this example, and it is possible to avoid having one variable length code separately in two areas.

In the second step, the vacant area and the AC-H area in the AC-L area are filled with the data overflowed in the first step. In this case, in FIG. 14, each area is filled in the numbered order. In FIG. 14, the empty area after the first step is indicated by diagonal lines. And the third step is the second
The data overflowed in the step is sequentially packed in the remaining empty area.

In the above embodiment, after shuffling, one macroblock constitutes one buffering unit, and the data of this one buffering unit is arranged in five sync blocks. Here, the five sync blocks SB1 to SB5 are not affected by the error in the same way. It is also preferable to arrange the 5 macroblocks within the 5 sync blocks in an order taking this point into consideration.

When the data of 5 macroblocks is packed into the 5 sync blocks by the above-mentioned first, second and third steps, the data overflowed in the first and second steps remains in the third step. It is packed in the empty area. Here, consider two cases. In the first case, the data of one macroblock is 1
This is a case where the length of the data area of the sync block is not exceeded, and a second case is a case where the data of one macro block exceeds the data area of one sync block.

In the first case, an error generated in another sync block does not affect the sync block at all. In the second case, since the sync block is arranged in another sync block by the above-described third step, an error generated in another sync block affects the sync block. The data in the sync block SB1 is sequentially packed into the empty areas in the other sync blocks. If there is an error in the data arranged before this packed data, the delimiter of the variable length code will be unknown and the data cannot be decoded. Therefore, in the second case, among the sync blocks SB1 to SB5, the influence of other sync blocks spreads as the sync block becomes a relatively later sync block.

As shown in FIG. 15, 5 macroblocks M extracted by the shuffling process from the screen of one frame.
B0 to MB4 are arranged in 5 sync blocks. This Figure 1
5 is similar to FIG. 4 and represents the numbering of 5 macroblocks. This number represents the correspondence with the divided area of the screen. As shown in FIG. 16, 525/60
In the system, reference symbols are attached to the data of DCT blocks included in each macroblock. 625/5
Reference numerals for the data of the DCT block of each macroblock in the 0 system are as shown in FIG.

As can be seen in FIG. 15, the macroblocks MB0 and MB4, which are labeled with reference numerals 0 and 4, respectively.
Is included in the areas on both sides of one screen, the macro block MB2 with the reference numeral 2 is included in the central portion of the screen, and the macro blocks MB1 and MB1 with the reference numbers 1 and 3 are included. MB3 is included in the part between the center and the edge. In one screen, the main part of the image usually occurs in the central part, and much attention is paid to the central part of the screen by the viewer of the screen. Therefore, when an error occurs, it is the image in the central portion of the screen that is most noticeable.

As described above, in the sync block in which 5 macroblocks are arranged, the influence of the error of other sync blocks is smaller in the sync block at the head. Therefore, as shown in FIG. 18, for the sync block SB1 that is least affected by the error, the macro block M at the center of the screen
Allocate the data of B2. Hereinafter, sync block SB2,
Data of macroblocks MB1, MB3, MB0, and MB4 are arranged for SB3, SB4, and SB5, respectively. Due to the relationship between the macro block and the sync block, the data in the central portion of the screen can be stochastically least affected by the error.

The present invention can be applied not only to the digital VTR but also to a disk recording / reproducing apparatus, a case of transmitting a digital image signal through a communication path, and the like.

[0068]

According to the present invention, since code signals of an approximately integer number of macro blocks exist in one sync block, data reproduced in units of one sync block is effective as in variable speed reproduction. Available for Further, according to the present invention, since the macro block in the central portion of the screen is arranged in the head sync block having the smallest influence of the error of other sync blocks among the plurality of sync blocks, the influence of the error is noticeable in the restored image. It can be none.

[Brief description of drawings]

FIG. 1 is a block diagram of a recording data processing circuit of a digital VTR to which the present invention is applied.

FIG. 2 is a schematic diagram used to describe a DCT.

FIG. 3 is a schematic diagram used to describe a macroblock.

FIG. 4 is a schematic diagram used to explain shuffling.

FIG. 5 is a block diagram of an example of an estimator.

FIG. 6 is a block diagram of an example of an activity detection circuit.

FIG. 7 is a schematic diagram showing a buffering unit.

FIG. 8 is a schematic diagram illustrating an example of a sync block.

FIG. 9 is a schematic diagram showing another example of a sync block.

FIG. 10 is a block diagram of an example of a framing circuit.

FIG. 11 is a schematic diagram for explaining the operation of the framing circuit.

FIG. 12 is a schematic diagram for explaining the operation of the framing circuit.

FIG. 13 is a schematic diagram for explaining the operation of the framing circuit.

FIG. 14 is a schematic diagram for explaining the operation of the framing circuit.

FIG. 15 is a schematic diagram for explaining the shuffling.

FIG. 16 is a schematic diagram for explaining a DCT block forming a macro block.

FIG. 17 is a schematic diagram for explaining a DCT block forming a macro block.

FIG. 18 is a schematic diagram showing a relationship of arrangement of macroblocks with respect to a plurality of sync blocks.

[Explanation of symbols]

4 ... DCT circuit, 6 ... Quantization circuit, 7 ... Estimator, 11 ... Framer circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-52-143712 (JP, A) JP-A-62-248393 (JP, A) JP-A-2-220270 (JP, A) JP-A-4- 56577 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N ^7/ 00-7/68 H04N 5/38-5/46

Claims (3)

(57) [Claims] 1. A digital image signal transmission apparatus for encoding a digital image signal by orthogonal transformation and variable-length coding and transmitting the encoded output, wherein a macroblock composed of a plurality of orthogonal transformation blocks is included in an image. Shuffling means for collecting a plurality of data from discrete positions; buffering means for controlling the data amount of the encoded output below a predetermined value in units of a plurality of macroblocks from the shuffling means; Means for arranging the coded output from the means into a plurality of sync blocks of a certain length, and among the plurality of shuffled macroblocks, the one in the center of the screen is the plurality of sync blocks. A device for transmitting a digital image signal, which is arranged at the beginning of a block. 2. The digital image signal transmission device according to claim 1, wherein the shuffling means collects one macroblock from each of the five divided regions of the image in the horizontal direction. 3. The digital image signal transmitting apparatus according to claim 2, wherein the number of the plurality of sync blocks having a fixed length is five.