JP3458398B2 - Digital image signal transmission equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital image signal transmission apparatus using, for example, DCT as high-efficiency coding, and more particularly to control of the data amount of transmission data. 2. Description of the Related Art A digital VTR for recording a digital video signal on a magnetic tape by, for example, a rotary head is known. Because of the large amount of digital video signal information,
High-efficiency coding for compressing the transmission data amount is often adopted. Among various high efficiency codings, DC
The practical use of T (Discrete Cosine Transform) is in progress. [0003] DCT converts an image of one frame into, for example, (8
.Times.8), and the block is subjected to cosine transform, which is a type of orthogonal transform. As a result, (8 × 8) coefficient data is generated. Such coefficient data is transmitted after being subjected to a variable length coding process such as a run length code and a Huffman code. At the time of transmission, it is common to have a sync block configuration in which a block synchronization signal is added for each data of a fixed length. A digital VTR using a magnetic tape,
In a disk recording device or the like using a disk-shaped recording medium, one field or one frame of video data is usually recorded on one or two or more integer tracks. However, when a variable-length output is formed as in the above-described DCT, the data amount of one frame varies. Therefore, a buffering process for reducing the data amount of one frame to a target value or less is required. As a buffering process, a method of controlling the amount of data generated in one frame period is conceivable. In that case, however, the amount of data to be controlled increases, and the amount of memory increases and the scale of other hardware increases. Increase. [0005] In view of this point, 1
The amount of data in a predetermined period (referred to as a buffering unit) shorter than a frame is controlled, and even in the entire one frame period,
As a result, a buffering process for reducing the data amount to a target value or less is preferable. In this method, data of different buffering units is included in the same sync block, and as a result, there is a problem that the redundancy of transmission data increases. FIG. 8 shows a conventional sync block that has undergone a buffering process. A block synchronization signal SYNC is located at the head of a sync block having a continuous structure of bytes, and thereafter, additional information AIN0 and AIN1 including a quantization number for identifying a quantization step used for buffering are provided. In the data area located after the additional information AIN1, the coefficient data (DC
Parity PT of the error correction code added for each data of the sync block is located. In the example of FIG. 8, both the video group 0 and the video group 1 are included in the data area.
A video group is the same buffering unit DCT
Code, that is, a group of DCT codes quantized in the same quantization step. Additional information AIN0
Is related to video group 0, and additional information AIN1 is related to video group 1.
As described above, since the DCT codes of different buffering units are included in the same sync block, the amount of additional information increases and the redundancy increases. When the amount of data subjected to the buffering process is shorter than the data area length of one sync block, the number of video groups included in one sync block is not constant as shown in FIG. Three pieces of additional information AIN0, AIN1, and AIN2 are required to indicate the quantization numbers of the maximum number (three in the example of FIG. 9) of video groups that can be included in one sync block. Therefore, in the case of a sync block including two or less video groups, useless and meaningless additional information exists. This also increases redundancy. Further, when three video groups are included, as shown in FIG. 10, an empty area a generated in each buffering unit, a part of bits of a variable-length code segment continuing from the immediately preceding sync block. b, some bits c of the break of the variable-length code following the immediately following sync block
And are included. At the time of variable speed reproduction in which the tape speed is made different from that at the time of recording, the track on the tape does not coincide with the scanning locus during reproduction, and the reproduced data becomes fragmentary. At the time of this variable speed reproduction, validity / invalidity is determined for each sync block. Therefore, as shown in FIG. 10, including many useless portions in one sync block causes a reduction in the amount of data that can be reproduced. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a digital image signal transmission apparatus having a low degree of redundancy and capable of increasing the number of reproducible data during variable speed reproduction. According to the first aspect of the present invention, frames are continuously formed by encoding that generates a variable-length encoded output .
In a digital image signal transmitting apparatus for compressing an input digital image signal and transmitting a variable-length coded output, n (n is 2 or more) shorter than one frame period
Of the variable-length coded output of the macroblock
Estimate the raw amount of data, the eyes of the generated data amount below the target value
Determine the quantization step that is close to the standard value, and
Buffering circuits for requantization in steps (5, 6)
And N variable-length coded outputs of n macroblocks whose data amount is controlled by the buffering circuits (5, 6)
(N is a positive integer equal to or greater than 1), a circuit (8) arranged in the data area of a sync block, and a device for transmitting data having a sync block configuration.
Signal and additional information are added to the data area.
The quantization step or quantization step.
A separate code signal is applied to each of the sync blocks.
A transmission device for a digital image signal which is inserted as additional information . Each sync block does not include a DCT code of a different video group. Therefore, it is sufficient to insert one quantization number into the sync block. As a result, an increase in redundancy can be prevented. In addition, a useless area in the sync block is reduced, and the number of reproducible data during variable speed reproduction can be increased. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a digital V according to the present invention.
2 shows a configuration of a video data processing circuit provided on the recording side of the TR. Digitized video data is supplied to an input terminal denoted by reference numeral 1. This video data is supplied to the blocking circuit 2. In the blocking circuit 2, the video data in the raster scanning order is, for example, (8 × 8) 2
It is converted to data of a dimensional block structure. The output of the blocking circuit 2 is supplied to a DCT (cosine transform) circuit 3. (8 × 8) coefficient data generated by the DCT circuit 3 (data of one DC component and 63
(Comprising data of the number of ACs) is supplied to the quantization circuit 5 via the delay circuit 4. As an example, 64 coefficient data DT in one block are transmitted in order from an alternating current component having a lower order to a component having a higher order in a zigzag scanning order, with a direct current component at the top. The coefficient data is also supplied to the estimator 6. The delay circuit 4 has a delay amount corresponding to the time required for the estimator 6 to determine an appropriate quantization step. In the quantization circuit 5, the DC component in the coefficient data is not requantized, but the AC component is requantized. That is, the constant data for the AC is divided by an appropriate quantization step, and the quotient is converted to an integer. This quantization step is determined by the quantization number from the estimator 6. In the case of a digital VTR, since processing such as editing is performed in units of frames, the amount of generated data per frame needs to be equal to or less than a target value. Since the amount of data generated by DCT and variable-length coding varies depending on the pattern to be coded, a buffering process is performed to reduce the amount of data generated in a buffering unit shorter than one frame period to a target value or less. . The reason why the buffering unit is shorter than one frame period is to simplify the buffering circuit, for example, by reducing the memory capacity for buffering. In this example, 15 macroblocks are set as a buffering unit. The output of the quantization circuit 5 is a variable length coding circuit 7
, And run-length coding, Huffman coding, and the like are performed. The DCT code from the variable length coding circuit 7 is supplied to the packing circuit 8, and the packing circuit 8 forms a DCT code divided by the data area length of the sync block in byte width. The output of the packing circuit 8 is supplied to a parity generation circuit 9 to form a parity of the error correction code. The output of the parity generation circuit 9 is supplied to the multiplexer 10. The output of the parity generation circuit 11 is supplied to the multiplexer 10. The quantization number QNO from the estimator 6 is supplied to the additional information (AIN) generation circuit 12, and the additional information AIN including the quantization number QNO is generated. This is error-correction-coded by the parity generation circuit 11 and then supplied to the multiplexer 10. The multiplexer 10 is also supplied with a block synchronization signal SYNC. The multiplexer 10 time-division multiplexes the outputs of the parity generation circuits 9 and 11 and the block synchronization signal SYNC, and generates transmission data at an output terminal 13. Although not shown, the transmission data is supplied to two rotating heads via a channel encoding circuit and a recording amplifier, and is recorded on a magnetic tape. The estimator 6 determines the quantization step having a value as small as possible, which can reduce the amount of data generated in the buffering unit to a target value or less. FIG. 2 shows an example of the estimator 6. n quantization circuits 20 ₁ , 20 ₂ ,
.., 20 _n are supplied with coefficient data from the DCT circuit 3. However, DC data is excluded from the buffering target. These quantization circuits 20 ₁
２０20 _n are supplied with different quantization steps Δ1, Δ2,..., Δn from the quantization step generation circuit 21. [0019] is divided by the quantization step, output which is integer are supplied to the variable length coding circuit 22 ₁ through 22 _n. These variable length encoding circuits 22 _{1 to} 22 _1
n is different from the variable length coding circuit 7 for generating an actual variable length code, and generates data of a code length of a variable length coded output. Data for this code length accumulator circuit 23 _1-23
n respectively. The accumulation circuit 23 ₁ ~ 23 _n, a reset pulse from terminal 24 is supplied. Accumulation circuit 23 ₁ ~ 23 _n is intended to determine the amount of DCT code generated by buffering ring units, in this example, 1
A reset pulse is generated every five macro blocks. Accumulation output of the accumulator circuit 23 ₁ ~ 23 _n are supplied to the determination circuit 25. The determination circuit 25 receives a target value A from a terminal 26.
m is supplied. The output of the accumulator circuit 23 ₁ ~ 23 _n and the target value Am is compared, in a range not exceeding the target value Am, most target value Am and close accumulator output, i.e., the optimal accumulator output is determined. By this determination output, the quantization number QNO
Is determined and taken out to the output terminal 27. This quantization number QNO is supplied to the quantization circuit 5. Quantization circuit 5
, Which converts the quantization number QNO into a quantization step
An OM is provided. The estimator 6 is not limited to the configuration shown in FIG. 2, but may employ various configurations such as a method of sequentially performing quantization at different quantization steps. In addition, a common quantization step is not limited to the coefficient data of the AC components of all orders, and a quantization step according to the order may be used. That is, the coefficient data for the AC is divided into a plurality of groups according to the order, and a quantization step is prepared for each of the plurality of groups. When different quantization steps are used, a plurality of sets of quantization steps for a plurality of groups are prepared, quantization is performed using a plurality of sets of quantization steps, and the optimum quantization step is determined by referring to the result. It is determined. FIG. 3 shows one sync block (SB) formed by the multiplexer 10. A block synchronization signal SY is provided at the beginning of a sync block having a byte
NC is located and then a quantization number QN to identify the quantization step used for buffering
In the data area after the additional information AIN, a DCT code whose data amount is controlled by buffering and a parity PT of an error correction code added for each data of the sync block are located. To position. The additional information contains the parity of the error correction code for the additional information, and if necessary, the address of the macroblock, the sync number, and the ID indicating the type of data.
Etc. are inserted. On the playback side, after decoding the variable length code, the quantization number and the corresponding quantization step are multiplied,
The coefficient data is restored. As an error correction code, a product code is used, and Reed-Solomon code is encoded on the data in the horizontal and vertical directions. The horizontal error correction code is called an inner code, and the vertical error correction code is called an outer code. The inner code is performed on data included in the data area of one sync block, and a horizontal parity PT is generated. Some sync blocks may include only vertical parity. At the time of variable speed reproduction, data cut out as a sync block is treated as valid, and error correction using an inner code is performed. In this example, as shown in FIG. 4, buffering is performed so that DCT codes of 15 macroblocks are arranged in the data area (shaded area) of 15 sync blocks SB1 to SB15. In other words, control is performed so that the data amount of the buffering unit (15 macroblocks) falls within the data area of the 15 sync blocks SB1 to SB15. The specific length of the data area of each sync block is defined in consideration of this point. The numerical value of 15 is merely an example. In short, the buffering is performed such that the data of the buffering unit is contained in the data area of the integer number of sync blocks. For example, when the buffering process is performed with a smaller memory capacity, the buffering unit is set to 5 macroblocks, and the data of the five macroblocks MB1 to MB5 is
It is also possible to control so as to fit within the data area of the sync blocks SB1 to SB5. At this time, the macro blocks MB1 to MB5 can be shuffled in the buffering unit and arranged as shown in FIG. The macro blocks are (8) per block.
× 8) is obtained by collecting a plurality of blocks of coefficient data.
For example, (Y: U: V = 4: 1:
In the case of the video data of 1), four Y blocks, one U block, and one V block at the same position in one frame
A total of six blocks including one block constitute one macro block. When the sampling frequency is 4 fsc (fsc: color subcarrier frequency), an image of one frame is (91
0 samples × 525 lines), of which the valid data is (720 samples × 480 lines). In the case of the above component system, the total number of blocks in one frame is (720 × 6/4) × 480 ÷ (8 × 8) =
8100. Therefore, 8100 ÷ 6 = 1
350 is the number of macroblocks in one frame. Further, as shown in FIG. 6, two tracks are simultaneously formed on the magnetic tape by two closely arranged rotating heads, and ten tracks T0 to T0 are formed.
One frame of data is divided and recorded in T9. Note that the PCM audio signal is error-correction-coded,
It is recorded together with video data, or recorded in an audio data recording section provided in one track. Since one frame is composed of 1350 macroblocks, 135 macroblocks are recorded per track. Since the buffering unit is 15 macro blocks, nine buffering units (video group 0 to video group 8) are recorded in one track as shown with respect to track T0. As described above, since the data amount of each video group is controlled to be equal to or slightly smaller than the target value Am, data of 135 macroblocks can be recorded on each track of a fixed length. At the time of variable speed reproduction, for example, when the tape speed is four times the speed at the time of recording, the two rotating heads draw a scanning locus indicated by a broken line in FIG. The data is played. The present invention can be applied not only to a digital VTR but also to a disk recording / reproducing apparatus, a case where a digital image signal is transmitted via a communication path, and the like. According to the present invention, according to the present invention , compared to one frame period,
(N is a positive integer of 2 or more) macro blocks
A buffer is a buffering unit, and buffering is performed so that the buffering unit fits in the data area of N (N is a positive integer equal to or greater than 1) sync blocks. Therefore, the additional information on each sync block only needs to include the information of the quantization step of one video group, and it is possible to prevent the additional information from increasing the redundancy. Needless to say, it is not necessary to associate the additional information with the video group at the time of reproduction, and the processing at the time of reproducing the additional information can be simplified. In addition, as shown in FIG. 7, in the present invention, a part of the bits b of the variable length code following the immediately preceding sync block and a part of the bits of the variable length code following the immediately following sync block c. Included,
The free area resulting from the buffering occurs in only one sync block in each buffering unit, and therefore, the amount of data that can be reproduced during variable speed reproduction can be increased. Furthermore, in the variable length coding, there is a problem that an error propagates. However, in the present invention, refreshing can be performed by utilizing a point that a buffering unit is an integer number of sync blocks.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an overall configuration of an embodiment of the present invention. FIG. 2 is a block diagram illustrating an example of a buffering configuration; FIG. 3 is a schematic diagram for explaining an array of sync blocks of transmission data. FIG. 4 is a schematic diagram illustrating an example of a relationship between a buffering unit and a sync block. FIG. 5 is a schematic diagram illustrating another example of the relationship between a buffering unit and a sync block. FIG. 6 is a schematic diagram of a track pattern according to an embodiment of the present invention. FIG. 7 is a schematic diagram illustrating a useless area generated in a sync block. FIG. 8 is a schematic diagram for explaining a conventional problem. FIG. 9 is a schematic diagram for explaining a conventional problem. FIG. 10 is a schematic diagram for explaining a conventional problem. [Description of Signs] 3 DCT circuit 5 Quantization circuit 6 Estimator 12 Additional information generation circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11B 20/12 G11B 20/10 H04N 5/92 H04N 7/13

Claims (1)

(57) [Claim 1] A digital signal which compresses an input digital image signal having continuous frames by encoding for generating a variable-length encoded output, and transmits the variable-length encoded output. In the image signal transmission device, n (n is a positive integer of 2 or more) shorter than one frame period
) The data generated by the variable-length coded output of the macroblock
The amount of the estimates, the first below the target value the generated data amount
Determine a quantization step to make the value close to the standard value, and
And buffering means for performing re-quantization in step, the n the data amount by the buffering means is controlled
N variable-length coded outputs of macroblocks (N is 1
Distribution in the data area of the sync block or more positive integer)
And means for location, and means for transmitting the data structure of the sync block, the sync block synchronization signal, the additional information is the Day
Data area, and identifies the quantization step or the quantization step.
Code signal for each of the above sync blocks
A digital image signal transmitting apparatus, wherein the additional information is inserted as the additional information .