JP3231833B2 - Band compression signal processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for converting a video signal or the like into a digital signal and performing band compression by combining intra-frame coding and inter-frame coding.
When the output signal is recorded on a tape in a helical scan system and transmitted to a recording / reproducing apparatus for reproducing the same, a good reproduced image can be easily obtained, particularly at the time of high-speed reproduction.

[0002]

2. Description of the Related Art As is well known, in digitally transmitting a video signal, band compression is performed by a transmission method using a variable length coding system, or by combining intra-frame coding and inter-frame coding. Transmission methods and the like are being studied. Among these, the technology of performing band compression by combining intra-frame encoding and inter-frame encoding and transmitting the data is disclosed in, for example, the document IEEE Trans.on Broadcasting.
Woo Paik described in Vol.36 NO.4 DEC 1990: “Digit
al compatible HD-TV Broadcast system "is a band compression technology, and its characteristic parts will be described below.

In FIG. 35, a video signal input to an input terminal 11 is supplied to a subtraction circuit 12 and a motion evaluation circuit 13, respectively. In the subtraction circuit 12, a subtraction process described later is performed, and the output is input to a DCT (discrete cosine transform) circuit 14. The DCT circuit 14 captures 8 pixels in the horizontal direction and 8 pixels in the vertical direction as a unit block (8 × 8 pixels = 64 pixels), and outputs coefficients obtained by converting the pixel array from the time domain to the frequency domain. Then, each coefficient is quantized by the quantization circuit 15. In this case, the quantization circuit 15 has 10 or 32 types of quantization tables, and individual coefficients are quantized based on the selected quantization table. The quantization circuit 15
Is provided with a quantization table so that the amount of generated information and the amount of transmitted information fall within a certain range.

The coefficient data output from the quantization circuit 15 is zigzag-scanned from the low band to the high band for each unit block and extracted.
6 and is subjected to variable-length coding with a set of a subsequent number of zero coefficients (run length) and a non-zero coefficient. The encoder is a variable-length encoder having a different code length depending on the frequency of occurrence of Huffman codes or the like. Then, the variable-length coded data is input to a FIFO (first-in first-out) circuit 17 and is read out at a specified speed. [Control signal, audio data, synchronization data (SYN
C), which multiplexes NMP and the like, which will be described later]. The FIFO circuit 17 serves as a buffer for absorbing the difference between the generated code amount and the transmitted code amount because the output of the variable length coding circuit 16 is a variable rate and the transmission line rate is a fixed rate. .

The output of the quantization circuit 15 is input to an inverse quantization circuit 19 and is inversely quantized. Further, the output of the inverse quantization circuit 19 is input to the inverse DCT circuit 20 and returned to the original signal. This signal is input to the frame delay circuit 22 via the addition circuit 21. The output of the frame delay circuit 22 is supplied to a motion compensation circuit 23 and the motion evaluation circuit 13, respectively. Motion evaluation circuit 13
Is the input signal from the input terminal 11 and the frame delay circuit 2
2 to detect the overall motion of the image, and control the phase position of the signal output from the motion compensation circuit 23. In the case of a still image, compensation is performed so that the original image matches the image one frame before. The output of the motion compensation circuit 23 can be supplied to the subtraction circuit 12 via the switch 24, and can also be fed back from the addition circuit 21 to the frame delay circuit 22 via the switch 25.

Next, the basic operation of the above system will be described. The basic operation of this system includes an intra-frame encoding process and an inter-frame encoding process. The intra-frame encoding process is performed as follows. When this process is performed, the switches 24 and 25 are both off. The video signal at the input terminal 11 is converted from the time domain to the frequency domain by the DCT circuit 14 and quantized by the quantization circuit 15. This quantized signal is output to the transmission path via the FIFO circuit 17 after being subjected to the variable length encoding process. The quantized signal is supplied to an inverse quantization circuit 19
The signal is returned to the original signal by the inverse DCT circuit 20 and is delayed by the frame delay circuit 22. Therefore, at the time of the intra-frame encoding processing, it is equivalent to the information of the input video signal being subjected to variable-length encoding as it is. This intra-frame processing is performed at appropriate intervals in scene changes of the input video signal and in predetermined blocks. The processing in the periodic frame will be described later.

Next, the inter-frame encoding process will be described. When the inter-frame encoding process is performed, the switches 24 and 25 are both turned on. Therefore, a signal corresponding to the difference between the input video signal and the video signal one frame before is obtained from the subtraction circuit 12. This difference signal is
The signal is input to the DCT circuit 14, converted from the time domain to the frequency domain, and then quantized by the quantization circuit 15. Further, since the difference signal and the video signal are added to the frame delay circuit 22 by the addition circuit 21 and input,
A predicted video signal that predicts the input video signal from which the difference signal is generated is generated and input.

FIG. 36 shows a line signal in a state where a video signal of a high-definition television signal has been subjected to the intra-frame processing and the inter-frame processing as described above, and is transmitted on a transmission path. This signal is a signal of a transmission line, and is shown in a state where a control signal, an audio signal, a synchronization signal (SYNC), a system control signal, an NMP, and the like are multiplexed. FIG. 36A shows a signal on the first line, and FIG. 36B shows a signal on the second and subsequent lines. If this video signal has been processed in a frame, a normal video signal can be obtained by performing inverse conversion. However, in the case of a video signal that has been subjected to an inter-frame encoding process, even if this signal is inversely transformed, only a difference signal is reproduced. Therefore, a normal video signal can be reproduced by adding the video signal (or predicted video signal) reproduced one frame before to this difference signal.

According to the above-mentioned system, the signal processed in the frame has all information variable-length coded, and the signal processed in the inter-frame after the next frame transmits differential information, and the This means that compression has been achieved.

Next, the definition of a set of pixels to be processed by the above band compression system will be described. That is, a block: an area of 64 pixels composed of 8 pixels in the horizontal direction and 8 pixels in the vertical direction.

Super block: horizontal direction of luminance signal 4
It is an area consisting of two blocks and two blocks in the vertical direction. This area includes one block each of the color signals U and V. Further, the image motion vector obtained from the motion evaluation circuit 13 is included in a super block unit.

Macro block: 11 super blocks in the horizontal direction. When a code is transmitted, the DCT coefficient of the block is converted into a code determined by the number of consecutive zero coefficients and the amplitude of the non-zero coefficient, and transmitted as a set. Finally, an end-of-block signal is added. Then, the motion vector of the motion correction performed in super block units is
It is added and transmitted in macroblock units.

The transmission signal shown in FIG.
Particularly relevant matters will be further explained. First
The line synchronization (SYNC) signal indicates a frame synchronization signal in the decoder, and all the timing signals of the decoder are generated using one synchronization signal per frame. The NMP signal on the first line indicates the number of video data from the end of this signal to the beginning of the macroblock of the next frame. This is because the code is configured by adaptively switching between the intra-frame encoding process and the inter-frame encoding process, so that the code amount of one frame is different for each frame, and the code position is different. It is to come. Therefore, the position of the code corresponding to one frame is indicated by the NMP signal.

Further, as a countermeasure when the user changes the channel, periodic intra-frame processing is performed. That is, in this band compression system, as described above, the eleven super blocks in the horizontal direction are called macroblocks, and there are 44 super blocks in one screen in the horizontal direction. That is, there are a total of 240 macroblocks in one frame, including 4 macroblocks in the horizontal direction and 60 macroblocks in the vertical direction. In this band compression system, FIGS.
As shown in FIGS. 38 (a) to 38 (c), refresh is performed for each column of a superblock in units of four macroblocks, and all superblocks are refreshed every 11 frames. That is, as shown in FIG. 38 (d), by storing 11 frames of refreshed super blocks, intra-frame processing is performed in all areas.
For this reason, for example, during normal reproduction of a VTR (video tape recorder) or the like, the above-described intra-frame processing is performed at a period of 11 frames, so that a reproduced image can be viewed without any problem.

Note that head data is inserted at the head of the macro block. This head data includes
A motion vector, a field / frame determination, a PCM / DPCM determination, a quantization level, and the like of each superblock are inserted together.

By the way, the above-mentioned band compression system includes:
It is used as an encoder for band compression of a television signal, and its decoder is used on the receiving side. Here, it is considered that the transmission signal is recorded on a VTR.
A general VTR is a method in which a video signal of one field is converted into a fixed-length code, a certain amount of information is generated, and recorded on X tracks (X is a positive integer).

On the other hand, if it is attempted to record and reproduce on a VTR using the transmission signal obtained by the above-mentioned band compression system as it is, the variable-length code is used as it is for the intra-frame processing and inter-frame processing code. The position where the code processed in the frame is recorded is not fixed, and blocks that are not refreshed are generated at the time of high-speed reproduction.

More specifically, FIG. 39 shows a track pattern in the case where the variable-length coded signal is helically recorded on the magnetic tape 26 as described above. In the track patterns T _{1 to} T ₁₁ , the portions indicated by thick lines indicate the switching positions of the frames F _{1 to} F ₁₁ . The switching position of the frame F ₁ to F ₁₁ are not aligned is that the recording data is created by the variable-length code. When the magnetic tape 26 is normally reproduced by a VTR, all the track patterns T _{1 to} T ₁₁ are sequentially scanned by a magnetic head. Video signals can be reproduced. That is, at the time of normal reproduction, all of the codes processed on the intra-frame and the codes processed on the inter-frame, which are recorded on the magnetic tape 26, can be reproduced, so that an image can be formed using all the codes.

However, in a VTR, there are cases where only a limited number of tracks are reproduced, for example, in a double speed reproduction mode in special reproduction. At this time, the magnetic head jumps the track and picks up the recording signal. In this case, there is no problem if the tracks of the signal subjected to the intra-frame encoding processing are successively reproduced, but if the track subjected to the inter-frame encoding processing is reproduced, only an image based on the difference signal is obtained.

FIG. 40 shows trace trajectories X _{1 to} X ₁₁ of the magnetic head when double-speed reproduction is performed. FIG.
At 0, since the signals subjected to the intra-frame encoding processing are dispersedly recorded in the frames F _{1 to} F ₂₄ , the position of the intra-frame processing portion reproduced on the screen is undefined. FIGS. 41 (a) to 41 (h) and FIGS. 42 (a) to 42 (c) show intra-frame processed signals which can be reproduced at 2 × speed reproduction. And these 1
When one frame is accumulated, as shown in FIG.
There is no code that has undergone periodic intra-frame processing, that is, there is a portion where a refreshed super block does not exist, and a portion where a reproduced image cannot be formed occurs.

[0021]

As described above, the helical scan recording / reproducing apparatus provided with the conventional band compression system has a problem that high-speed reproduction such as double-speed reproduction becomes difficult.

Therefore, the present invention has been made in view of the above circumstances, and has as its object to provide an extremely good band compression signal processing apparatus capable of easily obtaining a good reproduced image at high speed reproduction.

[0023]

A band compression signal processing apparatus according to the present invention forms a (a is a positive integer) image area in a video signal of one screen, and applies a frame to the video signal. An intra-frame processing signal that has been subjected to intra-frame encoding processing using information within the frame, and an inter-frame processing signal that has been subjected to inter-frame encoding processing using differential information between frames, are created. After that, an inter-frame encoding process is performed, and this signal processing method is adaptively repeated according to the motion evaluation of the input video signal. Refresh coding processing means for periodically performing intra-frame coding processing on signals of b image areas out of a areas, and combining a plurality of blocks subjected to the refresh coding processing. ,bird Forming a click blocks, as well as arranged between the non-trick block not subjected to refresh encoding process, a code indicating a code length of the trick block
This is added to overhead data .

[0024]

According to the above configuration, a signal subjected to intra-frame encoding processing can be obtained accurately at the time of high-speed reproduction, so that a good reproduced image can be obtained.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. In this embodiment, since the intra-frame encoding process is performed on 2640 regions per screen in 11 frames, the number of regions a per screen is a = 2640 and the intra-frame encoding processing period f = 11 frames. Here, an example in which a = 2640 regions do not overlap each other is used, but they may overlap. further,
In order to explain the case where one track is divided into 10 and the average video code for one frame is recorded in one track, the number of divisions d per track = 10, the number of tracks for recording the average video code for one frame Let c = 1. Therefore, the number of recording medium areas is d × c × f = 10 × 1 × 11 = 110. The correspondence between the screen area and the recording medium area will be described in the case of equal distribution. Note that, in the present invention, it is not always necessary to equally allocate. Therefore, the number of screen areas e = a / d × c × f = 2640 that enters one recording medium area
/ 10 × 1 × 11 = 24 pieces, and e = 24 pieces are replaced by d
The case of associating with × c × f = 110 regions will be described.

In FIG. 1, the same parts as those in FIG. 35 are denoted by the same reference numerals, and the description will focus on the parts different from the conventional system. FIG. 2 shows the operation timing of this system. Here, this embodiment will be described with reference to a block diagram on the encoder side for the sake of simplicity, but it can also be realized on the decoder side receiving the transmission data shown in FIG. FIG. 1 will be described. The input terminal 27 is supplied with a synchronization signal SYNC of the input video signal. This synchronization signal SYNC is S
The signal is input to the YNC signal detection circuit 28 and detected. SY
The NC signal detection circuit 28 generates a SYNC pulse synchronized with the synchronization signal SYNC to generate the track formation signal generation circuit 2
9. In the case where the synchronization signal SYN in the transmission data shown in FIG.
C may be detected and input to the SYNC signal detection circuit 28.

FIG. 2A shows an input video signal, Y indicates a luminance signal, U and V indicate chrominance signals, and the numbers written in the frames indicate frame numbers. FIG.
(B) SY obtained from the SYNC signal detection circuit 28
An NC pulse is generated in synchronization with a frame switching point of the input video signal shown in FIG. FIG. 2C shows a track forming signal obtained from the track forming signal generating circuit 29. A and B attached to the track formation signal designate a period in which the A head and the B head alternately form a track. A
As shown in FIG. 1, the head and the B head are mounted at a position facing the rotary drum 30 by 180 °. Here, a case will be described in which heads are attached one by one, but if the amount of code that can be recorded in one track is small, p (p is a positive integer) opposed heads should be arranged. Good. In this embodiment, the SY shown in FIG.
The generation timing of the NC pulse and the switching timing of the track forming signal shown in FIG. 2C are synchronized. FIG. 2D shows a track formed by the A head and the B head, and the numbers written in the frames indicate the track numbers.

The track forming signal output from the track forming signal generating circuit 29 is supplied to a track forming control circuit 31. This track formation control circuit 31
Controls the rotation phase of the rotating drum 30 and
The timing of supplying recording signals to the head and the B head is controlled. In this embodiment, since the average code generation amount of one frame corresponds to one track, the rotating drum 3
The case where the number of rotations of 0 is 900 rpm will be described. However, the average generated code of one frame may be recorded on c tracks (c is a positive integer) by c magnetic head scans, and the rotation speed of the rotating drum 30 may be set to a different rotation speed such as 1800 rpm.

Next, a description will be given of a code permutation method used in this embodiment to enable high-speed reproduction of a VTR. First, multiplexers 37 combine the respective signals obtained by passing the color signals U and V supplied to the input terminals 32 and 33 through the decimators 34 and 35 and the luminance signal Y supplied to the input terminal 36. The input video signal is supplied to the subtraction circuit 12 and the motion evaluation circuit 13, and the variable length coding circuit 16 outputs a band-compressed video code.

In the conventional band compression system shown in FIG. 35, a video signal is transmitted after being subjected to variable-length coding. As shown in FIG. Is different. FIG.
The NMP signal shown in (h) indicates a switching point of a frame of the video signal. Conventionally, 2640 superblocks exist in one frame, and the 2640 superblocks are included in one frame period indicated by the NMP signal in FIG.

Conventionally, four macroblocks exist in a horizontal direction on one screen, and these macroblocks are composed of 11 super blocks. Then, one superblock in the microblock per frame uses the intra-frame processing forcibly. The sequence for forcibly using the intra-frame processing is included in the system control signal of FIG. Here, the super block for which the intra-frame processing is forcibly performed is referred to as a refresh block, and the super block for which the intra-frame processing is not forcibly performed is referred to as a non-refresh block.

In other words, as a definition of the term, refresh block: When the intra-frame processing is forcibly performed one super-block at a time in one frame period among macro blocks, the super-block which has performed the intra-frame processing is called a refresh block. Since a macro block is composed of 11 super blocks, 1
Intra-frame processing is forcibly performed in one frame cycle.

Non-refresh block: A super block other than the refresh block described above. In this super block, there are a block that has undergone intra-frame processing and a block that has undergone inter-frame processing, depending on the contents of an image. For example, when a scene change or the like occurs in an input video signal, in-frame processing may be used, but this is also a non-refresh block.

Here, in one frame period, there are 240 refresh blocks (= 2640 フ レ ー ム 11). Therefore, conventionally, there are 240 refresh blocks in one frame period shown in FIG. 2H, as shown in FIG. 2G. Then, the conventional signal is directly used as VT
When recording with R, the position of the refresh block cannot be determined, and high-speed reproduction cannot be performed as described above.

FIGS. 3A and 3B show video signals of frame numbers F ₅ and F ₆ , respectively. In the figure, the portions indicated by G ₅ and G ₆ indicate refresh blocks, and the portions indicated by H ₅ and H ₆ indicate non-refresh blocks. Thereafter, between the frame number, the refresh block number, and the non-refresh block number, the refresh block number of the frame having the frame number F _n (n is an integer) is G _n , and the non-refresh block number is H _n .

In the present invention, the arrangement of the refresh block and the non-refresh block on the track is made different.

This embodiment shows a case where one track is divided into ten parts and recorded. When one track is divided into ten, high-speed reproduction can be performed up to 10 times speed. At the time of high-speed reproduction of 11 times or more, all the refresh blocks cannot be reproduced, so that an area where an image cannot be formed occurs, as in the diagram shown in FIG. If it is desired to realize high-speed reproduction of 20 times speed as a VTR specification, one track may be divided into 20. Furthermore, when it is desired to realize fast high-speed reproduction, refresh blocks may be arranged at equal intervals on a track.

FIG. 2E shows a timing pulse for dividing one track into ten parts. One track period shown in FIGS. 2B and 2C is divided into ten equal parts.
The divided one period is called a sector.

That is, as a definition of a word, a sector: d is almost equally divided into one track period (in this case, 1
0) Refers to the divided period.

In this embodiment, as shown in FIG. 2F, 24 refresh blocks are put in one sector. In this case, since one track includes 10 sectors, 240 refresh blocks are inserted in one track, which is equal to the number of refresh blocks in one frame of the video signal. That is, the number e of refresh blocks included in one sector is defined as b, where b is the number of super blocks in which intra-frame processing is periodically performed.
If b intra-frame processing signals are recorded on c tracks, e = b / c × d (in this case, 240/1 × 10
= 24).

By performing the above-described code exchange, the refresh block for one frame is conventionally arranged in one frame period indicated by the NMP signal, but the refresh block for one frame is arranged in one track period. It can be arranged to be present.

FIG. 4 shows a track pattern. That is, the tracks T _{1 to} T ₁₁ on the magnetic tape 26
G ₁ was filled in the frame of ~G ₁₁ corresponds to the refresh block number G _n described above. The relationship between the refresh blocks and the track T _n is the number in the track T _n G
The relationship is that _n refresh blocks are recorded. Further, H ₁ to H ₁₁ filled out in the frame of the track T ₁ through T ₁₁ are non-refresh block number H mentioned above
Corresponds to _n . The switching point of the non-refresh block is a thick line portion shown in the frame of the tracks T _{1 to} T ₁₁ .

Track 38 in FIG. 4 shows the relationship between sectors and tracks. The track 38 is divided into 10 and d =
It is divided into ten sectors. In this one sector,
e = 24 refresh blocks are arranged. The non-refresh block is inserted while the refresh block is arranged.

[0044] Here, if the track T _5, T ₆ will be described in detail as an example, the track T ₅ to record refresh blocks G ₅ of the frame F _5. Also, track T
The ₆ records the refresh block G ₆ of the frame F _6. A non-refresh block is recorded in the empty portion where the refresh block is arranged. The track T ₅ records non refresh block H _5, H _6, the track T ₆ records the non-refresh block H _6, H _7.

Therefore, in order to realize the above-mentioned recording mode, the video code subjected to the band compression encoding obtained from the variable length encoding circuit 16 in FIG. 1 is supplied to the code exchanging circuit 39 again. The refresh block control circuit 40 generates a code position signal of the above-described refresh block. The code position signal is supplied to the code replacement circuit 39. The code permutation circuit 39 rearranges refresh blocks and non-refresh blocks based on the input video code and code position signal.

That is, a process of inserting 24 refresh blocks into each of 10 sectors provided in one track is performed. This processing is realized by temporarily storing codes in a memory (not shown) and reading the codes from the memory so that 24 refresh blocks are included in one sector.

The output of the transposition circuit 39 is
It is supplied to the index insertion circuit 41. The index insertion circuit 41 inserts an index signal into the control data section of each sector so that it can be detected at the time of reproduction that a non-refresh block is partially separated and recorded. The index signal is prepared by an index generation circuit 42 to which a code position signal from the refresh block control circuit 40 is supplied. Then, the output of the index insertion circuit 41 is
The data is supplied to the A head and the B head via the multiplexer 43 and is recorded on the magnetic tape 26.

In the case where the refresh block and the non-refresh block are exchanged in the decoder, the PCM / DPC of the head data existing at the head of the macroblock inside the video code shown in FIG.
The refresh sequence code included in the M determination code and the system control signal may be detected and used as an output signal of the refresh block control circuit 40.

FIGS. 5A and 5B show trace loci X _{1 to} X ₁₁ of the head during double speed reproduction. Note that within the framework of each track T ₁ through T _22, refresh similar to FIG. 4 blocks G _n and non-refresh block H
Indicates _n . In the head trace at the time of double speed reproduction shown in FIG. 5, reproducible refresh blocks are shown in FIGS. 6 (a) to 6 (h) and 7 (a) to 7 (c). FIGS. 6A to 6H and FIGS.
Frames 1 to 11 shown in (c) correspond to frames 2 to 11 shown in FIG.
Speed indicates playable refresh block at a head trace loci X ₁ to X ₁₁ at the time of reproduction.

[0050] In example frame 1, by performing the head trace X _1, displays the refresh block G ₁ in the upper half of the screen, it is possible to display the refresh block G ₂ in the lower half of the screen. Similarly, in frames 2 to 11, the refresh block G ₃
It is possible to play up to ~G _22. Therefore, if reproducible refresh blocks are accumulated in frames 1 to 11, codes in all screen areas can be reproduced as shown in FIG. 7D.

The code subjected to the inter-frame processing and the code subjected to the intra-frame processing according to the content of the image are included between the codes subjected to the intra-frame encoding processing periodically. These codes have no correspondence between the image area and the recording medium area.

In the present invention, the correspondence between a image areas and d × c × f recording medium areas is 1: 1.
Or a 1: 2, 2: 1 correspondence,
Any correspondence may be used, such as a correspondence in which a blank is inserted in the area of the recording medium. The recording medium is not limited to the magnetic tape 26, but may be applied to a video disk. In this case, one round of the disk corresponds to one track of the tape.

Although high-speed reproduction is possible by inserting a refresh block in a predetermined area on the track of the VTR, it is necessary to prevent the code amount from exceeding the code amount recordable in the predetermined area.

The code amount of a predetermined refresh block is
If the recordable code amount in a predetermined area of the recording medium is exceeded, refresh is not performed at a position on the screen corresponding to the exceeded code.

Even if this is not avoided, refreshing is performed from a certain fixed position on the image, so it is highly possible to judge the contents of the image. Requires control of the amount of code generated in the refresh block.

In this example, the code of the refresh block is divided into a plurality of parts, so that the low-frequency component or MSB of the refresh block
Insert the sign.

Therefore, the code amount of the refresh block will be described in detail.

First, a two-dimensional DCT circuit will be described.

First, the image is divided into small blocks (N × N) each including N pixels in both the horizontal and vertical directions, and each block is subjected to two-dimensional DCT. The size of N at this time is set to 8 to 16 from the conversion efficiency. In this embodiment, N =
8 is used.

The transform coefficient of the two-dimensional DCT is given by equation 1, and its inverse transform equation is given by equation 2.

[0061]

(Equation 1) Here, F (0,0) represents a DC component coefficient,
(U, v) includes high frequency horizontal frequency components as u increases, and high frequency vertical frequency components as v increases.

First, the nature of the coefficient of the DC component of F (0,0) will be described. F (0,0) corresponds to a DC component representing an average luminance value in an image block, and its average power is usually considerably larger than other components.

Further, when the DC component is coarsely quantized, noise (block distortion) peculiar to the orthogonal transformation which is visually perceived as large image quality deterioration is generated. Then, F (0,0)
Is assigned a large number of bits (usually 8 bits or more) and is equally quantized.

Next, the conversion coefficient F (u, v) excluding the DC component
State the nature of The average value of F (u, v) is given by Equation 1,
It becomes "0" except for the DC component F (0,0).

When a fixed number of bits is assigned to a small block of an image to perform efficient encoding, a large number of encoded bits are allocated to transform coefficients of low-frequency components, and conversely, By performing coding by allocating a small number of coding bits to the transform coefficient of the high-frequency component, it is possible to reduce deterioration in image quality and perform coding at a high compression rate.

The image is converted into a small block of 8 × 8 = 64 pixels consisting of 8 pixels in both the horizontal and vertical directions,
When the CT is performed, the converted coefficients for each frequency component are 8 × 8 = 64 two-dimensional coefficients as shown in FIG. In FIG. 8, the upper left is a DC coefficient (DC component). The other 63 are AC coefficients (AC components), and the spatial frequency increases toward the lower right. Since the AC component has a two-dimensional spread, it is converted to one-dimensional by zigzag scanning shown in the order of 0 to 63 upon encoding and transmission.

Here, the coefficients of the 64 DCTs are represented by DCT _i
It is represented by [i = 0 to 63].

The number of quantization bits for quantizing each pixel is often 8 bits in the case of an image signal.

The DCT coefficient of the output obtained by performing the DCT conversion on the 8-bit pixel may be represented by 12 bits.

Next, quantization will be described.

The above-mentioned 64 DCT coefficients are linearly quantized with a different step size for each coefficient position, using a quantization table which defines a quantization step size for each coefficient.

There are two methods for setting the quantization step, but they are basically the same.

The first method is a method of transmitting a code indicating a quantization table using a quantization table in which a quantization step is determined for each of 64 DCT coefficients.

FIG. 9 shows an example of the quantization table. In the figure, q = 0 to q = 9 are quantization table codes representing a quantization table, and the decoder can perform inverse quantization by transmitting this code.

The 64 numbers arranged in a square indicate the number of quantization bits, and have a correspondence with the 64 two-dimensional coefficients shown in FIG. For example, 7 in the upper left of the quantization table of q = 0 indicates that the DC component is quantized by 7 bits.

Hereinafter, each coefficient is similarly quantized by the number of bits indicated in the quantization table.

In the second method, first, 64 DCT coefficients are weighted using a weighting matrix.

Thereafter, the quantization width data QS (Quantize-S
This is a method in which each coefficient is uniformly divided and then quantized using cale). At the time of transmission, a code corresponding to the quantization width data is sent. The weight matrix has a default value. Furthermore, a specific type of weighting matrix can be transmitted.

As an example, MPEG. In I, 5 bits are assigned to the code of the quantization width data QS, and 32 types can be designated. Therefore, this value is represented by QS _j [j = 0 to 31].

Here, the quantization width data QS _{j will be} defined.

The case where the DCT coefficient value is quantized with the maximum number of quantization bits is represented by j = 0, and QS ₀ = 1.

The case where the DCT coefficient value is not transmitted is represented by j = 31. At this time, the number of quantization bits, which will be described later, is QL ₃₁ = 0.

Here, j is referred to as a quantization level.

FIG. 10 shows MPEG. The default value of the weighting matrix of the luminance signal used in I is shown.

In the figure, 64 numbers of 8 × 8 are:
There is a correspondence with the 64 two-dimensional coefficients shown in FIG.
The weighting value for each DCT coefficient is shown.

In the encoder, each coefficient of the DCT is divided by the corresponding weight value and quantization width data QS.

The coefficients of the 64 DCTs are represented by DCT _i [i = 0
６３63], and each value of the weighting matrix is represented by WEIGHT _i [i = 0 to 6].
3] When each value after quantization is represented by Q _i [i = 0 to 63],

(Equation 2) Is represented by

The number of quantization bits at this time is

(Equation 3) Is represented by

An example is shown below.

MPEG. I in the vertical direction of the luminance signal of I
The AC component is represented by DCT ₁ in FIG. 8 described above.

The value corresponding to DCT ₁ in the weighting matrix is WEIGHT ₁ = 16. This is shown in FIG.
Corresponds to the part marked with a circle. When the quantization width data QS ₀ = 1,

(Equation 4) Since the coefficient of DCT _i is represented by 12 bits, log ₂ D
The maximum value of CT _i is 12. The number of quantization bits at this time is

(Equation 5) Becomes

FIG. 11 shows the required maximum number of quantization bits after passing through the weighting matrix when QS ₀ = 1. This figure is a matrix representing 8 × 8 = 64 quantization bit numbers, and each number indicates the quantization bit number corresponding to each position of the DCT coefficient shown in FIG.

FIGS. 12 and 13 quantitatively show nine representative quantization tables among the quantization tables when 32 types of quantization width data QS _j are set.

In order to explain the case where the above-described second method regarding the quantization table is used, this table is based on the quantization width data QS.

Here, j = 31 is an example in which no data is generated, and corresponds to quantizing all coefficients with 0 bits. Also, j = 0 is the quantization width data QS ₀ = 1
Therefore, it is equivalent to quantization with a weighting table. That is, in this case, the bits are allocated by the weighting table shown in FIG.

In FIGS. 12 and 13, the horizontal axis represents DCT.
These 64 coefficients correspond to the order of the zigzag scan shown in FIG. The vertical axis is D
In each coefficient of CT, the number of bits to be transmitted is shown.

When quantizing the DCT coefficients, M
From SB (Most Significant Bit) to LSB (Least Sign)
ificant Bit) is present. When limiting the number of bits to be transmitted, naturally, the MSB is transmitted with priority.

As described above, if the number of quantization bits is reduced for the DC component, block distortion and the like become conspicuous, so that the DC component is treated separately, and there is an example in which a fixed number of quantization bits is allocated. Here, it is assumed that 8 bits are allocated.

MPEG. In the case of the example of the luminance signal of I, the maximum value of the AC component is 8 bits as described above.

With reference to FIGS. 12 and 13, a quantitative description will be given of the number of quantization bits and quantization width data.

The generated code amount becomes maximum when j = 0, and as j increases, the generated code amount decreases.
It becomes 0 at 31 and no sign is generated.

It is possible to control the amount of code generated by controlling the quantization width data.

There are two types of code amount control methods. The first method is a method of controlling the quantization level as described above. In this case, the generated code amount of the refresh block is suppressed, so that the image quality of the refresh block itself is deteriorated. However, in the next frame, the difference between the in-frame processing signal of the refresh block and the video signal of the next frame is sent, so that the image quality only drops momentarily.

The second technique is to divide the code once quantized into two, and to reduce the amount of code of the MSB or low frequency component to VTR.
This is a method of reducing the amount of codes that can be read out at the time of high-speed reproduction on a recording medium such as this.

On the other hand, when special reproduction is realized using a refresh block in a recording medium such as a VTR, the refresh rate of the screen can be surely maintained at a constant cycle by controlling the code amount of the refresh block to a predetermined code amount. .

Regarding this, Japanese Patent Application No. 3-250671 is disclosed.
It is described in the issue.

There are the following two methods according to the technique of the special reproduction of the VTR.

The first method is a method using DTF as a VTR servo method.

When the maximum recording code amount that can be recorded on p tracks formed in one scan is α, and when a video signal is recorded by c head scans per frame, 1 / c of the video of one frame is recorded. It is necessary to keep the maximum code amount of the refresh block in the area at or below α.

The second method is a case where DTF is not used.

When the DTF is not used, the high-speed reproduction speed is i
In the case of (1), 1 / i of the p tracks formed in one scan is traced.

As described above, when the maximum code amount that can be recorded on p tracks formed in one scan is α, and a video signal is recorded by c scans per frame,
It is necessary to keep the maximum code amount in the 1 / c × i area of the refresh block of one frame to α / i or less.

In this case, the case where an extremely wide head is not used as the special reproduction head is shown.

FIG. 14 is a diagram showing an embodiment of the present invention.

Although the present embodiment is described using an example on the encoder side, it can also be realized in a decoder. In that case, it can be realized by extracting necessary signals from the output of the variable length decoding circuit of the decoder or from the inside.

First, the output signal of the quantization circuit 15 passes through a zigzag scan circuit 44 and is then input to a code arrangement circuit (code replacement circuit) 45.

The zigzag scan circuit 44 rearranges 8 × 8 DCT coefficients by the scan method shown in FIG.

The purpose of the operation of the code arrangement circuit 45 is the same as that of the code replacement circuit 39 described with reference to FIG. 1, and the arrangement of the codes is such that the refresh block signal is recorded in a predetermined area on the tape. is there.

In this embodiment, the code of the refresh block is divided so that the code amount that can be recorded in a predetermined area on the tape is recorded, and the code corresponding to the low-frequency component or the MSB component is recorded in the predetermined area. I will focus on the case.

When the code amount of the refresh block is not divided and the code amount of the refresh block is limited to a code amount that can be recorded in a predetermined area on the tape, the refresh block is recorded in the predetermined area and the decoder circuit is used. The effect of the present invention can be realized without using a part (refresh block dividing circuit 72 and refresh block low band / high band code combining circuit 73).

In the code arrangement circuit 45, the refresh block separation circuit 46 first performs a refresh block selection 46a and a non-refresh block selection 46b.

Regarding the non-refresh block selection 46b, as in the conventional example, the variable length coding circuit 47 performs variable length coding processing and temporarily stores it in the memory 48.

Refresh block code division circuit 49
Is a low frequency or MSB extraction circuit 49a and a high frequency or L
It comprises an SB extraction circuit 49b. This output signal is stored in the memory 48 through the variable length coding circuits 50 and 51, respectively. In the low band or MSB extraction circuit 49a, the VTR
The low band or MSB code of the refresh block is extracted so as to be within the code amount of a predetermined area to be reproduced at the time of special reproduction. This extraction method will be described later in detail.

The memory 48 exchanges the codes of the low-frequency component or the MSB component of the refresh block so that special reproduction can be performed, and reads the code from the memory.

Next, a method of dividing the code of the refresh block will be described.

First, the features of the conventional refresh block will be summarized.

1) A refresh block is a super block that has been forcibly subjected to intra-frame processing.

2) The super block includes eight luminance signal blocks and two chrominance signal blocks. The DC components of the eight luminance signal blocks are converted into DPCM and Huffman-coded.

3) The AC component of the luminance signal and the chrominance signal are
Zigzag scan and Huffman coding.

The method of dividing the refresh block is 4
There are types.

This will be described with reference to FIGS.

The code of the non-refresh block is not divided and is processed in the same manner as in the conventional example.

FIGS. 15 to 18 show the respective coefficients obtained by arranging the DCT coefficients by zigzag scanning on the horizontal axis, similarly to FIGS. 12 and 13. The vertical axis indicates the number of bits used for quantization.

FIG. 15A, FIG. 16A, FIG.
7 (a) and FIG. 18 (a) show the number of quantization bits before code division. Here, a case where the quantization level j = 0 before division is shown.

The first method is a method of dividing a DC component and an AC component of a refresh block as shown in FIG.

That is, the code in FIG. 15A is divided into a DC component (FIG. 15B) and an AC component (FIG. 15C). Then, a code is transmitted so that the DC component (FIG. 15B) is recorded in the trick sector.

Here, words are defined.

Trick sector: An area on a recording medium obtained by dividing a tape track into a plurality of sections is referred to as a sector, and during trick play, a sector to be reproduced is referred to as a trick sector.

As a method of minimizing the change from the conventional circuit, there is a method of recording only the DC component of the luminance signal in the trick sector.

The remaining reference numerals shown in FIG. 15C are recorded in places other than the positions where the reference numerals in FIG. 15B are arranged.

Since the DC components of the conventional example are all quantized with the same bit, no additional information indicating the number of quantization bits is required.

If the code amount of the DC component of the refresh block exceeds the maximum recording code amount of the trick sector on the tape, the bit on the MSB side of the DC component is transmitted, and the additional information indicating the quantization level is transmitted. There are also transmission methods.

In the second method, a low-frequency component (FIG. 16B) and a high-frequency component (FIG. 16C) of a refresh block are used.
Is a method of dividing Non-refresh blocks are not divided.

In this case, the DC component of the refresh block and the AC component on the low frequency side as shown in FIG. 16B are recorded in the trick sector on the track, and the rest of the refresh block is recorded in other portions. The high-frequency component and the code of the non-refresh block are recorded.

In the non-trick sector, the AC component on the high frequency side of the refresh block and the code of the non-refresh block are recorded.

The low-frequency AC component shown in FIG.
The zigzag scan is performed halfway, after which a code of EOB (End of Block) indicating the end point of the block is forcibly inserted and transmitted as a code of one block.

In the example of FIG. 16B, the sign of EOB is inserted after the first to ninth coefficients of the DC and AC components of the zigzag scan.

Next, the AC on the high frequency side shown in FIG.
The components will be described. Here, since the component corresponding to the low-frequency component transmitted in FIG. 16B has already been transmitted,
The amplitude becomes 0. Therefore, after assigning the Huffman code indicating the number of consecutive 0s, Huffman coding is performed by indicating the number of consecutive 0s and the amplitude of the non-zero coefficient, as in the conventional example.

At the time of normal reproduction and slow reproduction, a low-frequency component of a refresh block recorded in a trick sector and a high-frequency component of a refresh block recorded in other places are combined to reproduce a high-resolution reproduced image. Get.

In the synthesizing method, the low-frequency component and the high-frequency component of the refresh block are each subjected to Huffman decoding, and when performing an inverse zigzag scan, respective codes are arranged to obtain DCT coefficient values.

At the time of high-speed reproduction, a high-speed reproduction image is obtained by using low-frequency components of a refresh block reproduced from a trick sector.

Since the high-frequency AC component is not used, the resolution falls, but there is no problem in locating the screen.

The third method is a method of recording the MSB side of a code in a trick sector.

In the conventional quantization table determination method, first, a weighting coefficient is multiplied, and then quantization width data is further multiplied. The quantization level j corresponding to the quantization width data is transmitted.

In this method, the code of the quantization level j = 0 shown in FIG.
After the transform coefficients of the DCT are obtained, a value having a large quantization level number j, that is, j for transmitting the MSB side at the time of quantization is set.

Here, as shown in FIG. 17 (b), the code having the input quantization level j = 0 is created with a code of j = 16 and recorded in the trick sector. Also, this quantization level j = 16 is recorded. This code corresponds to a code obtained by increasing the number of quantization levels and coarsely quantizing the content of an image. Therefore, as can be seen by comparing FIG. 17A and FIG. 17B, the code at the quantization level j = 16 indicates the MSB side of the code at the quantization level j = 0.

The code shown in FIG. 17C is a code corresponding to the difference between the quantization levels j = 0 and j = 16.
This represents the LSB side of j = 0. This code is Huffman-coded.

17 (b) except that the code of the quantization level j = 16 is recorded in the trick sector.
Record the code of (c).

At the time of normal reproduction and slow reproduction, the coarsely quantized code of FIG. 17B reproduced from the trick sector and the code of FIG.
, An image with less quantization noise is obtained.

At the time of special reproduction, a coarse and quantized code reproduced from a trick sector is output. Although a large amount of quantization noise is generated, it is possible to perform cueing in a VTR.

The fourth method is a method of recording a code on the MSB side in a low frequency band in a trick sector.

FIG. 18B shows the distribution of the number of quantization bits in the quantization table. As a quantization table for high-speed reproduction, a table is prepared for finely quantizing the low band and coarsely quantizing the high band.

A code (FIG. 18B) using a quantization table for high-speed reproduction is recorded in the trick sector.

The input code shown in FIG.
The sign of the difference in (b) is as shown in FIG.

This code and the code of the non-refresh block are recorded at a position other than the position where the code of FIG. 18B for special reproduction is recorded.

By using such a quantization table, the amount of generated code is suppressed, and the second
With this method, it is possible to obtain a slightly better image quality.

The coding method is the same as that of the third method. A code is formed by the quantization bit number distribution shown in FIG. 18B and recorded in a trick sector. Further, FIG.
Huffman coding of the code shown in FIG.
Record in a place other than the place where the code was recorded.

As described above, the code of the refresh block is divided into the low band or the MSB component and the high band or the LSB component, and the low band or the MSB component is recorded in the trick sector. Blocking is performed, and the image quality of the special reproduction image can be improved.

FIG. 19 is a diagram showing another embodiment of the present invention.

In the same figure, the same components as those of the conventional example
The same numbers are given. In addition, although the present embodiment considers minimizing the difference from the conventional example, the minimum change is made.However, it is possible to variously change the block configuration without changing the gist of the present invention. Needless to say.

The gist of the present invention is to divide a refresh block to be subjected to intra-frame processing into the entire area of the screen at intervals of f frames and to reduce the amount of generated codes of low-band or MSB codes by VCR.
Or the like, or a predetermined code amount determined from the recording medium.

In order to realize this gist, in the present invention,
The code amount of the low band or MSB code of the refresh block is independently calculated, and the division level of the refresh block is determined using this value. As described above, there are four types of code division methods, and in each of them, it is possible to control the amount of low-band or MSB code. The case of dividing into a band and a high band code will be described.

As a configuration, the refresh block code amount detection circuit 52, the refresh block low band code amount calculation circuit 53, and the refresh block division level setting circuit 54 are used as main components other than the above-described embodiment.

First, in each refresh block code amount detection circuit 52, the refresh block selection 46a
A refresh block is input, and the number of continuous 0-coefficient DCT coefficients and the amplitude of non-zero coefficients of each block inside the refresh block are detected. ROM storing a table as shown in FIG. 20 for the number of consecutive 0 coefficients and the amplitude of the non-zero coefficient.
To calculate the code amount of each refresh block.

FIG. 20, which is also used in the conventional example, shows the amplitude of the non-zero coefficient on the horizontal axis and the number of consecutive 0 coefficients on the vertical axis. The number in the frame indicates the number of bits of the code. By adding the number of bits of this code,
The generated code amount can be calculated in block units or super block units.

By comparing the calculated code amount with the target low-band code amount of each refresh block, the division level is set by the refresh block division level setting circuit 54 and input to the refresh block code division circuit 49. The target low-band code amount of the refresh block may be a constant value.

Further, in order to improve the control accuracy of the low-frequency code amount, a refresh block low-frequency code amount calculation circuit 53 may be used.

The refresh block low band code amount calculation circuit 53 calculates the low band code amount of the refresh block in a predetermined period.

As a VTR servo, no DTF is used.
In the case where a video signal is recorded by c = 1 head scan per frame and i = 2 × speed is realized as a special reproduction speed, refreshing of 1 / c × i = １ ／ region of video of one frame is performed. A case where the code amount of a block is calculated will be described.

When the code amount of this refresh block is the maximum recordable code amount α that can be recorded on p tracks formed in one scan, the code amount of the refresh block in a half area of one frame is α / c. The division level is set by the refresh block division level setting circuit 54 so that × i = α / 2 or less.

FIG. 21 shows a setting method for setting the quantization level based on the output signal of the refresh block low band code amount calculation circuit 53. In this example, a case is described in which the head scan of the VTR is one scan and the average code amount of the video signal of one frame is recorded. Also, a case will be described in which the trick play speed is doubled. In the embodiment, since there are 240 refresh blocks per frame, 120 refresh blocks are recorded per sector. This will be described in detail.

FIGS. 22 (a) and 22 (b) show a refresh block in one screen and a dividing method when the refresh block is further divided. F _n shown in FIG. 22 in (a) shows the screen of the n-th frame. G _n indicates a refresh block in the n-th frame. This refresh block is 240
Exists. In addition, G shown on the left side of the screen
_n (0) and G _n (1) indicate refresh blocks obtained by equally dividing the 240 refresh blocks in the vertical direction. That is, G _n (0) indicates 120 refresh blocks existing above the screen among the G _n refresh blocks. G _n (1) is
It shows the refresh blocks in the lower area of the screen, and includes 120 refresh blocks.
FIG. 22B shows a refresh block of frame number F _{n + 1} , and the definitions of G _{n + 1} (0) to G _{n + 1} (1) are the same as those in FIG. .

Next, the track pattern of the VTR will be described. FIG. 23 shows a track pattern on the magnetic tape 26. T _{0 to} T ₁₀ and T _n are the rotating drum 3
5 shows tracks recorded using the heads A and B of 0. Here, a case where the average generated code amount of one frame is recorded on one track will be described. That is, c =
The case of 1 will be described. This corresponds to the case where b = 240 refresh blocks are recorded on one track. That is, the refresh blocks G _n of the frame number F _n will be recorded in the track T _n.

In this configuration, when performing double-speed reproduction, the reproduction head crosses two tracks. Therefore, one track is divided into two equal parts.
While reproducing the area No. 2, a reproduction signal is obtained over two tracks. Here, if one divided portion is referred to as a sector, one track is formed per frame, so two sector numbers S _{0 to} S ₁ are assigned as shown in FIG.

It is to be noted that, generally, an area obtained by dividing one track into approximately equal parts d is referred to as a sector.

In order to realize i-time high-speed reproduction, the head straddles i tracks, so that one track reproduces an area of 1 / i. Then, assuming that the highest high-speed reproduction speed is i _max , i _max ≦
Set to the relationship of d. Then, the sector names are S _{0 to} S _d-1.
Expressed by

Next, the relationship between a refresh block and a sector will be described. When recording the refresh block G _n of the frame number n in one track T _n, G _n (0)
.. S ₀ , G _n (1)... S ₁ are recorded.

Here, assuming that the number of refresh blocks included in one sector is evenly arranged, the number of refresh blocks included in one sector is as follows. That is, 1
Assuming that the number of refresh blocks per frame is b, the number of tracks for recording the b refresh blocks is c, the number of track divisions is d, and the number of refresh blocks within one sector is e, e = b / c × d. Become. That is, e = 240/1 × 2 = 120.

In FIG. 23, the head traces of X _{0 to} X ₄ represent the head trajectory at 2 × speed. That is, in the head trace of X ₀ , the sector S ₀ of the track T ₀ (refresh block G ₀ (0)) and the sector S ₁ of the track T ₁ (refresh block G _0
1 indicates that (1)) can be reproduced.

Since the recording capacity that can be recorded in the sectors S ₀ and S ₁ of the recording medium on the tape is fixed,
Within this recording capacity, the refresh block G _n (0),
The generated code amount of G _n (1) must be suppressed.

In FIGS. 21A and 21B, the horizontal axis indicates the refresh block number. In the present embodiment, the refresh block number of sector 0 and the refresh block number of sector 1 are shown in order to record a refresh block of one frame in two sectors. In this example, 1
20 refresh blocks, the recording code amount of one sector α /
Do not exceed 2.

The ordinate of FIG. 21 indicates the code amount of the refresh block. The maximum code amount is α / 2 as described above.
Set to. Here, it is assumed that α / 2 = 250 k bits. In FIG. 21A, a solid line A is a target low-band code amount of the refresh block, and the generated code amount is controlled so as not to exceed this line. Since the solid line A is an example for control, it does not need to be a straight line, and what is necessary is to suppress the generated code amount per sector to α / 2.

The polygonal line B is a line showing an example of a change in the accumulated amount of low-frequency code of the refresh block. This shows an output signal of the refresh block low band code amount calculation circuit 53. The division level is determined so as not to exceed the refresh block low band target code amount A.

Since the output signal of each refresh block code amount detection circuit 52 is input to the refresh block division level setting circuit 54, the refresh block target code amount is compared with the refresh block low band code accumulated code amount B. It is possible to select a division table so as not to exceed A.

Here, in the case where the low-frequency code and the high-frequency code are divided as shown in FIG. 16, a position for separating the zigzag scan coefficients for determining the division level is determined when sequentially scanning.

This will be described in detail with reference to FIG.

FIG. 21 (b) is an enlarged view of the horizontal axis of FIG. 21 (a). Refresh block number 80 to 8
How to determine the division level into 1 will be described with reference to FIG.

First, it is assumed that the code amount up to the refresh block number 80 has been calculated by the refresh block low band code amount calculation circuit 60, and the code amount is indicated by C in FIG. 21B. It is also assumed that the target code amount is determined by the refresh block number, and the refresh block number 81 has the code amount indicated by D in FIG. 21B.

Since the signal of the coefficient obtained by DCT of the refresh block is input to the refresh division level setting circuit 54 as the output signal of each refresh block code amount detection circuit 52, the generated code amount can be calculated.

Zigzag scan numbers ω = 6, 7, 8, 9 corresponding to refresh block division levels (FIG. 8)
Assuming that the code amount on the low-frequency side becomes E to H in FIG. 21B, the code amount ω = 7 of the generated code of F which does not exceed the target value D is selected.

[0201] Thus, since the low-frequency code amount of the refresh block can be controlled to the code amount included in the trick sector, high image quality can be obtained even during high-speed reproduction.

The structure of each block when the code of the refresh block is divided into a reduced component and a high-frequency component as shown in FIG. 19 will be described with reference to FIG.

FIG. 24A shows codes in one super block. That is, the luminance signal blocks Y ₀ to
Block U of Y ₇ and the chrominance signal, the V indicates the vertical axis indicates the coefficient of the DCT when the zigzag scanning in the horizontal axis. The numbers shown below the horizontal axis correspond to the numbers of the zigzag scan in FIG. The same applies to the horizontal axes in FIGS. 24 (b) to (e).

When the data is stored in the VCR, the reduced component and the high frequency component of the refresh block are divided and recorded.

A method of dividing a refresh block in the case of a DigiCipher will be described.
FIGS. 24B to 24E show examples when the refresh block shown in FIG. 24A is divided.

FIGS. 24B and 24C show a method of dividing the color signals U and V. FIG.

The color signal of the DigiCipher refresh block is shown in FIG.
As shown in (1), the coefficient is divided into a low-frequency component coefficient C _LF (U _LF , V _LF ) and a high-frequency component coefficient C _HF (U _HF , V _HF ).

As described above, the division is performed such that the code amount of the low band is kept within a predetermined code amount. Thus, the DCT zigzag scan coefficient is determined so as to fall within a predetermined code amount.

FIGS. 24D and 24E show luminance signals Y ₀ to Y ₀ .
₇ shows a division method of Y7. In the DigiCipher, the DC component Y _DC of the luminance signal is converted into a DPCM by collecting DC coefficients of eight luminance signals DCT in the super block. Therefore, Y _DC is used as it is as a code on the low frequency component side.

The AC component Y _AC of the block of the luminance signals Y _{0 to} Y ₇ is divided into a low-frequency code and a high-frequency code. The division method is determined based on the code amount of the low frequency band similarly to the color signal. As a result, the code Y _LF of the low frequency component and the code Y _{HF of the} high frequency component are obtained.

FIGS. 25A and 25B are diagrams showing the division of codes in macroblock units. Within a macroblock, there are refresh blocks and non-refresh blocks. Of these, the above-described code division is performed only for the refresh block, and the DC of the luminance signal as a low-frequency component is obtained.
The low-frequency code Y of the component Y _DC and the AC component of the luminance signal
_{0LF ~Y 7LF} and produce the luminance signal high-pass code Y _0HF ~Y _7HF a high-frequency component.

[0212] Then, a low frequency block to the head traces when the special reproduction, a DC code Y _DC luminance signal of the refresh block, the luminance signal low band code Y _0LF ~Y _7LF and the chrominance signal low-frequency encoding U _LF, V _LF Consists of

The non-trick blocks that the head does not trace during special reproduction are the non-refresh block and the high-frequency code Y _0HF of the luminance signal of the refresh block.
Highband code U _HF color signals to Y _{7F H,} consisting of V _HF.

FIGS. 26 to 29 show an example of a method of arranging trick blocks and non-trick blocks in a bit stream.
It is shown using.

FIGS. 26 and 27 show trick blocks.
This will be described with reference to FIG.

First, a trick block is defined.

Trick block: A block in which a head is traced and reproduced in high-speed reproduction on a recording medium such as a VCR. The trick block includes a plurality of low-frequency component refresh blocks and overhead data thereof.

FIG. 26 shows an example of a trick block. In this example, a case where five refresh blocks (low-frequency blocks) of low-frequency components are put in a trick block is shown.

FIG. 27 shows an arrangement of five low-frequency blocks.

In the conventional example, _two columns GO ₀ , GO ₁ , GO ₂ , and GO ₃ included in the vertical four columns of the screen (shown in FIG. 26)
Refresh is applied to 40 super blocks. Thus, there are 240 low frequency blocks per frame.

Of these, five low-frequency blocks adjacent in the vertical direction are collectively referred to as a trick block. FIG.
6 and FIG. 27 are numbered 0 to 4 in order to show an example of the order of the five low-frequency blocks.

In order to indicate the position of a trick block in the vertical direction, a vertical ID (VID) is included in overhead data. The positional relationship of this vertical ID on the screen is shown at the left end of FIG.

Further, as will be described later, trick block address codes are set from 0 to 15 as shown in FIG.

The vertical ID changes in the order of VID = 0 to 2,
In this example, three sets of five low-frequency refresh blocks (VID = 0 to 2) are combined into one trick block.

FIG. 27 shows the bit stream structure of the trick block.

The overhead data of the trick block is composed of a vertical ID, a trick block code length, a quantization level of each low frequency block, and a code indicating field / frame discrimination.

When the vertical ID is set to a predetermined number, the code of the frame count is selected.

In the conventional example, a code indicating the position on the refresh screen is required to refresh the area of 1/11 per frame, and this is the frame count.

Further, variable length codes of five low frequency blocks are inserted into trick blocks.

Next, the non-trick block shown in FIG.
This will be described with reference to FIG.

A non-trick block is defined.

Non-trick block: A block that is not used to compose a reproduced image during high-speed reproduction on a recording medium such as a VCR.

The non-trick block is composed of a high-frequency component of one refresh block, ten non-refresh blocks, and overhead data thereof.

FIG. 28 shows the configuration of a non-trick block.

The overhead data includes channel I
D, non-trick block code length, quantization level, field / frame discrimination, PCM / DPCM discrimination, and motion vector.

The difference between the conventional macro block and the non-trick block is that the refresh block is composed of a high-frequency component code.

FIG. 29 is a diagram showing bit stream structures of trick blocks and non-trick blocks.

The non-trick block 55 in FIG.
The structure shown in FIG. Here, NTBA (Non
Trick Block Address) indicates an address code of a non-trick block, and indicates that NTBA = ₁ to n1 are sequentially transmitted.

After transmitting the non-trick block, the trick block 56 is transmitted.

The trick block 56 has the structure shown in FIG. Here, TBA (Trick Block Addr
ess) is the address code of the trick block on the screen, and FIG. 29 shows that TBA = 0 to 15 are sequentially transmitted.

After transmitting the trick block 56, N
Non-trick block 57 from TBA = n ₁ +1 to n ₂
Is sent.

This bit stream corresponds to the output signal of the memory 48 of the code arrangement circuit 45 in FIG.

[0243] will be described with reference to FIG. 30 with respect to setting of the changeover points NTBA = n ₁ of the non-trick blocks and the trick blocks.

The point when arranging the trick block is to record the trick block in a trick sector to be reproduced during high-speed reproduction.

Here, a case will be described in which the average generated code amount per frame is recorded on one track to realize a double speed high reproduction speed.

FIG. 31 shows recording tracks and head traces and recording positions of trick blocks G _{0 to} G ₁₀ at 2 × speed. Sector S ₀ of the track T _0, records the trick block G _0, to the sector S ₁ of the track T ₁ recorded trick block G _1.

FIG. 30 shows a VCR data multiplex format in this case.

FIG. 27 is a diagram showing transmission data of frame 1 and frame 2.

The horizontal axis corresponds to a period of one unit described later, and the vertical axis corresponds to the number of units to be recorded on one track.

Here, since the case where one frame is recorded on one track is described, the vertical axis also corresponds to one frame.

Here, a broken line drawn in the transmission code of each frame indicates a switching point of the sector.

In the bit stream structure shown in FIG.
The method of determining A = n ₁ and NTBA = n ₂ is that the trick blocks G ₀ and G ₁ are assigned to the sector S of the track T ₀ .
₀ and NT as placed in a sector S ₁ of the track T ₁
Determine BA.

As described above, after arranging the codes of the non-trick block and the trick block, as shown in FIG. 30, the sync signal, the non-trick / trick block position, the non-trick / trick block address code, other additional information, An error correction code is added and recorded.

The VCR has jitter due to uneven rotation of the cylinder, track jump at the time of special reproduction, and the like.
It is necessary to add a sync signal at a predetermined interval.

Here, one period of the sync signal is referred to as one unit.

Definition of words Unit: One period of sync in transmission data to VCR In this period, sync, additional information, non-trick / trick block position code (NTBP / TBP), non-trick / trick block address code (NTBA /
TBA) and codes of non-trick blocks or trick blocks, error correction codes, and the like.

FIG. 32 is an enlarged view of the VCR data multiplex format.

First, an example of a non-trick / trick block area code will be described. This code represents the projection position information of each block. In one frame,
There are 240 non-trick blocks. Also, the trick block address code is as shown in FIG.
Since there are 16 codes, the projection position can be represented by using 256 codes. Here, the area codes of the non-trick block are tentatively indicated by the area codes of 0 to 239 trick blocks by 240 to 255.

Since each block is composed of a variable length code, the switching point of the block is not fixed.
Thus, the address code of the first non-trick / trick block entering each unit is placed at the end of the sync signal.

Furthermore, the starting point of this block is not fixed. Therefore, this starting point is indicated by a non-trick / trick block position code.

In the example of FIG. 32, the non-trick block address 11 of the unit number 20 is inserted as a non-trick / trick block address code after the sync, and the starting point 5 of the code of the non-trick block is set to the non-trick / trick block.
Insert and record as trick block position code.

When arranging a trick block between non-trick blocks, the trick block is inserted so that the position of the head block of the trick block is always indicated by the trick block position code.

A unit may include a plurality of trick blocks and non-trick blocks. in this case,
The position indicated by the trick block position code indicates the position of the first (non) trick block that appears. Therefore, the first block of the trick block is arranged so as to appear first in the unit. That is, T in FIG.
It is arranged as BA = 0.

The VCR data multiplex format only adds additional information such as an index.
There is no requirement for video source coding from this format. Therefore, the content of the video information is not deteriorated by this format.

The operation at the time of decoding will be described. First, the operation of the normal reproduction will be described.

In FIG. 33, the input terminal 58 has a VC
A signal obtained by subjecting a reproduced signal from R to reproduction waveform equalization, error correction, and the like is input.

The unit sync detection circuit 59 detects a sync signal inserted in each unit. This eliminates the effects of VTR jitter and the like. Further, at the time of special reproduction such as slow or high-speed reproduction, by detecting this sync signal, each unit is grasped, and the ID or (Non
-) Trick Block Position, (Non-) Trick Brock Addre
Detect ss signal. In the (non) trick block position detection circuit 60, the VCR Data Multiplex Format
The (Non-) Trick Block Position signal is used to determine the starting point of the (non) trick block.

The (non) trick block address detection circuit 61 grasps the projection position of the (non) trick block on the screen from the (Non-) Trick Brock Address signal of the VCR Data Multiplex Format.

The (non) trick block separation circuit 62 receives a signal expressed in the VCR Data Multiplex Format, separates the code of the trick block from the code of the non-trick block, and outputs the separated signal.

For this separation, (Non-) Trick Block Posi
Use the Option signal and the (Non-) Trick BrockAddress signal.

The code of the trick block has the bit stream structure shown in FIG.

The trick block overhead data detection circuit 63 detects a vertical ID, a quantization level, a field / frame discrimination signal, a trick block code table, and a frame count.

In the trick block memory 64, FIG.
The variable length code of the trick block shown in FIG.

At the time of writing to the memory 64, the address generation circuit 65 outputs the Trick Brock Address signal and the vertical I
D. Generate address using trick block code length frame count.

When reading data from the memory 64, the address generation circuit 65 uses a signal obtained by feeding back a signal from the variable-length code decoding circuit 66 in addition to the signal used for writing. The decoding of the variable length code and the bit stream are sequentially compared with the Huffman table to determine the code breakpoint. Therefore, decoding is performed while feeding back the signal of the variable length code decoding circuit 66.

The trick block code subjected to the variable length decoding is once stored in the memory 67. At the time of normal reproduction, the phase is matched with the address of the code of the non-trick block.

The code of the non-trick block output from the (non-trick) block separation circuit 62 is input to the non-trick block overhead data detection circuit 68 and the non-trick block memory 69.

The non-trick block overhead data detection circuit 68 detects non-trick block overhead data, that is, channel ID, non-trick block code length, quantization level, field / frame discrimination, PCM / DPCM discrimination, and motion vector detection. Do.

[0279] The non-trick block memory 69 is shown in FIG.
Is stored.

When writing to the memory 69, the address generating circuit 70 generates an address using a non-Trick Block Address signal, a non-trick block code length, a channel ID, and a frame count reproduced from a trick block.

When reading data from the memory 69, the address generating circuit 70 uses a signal fed back from the signal of the variable length code decoding circuit 71 in addition to the signal used for writing.

The output signal of variable length code decoding circuit 71 is input to refresh block separation circuit 72.

The non-trick block has the configuration of the non-trick block shown in FIG. Therefore, the refresh high band code and the non-refresh block are separated by counting the EOB.

The refresh high band code output from the refresh block separation circuit 72 and the refresh low band code output from the memory 67 are input to the refresh block low band / high band code combining circuit 73. To perform this operation, memory address generating circuit 74 generates a necessary address.

This synthesis is shown in FIGS. 24 (c) and (b).
The operations (e) to (d) are performed.

That is, in the color signal blocks U and V, the low-frequency code and the high-frequency code are sequentially arranged according to the zigzag scan order.

In the luminance signal blocks Y _{0 to} Y ₇ ,
The DC code, the low-frequency code, and the high-frequency code are sequentially arranged according to the zigzag scan order.

Thus, the code of the refresh block is formed.

The macroblock construction circuit 75 combines the non-refresh block separated by the refresh block separation circuit 72 and the refresh block output from the refresh block low / high band code synthesis circuit 73.

This operation is the operation shown in FIG. 25 (b) → (a).

That is, a refresh block and a non-refresh block are sequentially arranged to form a macro block.

Also, the overhead data reconstruction circuit 7
In step 6, the overhead data is rearranged from the output of the trick block overhead data detection circuit 63 and the output of the non-trick block overhead data detection circuit 68.

Output signals of the overhead data reconfiguration circuit 76 are input to the circuit shown in FIG.

The operations of the inverse quantization circuit 77, the inverse DCT circuit 78, the motion compensation circuit 79, the YC separation circuit 80, and the frame delay circuit 81 are the same as those in the conventional operation.

At the time of high-speed reproduction, the reading of the memory 67 is controlled by the memory address generation circuit 74 so that the arrangement of the trick blocks read from the tape and the arrangement of the macro blocks at the time of outputting the video are matched.

The macro block of the conventional example is composed of 11 super blocks in the horizontal direction of the screen. Also, this is because the trick blocks are composed of refresh blocks and are arranged in one column in the vertical direction.

If the content of the video signal is not updated, a skip signal is generated by the skip signal generation circuit 82, and the frame delay circuit 81 and the YC separation circuit 80 directly output the data accumulated in the past.

In order to perform this operation, control signal of memory address generating circuit 74 is input to skip signal generating circuit 82.

For overhead data, the output signal of the trick block overhead data detection circuit 63 is rearranged by the overhead data reconfiguration circuit 76 and transmitted.

With the above operation, trick blocks can be reproduced during high-speed reproduction, and a reproduced image can be formed.

In this embodiment, the case where the refresh block is divided into the low-frequency component and the high-frequency component as shown in FIG. 25 has been described. However, the generated code amount of the refresh block is determined by a predetermined amount determined by the recording medium. When the value is set to the value, the refresh block need not be divided.

In this case, the low-frequency block of the trick block shown in FIG. 27 is constituted by a refresh block.
The high frequency block 0 of the eight non-trick blocks is deleted, and the non-trick blocks are constituted by non-refresh blocks.

In this case, the decoder of FIG. 33 does not need to use the refresh block separating circuit 72 and the refresh block low band / high band code synthesizing circuit 73, so that the output signal of the variable length code decoding circuit 71 and the memory By inputting the output signal of 67 to the macroblock construction circuit 75, the effects of the present invention can be realized.

[0304] The present invention is not limited to the above embodiments, but can be implemented with various modifications without departing from the spirit and scope of the invention.

[0305]

As described in detail above, according to the present invention,
It is possible to provide an extremely good band compression signal processing device that can easily obtain a good reproduced image at the time of high-speed reproduction.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a band compression signal processing apparatus according to the present invention.

FIG. 2 is a timing chart shown for explaining the operation of the embodiment.

FIG. 3 is a diagram showing a relationship between refresh blocks and non-refresh blocks of frame numbers F ₅ and F _{6 in} the embodiment.

FIG. 4 is a view showing a track pattern in the embodiment.

FIG. 5 is a diagram showing a head trace trajectory during double-speed playback in the embodiment.

FIG. 6 is an exemplary view showing reproducible refresh blocks of frames 1 to 8 in the embodiment.

FIG. 7 is a view showing refreshable refresh blocks of frames 9 to 11 and refresh blocks in which 11 frames are stored in the embodiment.

FIG. 8 is a diagram showing a scan order when zigzag scanning DCT coefficients.

FIG. 9 is a diagram showing an example of a quantization table.

FIG. 10 is a diagram showing an example of a weighting table.

FIG. 11 is a diagram showing an example in which the weighting table is converted into the number of bits.

FIG. 12 is a diagram showing the number of bits generated by a quantization table.

FIG. 13 is a diagram showing the number of bits generated by a quantization table.

FIG. 14 is a block diagram showing details of a main part of the embodiment.

FIG. 15 is a diagram showing division of codes in the embodiment.

FIG. 16 is a diagram showing division of codes in the embodiment.

FIG. 17 is a diagram showing division of codes in the embodiment.

FIG. 18 is a view showing division of codes in the embodiment.

FIG. 19 is a block diagram showing another embodiment of the present invention.

FIG. 20 is a diagram showing a code amount according to another embodiment.

FIG. 21 is a view for explaining the operation of the other embodiment.

FIG. 22 is a diagram showing a refresh block according to another embodiment.

FIG. 23 is a diagram showing a track pattern according to another embodiment.

FIG. 24 is a diagram showing a code of a trick block according to another embodiment.

FIG. 25 is a diagram showing codes of trick blocks according to another embodiment.

FIG. 26 is a diagram showing an address code of a trick block according to another embodiment.

FIG. 27 is a diagram showing a bit stream of a trick block according to another embodiment.

FIG. 28 is a diagram showing a bit stream of a non-trick block according to another embodiment.

FIG. 29 is a diagram showing a bit stream of a (non) trick block according to another embodiment.

FIG. 30 is a diagram showing transmission data of another embodiment.

FIG. 31 is a diagram showing a track pattern according to another embodiment.

FIG. 32 is a diagram showing a structure of transmission data according to another embodiment.

FIG. 33 is a block diagram showing a configuration example of a decoder according to the present invention.

FIG. 34 is a diagram showing an overhead data processing circuit of the decoder.

FIG. 35 is a block diagram showing a conventional band compression system.

FIG. 36 is a diagram showing a format of a signal transmitted from the conventional system.

FIG. 37 is a view showing reproducible refresh blocks of frames 1 to 8 during normal reproduction in the conventional system.

FIG. 38 is a diagram showing a reproducible refresh block of frames 9 to 11 and a refresh block in which 11 frames are accumulated during normal reproduction in the conventional system.

FIG. 39 is a view showing a track pattern in the conventional system.

FIG. 40 is a diagram showing a head trace trajectory at the time of double speed reproduction in the same conventional system.

FIG. 41 is a diagram showing reproducible refresh blocks of frames 1 to 8 during double speed reproduction in the conventional system.

FIG. 42 is a diagram showing reproducible refresh blocks of frames 9 to 11 and refresh blocks in which 11 frames are accumulated in double speed reproduction in the conventional system.

[Explanation of symbols]

11 input terminal, 12 subtraction circuit, 13 motion estimation circuit, 14 DCT circuit, 15 quantization circuit, 16 variable length coding circuit, 17 FIFO circuit, 18 output terminal,
19: inverse quantization circuit, 20: inverse DCT circuit, 21: addition circuit, 22: frame delay circuit, 23: motion compensation circuit,
24, 25 switch, 26 magnetic tape, 27 input terminal, 28 SYNC signal detection circuit, 29 track formation signal generation circuit, 30 rotating drum, 31 track formation control circuit, 32, 33 input terminal, 34, 35 ... decimator, 36 ... input terminal, 37 ... multiplexer, 38
... Track, 39 ... code replacement circuit, 40 ... refresh block control circuit, 41 ... index insertion circuit
42 ... index generation circuit, 43 ... multiplexer,
44: zigzag scan circuit, 45: code arrangement circuit, 4
Reference numeral 6: refresh block separation circuit, 47: variable length coding circuit, 48: memory, 49: refresh block code division circuit, 50, 51: variable length coding circuit, 52: refresh code amount detection circuit, 53: refresh Block low-frequency code amount calculation circuit, 54: refresh block division level setting circuit, 55: non-trick block, 56: trick block, 57: non-trick block, 58: input terminal, 59: unit sync detection circuit,
60 ... (non) trick block position detection circuit, 6
1 ... (non) trick block address detection circuit, 62 ...
(Non) trick block separation circuit, 63: trick block overhead data detection circuit, 64: trick block memory, 65: address generation circuit, 66: variable length code decoding circuit, 67: memory, 68: non-trick block overhead data detection Circuit, 69: non-trick block memory, 70: address generation circuit, 71: variable length code decoding circuit, 72: refresh block separation circuit, 73: refresh block low / high band code synthesis circuit, 74: memory address generation circuit , 75 macroblock construction circuit, 76 overhead data reconstruction circuit, 77 inverse quantization circuit, 78 inverse DCT circuit, 79
Motion compensation circuit, 80: YC separation circuit, 81: Frame delay circuit, 82: Skip signal generation circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/76-5/956 H04N ^7/ 24-7/68 G11B 20/10-20/12

Claims (6)

(57) [Claims] 1. A frame obtained by forming a image area (a is a positive integer) in a video signal of one screen and performing an intra-frame encoding process on the video signal using information in the frame. An intra-processed signal and an inter-frame processed signal that has been subjected to inter-frame encoding using the difference information between frames are created. After the intra-frame encoding, the inter-frame encoding is performed. A band compression unit that adaptively repeats a processing method according to a motion evaluation of an input video signal; and b frames out of the a regions in each of f frames (f is an integer of f ≧ 2). Refresh coding processing means for periodically performing the intra-frame coding process on a signal in an image area; combining a plurality of blocks subjected to the refresh coding process to form a trick block; No. treatment while positioned between the non-trick block not subjected to the band compression signal processing apparatus characterized by the addition to the overhead data a code indicating a code length of the trick block. 2. An intra-frame coded signal obtained by performing an intra-frame coding process on an input video signal using information in a frame and an inter-frame coding process performed by using difference information between frames. Create an inter-frame coded signal,
A signal processing unit that adaptively repeats a signal processing method for performing the inter-frame encoding process after the intra-frame encoding process according to a motion evaluation of the input video signal; Recording means for continuously recording an encoded signal and an inter-frame encoded signal on a recording medium; and continuously recording the intra-frame encoded signal and the inter-frame encoded signal from the recording medium using the recording / reproducing element. Reproducing means for reproducing at the time of high-speed reproduction, the recording / reproducing element reproduces only a mechanically restricted area on the recording medium; and The intra-frame coded signal is recorded in a possible mechanically restricted area on the recording medium, and the variable-length data stream output from the signal processing unit is A data multiplex format in which synchronization signals of a fixed length are arranged at selected time intervals, wherein the signal processing unit arranges an index at a rear portion of each of the synchronization signals, and the variable at a rear portion of each index. A band compression signal processing apparatus, wherein corresponding segments of a long data stream are arranged, and each index indicates the content of variable length data included in the corresponding segment of the variable length data stream. 3. The data multiplex format includes an identification code for identifying whether a type of a block located at the rear of each of the synchronization signals is a refresh block or a non-refresh block. The band compression signal processing device according to claim 2. 4. The band compression signal processing apparatus according to claim 2, wherein the data multiplex format includes a number indicating a frame number assigned to a block located at the rear of each of the synchronization signals. 5. The band compression signal according to claim 2, wherein the data multiplex format includes a code indicating a display position of a refresh block or a non-refresh block located at the rear of each of the synchronization signals. Processing equipment. 6. The band compression signal processing apparatus according to claim 2, wherein the data multiplex format includes information indicating a start position of the index.