JP3406884B2 - Integrated circuit device and liquid crystal display device using the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device in which electronic circuits such as a large number of amplifier circuits are integrated and a liquid crystal display device, and more particularly, to an integrated circuit device in which variations in bias current between chips are reduced. The present invention relates to a liquid crystal display device using a drive circuit as an amplifier circuit.

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device and a liquid crystal display device in which electronic circuits such as a large number of amplifier circuits are integrated, and more particularly, to an integrated circuit device in which variations in bias current between chips are reduced and to drive the same. The present invention relates to a liquid crystal display device used as an amplifier circuit of a circuit.

A display driving circuit in a conventional liquid crystal display device uses a digital image signal (hereinafter, RG).
B signal), a first memory element having the same number as the number of pixels required for one horizontal line, a shift register for transferring a timing pulse for storing the RGB signal, and one horizontal signal for the RGB signal stored in the memory element. A second storage element that further stores in a cycle of a period, a D / A converter (DAC) group that converts an RGB signal of one horizontal line stored in the second storage element into an analog value, and this DAC group It is composed of an amplifier circuit group for inputting RGB signals converted into analog values and driving signal lines and liquid crystal cells of a liquid crystal display panel. The liquid crystal cell to which the voltage of the RBG signal converted into the analog value is applied determines the brightness of the corresponding pixel by changing the light transmittance according to the voltage value.

Here, the bias current of the amplifier circuit group is 1
It is set according to the bias signals generated by the two bias circuits. Specifically, the current Ibias generated in the bias circuit is supplied to the diode-connected transistor provided in the bias circuit, and the gate voltage of this transistor is supplied to each amplifier circuit of the amplifier circuit group.

In each amplifier circuit, the gate voltage of the transistor is applied to the gate of the transistor of each amplifier circuit and converted into a current. This converted current is used as the bias current. That is, the transistor of the bias circuit and the transistor of the amplification circuit form a current mirror circuit, and the transistor of the bias circuit serves as the input side transistor of the current mirror circuit and the transistor of the amplification circuit serves as the output side transistor of the current mirror circuit.

Depending on the specifications of the liquid crystal display device,
The number of amplifying circuits included in the amplifying circuit group is very large, for example, 3000, which uses an amorphous silicon TFT in a liquid crystal digital panel. Therefore,
Since it is difficult to configure the amplifier circuit group with one chip when integrated into an integrated circuit, it is common to configure with a plurality of chips. In this case, the bias circuit is also provided for each chip. Generally, about 300 amplifier circuits are incorporated in one chip.

These amplifier circuits are integrated in a row in a chip, and the input side transistors (transistors of the bias circuit) of the current mirror circuit are arranged at either end of the row of this amplifier circuit. . For example, the input side transistor is arranged next to the amplifier circuit at the left end.

MOS transistors are usually used as the transistors of the bias circuit and the transistors of the amplifier circuit. The threshold voltage (Vt) of a MOS transistor generally varies within a certain range even between different chips and the same chip. Here, even if the threshold voltage of the transistors in the amplifier circuit varies, when the number of amplifier circuits in one chip is large, such as 300, there is generally no great difference in the degree of variation in the transistors in the amplifier circuit between different chips.

However, if the threshold voltage of the diode-connected transistor in the bias circuit varies between chips, the bias current flowing in the transistor in the amplifier circuit varies according to this variation, which results in a difference in current consumption between chips. And appear as a difference in characteristics. The difference in current consumption between chips has an important influence on the power supply design of the liquid crystal display device and is not preferable. Further, variations in characteristics between chips cause deterioration of image quality of the liquid crystal display device.

[0010]

As described above, in the bias circuit configuration in the amplifier circuit used in the conventional liquid crystal display device, the bias currents flowing in a large number of transistors of the amplifier circuit in the chip vary among the chips. As a result, there is a problem in that the current consumption and characteristics differ among the chips.

According to the present invention, the variation in bias current between chips is small, and the difference in current consumption and characteristics between chips is reduced, and an integrated circuit device using the same for a drive circuit facilitates design and also reduces image quality. An object is to provide a reduced liquid crystal display device.

[0012]

The present invention comprises a plurality of electronic circuits and an input current for setting a bias current,
A current consisting of a plurality of diode-connected input side transistors distributed in the plurality of electronic circuits and a plurality of output transistors each supplying an output current corresponding to the input current to the plurality of electronic circuits as a bias current. Provided is an integrated circuit device in which a mirror circuit is integrated in one chip.

According to the present invention, a plurality of electronic circuits are integrated in a chip in the form of an array, and the input side transistors are every L (L is a positive number of 1 or more) electronic circuits of the plurality of electronic circuit columns. It is distributed and arranged inside.

According to the present invention, the plurality of electronic circuits are integrated in an array in a chip, and among the diode-connected input side transistors in the plurality of electronic circuits, M (M) rows of the plurality of electronic circuits are arranged. Is used by connecting only P pieces (P is a positive number of P ≦ M) for every input side transistor of 1 or more) so as to form a current mirror circuit together with the output side transistor.

As described above, the integrated circuit device of the present invention is provided with a plurality of diode-connected input-side transistors which form a current mirror circuit together with an output-side transistor which generates a bias current in each electronic circuit. By arranging in a distributed manner, the average value of the variations in the threshold voltage of the input side transistor for each chip becomes substantially equal among the chips. Therefore, the matching between the input side transistor and the output side transistor is improved, and the current consumption and the difference in characteristics between chips are reduced.

According to the present invention, a plurality of pixels, a liquid crystal display in which a signal line for selectively applying an image signal to each pixel and a scanning line intersecting with the signal line are arranged, and the image signal is amplified to amplify the image signal. The amplification circuit group is configured to include an amplification circuit group that supplies the signal line, and is configured by a drive circuit that drives the signal line and a selection circuit that selects the scanning line.
Integrated in a plurality of chips in a predetermined number of units, each of the chips receives an input current for setting a bias current, a plurality of diode-connected input side transistors, and an output corresponding to the input current. Integrating a current mirror circuit consisting of a plurality of output transistors that respectively supply a current as a bias current to the amplifier circuit,
The plurality of input-side transistors provide a liquid crystal display device in which the plurality of input-side transistors are dispersedly arranged in the plurality of amplifier circuits incorporated in each of the chips.

As described above, when the amplifier circuit group in the drive circuit of the liquid crystal display device is configured by using the integrated circuit device according to the present invention, the difference in the current consumption and the characteristics between the chips is small, so that the design of the power supply is particularly easy. In addition, it is possible to realize a liquid crystal display device in which image quality deterioration due to characteristic variations is small.

According to the present invention, a plurality of output transistors for receiving a set voltage for setting a bias current and supplying an output current to the electronic circuit as a bias current, and distributedly arranged in the plurality of electronic circuits. An integrated circuit including a plurality of monitoring transistors that receive the set voltage and output a monitor current, and an amplifier that amplifies a voltage according to a difference between the monitor current and the set input current and outputs the set voltage Provide a device.

According to the present invention, a plurality of pixels, a liquid crystal display in which a signal line for selectively applying an image signal to each pixel and a scanning line intersecting with the signal line are arranged, and an image signal is amplified. The amplifier circuit group that supplies the signal lines, a drive circuit that drives the signal lines, and a selection circuit that selects the scanning lines are included in the plurality of chips in a predetermined number of units. Integrated, each of the chips is
A plurality of output transistors that receive a set voltage for setting a bias current and supply an output current to the amplifier circuit as a bias current, and a plurality of output transistors that are arranged in a distributed manner in the plurality of amplifier circuits and receive the set voltage. Provided is a liquid crystal display device including a plurality of monitoring transistors that output a monitoring current and an amplifier that amplifies a voltage according to a difference between the monitoring current and a set input current and outputs the set voltage.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a liquid crystal display device to which the present invention is applied. The liquid crystal display device includes a liquid crystal display panel 10, a liquid crystal display drive circuit 12 for supplying an image signal to a signal line, and a scanning line selection circuit 13 for selectively driving a scanning line. The liquid crystal display panel 10 is composed of a large number of liquid crystal cells 11 arranged in a matrix, a plurality of signal lines 14 to which an image signal is supplied, and a plurality of scanning lines 15 intersecting these signal lines 14. It

The display drive circuit 12 of the liquid crystal display device transfers the same number of storage elements 22 as the number of pixels required for one horizontal line for storing a digital image signal (hereinafter, RGB signal) and a timing pulse for storing the RGB signal. The shift register 21, the storage element 23 that further stores the RGB signals stored in the storage element 22 in a cycle of one horizontal period, and the R of one horizontal line stored in the storage element 23.
D / A converter (DA that converts the GB signal into an analog value
C) Group 24 and an amplifier circuit group 25 for inputting RGB signals converted into analog values by the DAC group 24 and driving the signal lines 14 and the liquid crystal cells 11 of the liquid crystal display panel. The liquid crystal cell 11 to which the voltage of the RBG signal converted into the analog value is applied changes the light transmittance according to the voltage value to determine the brightness of the corresponding pixel.

FIG. 3 shows an integrated circuit device having a one-chip structure according to the first embodiment of the present invention, which is used in the above liquid crystal display device. This integrated circuit device has a plurality (N) of amplifier circuits 31 to 3N. Amplifier circuit 31-
3N constitutes, for example, a part of the amplifier circuit group 25 in FIG. 2 included in the liquid crystal display drive circuit 12 of the liquid crystal display device shown in FIG. 1, and is linear in the chip along the horizontal direction of the drawing. Are arranged side by side to form a line.

The amplifier circuits 31 to 3N are respectively provided with bias current mirror circuits in which the diode-connected transistors MR1 to MRN are used as input side transistors and the transistors M1 to MN are used as output side transistors. There is. These transistors MR1 to MRN and M1 to MN are composed of MOS transistors in this example.

The gates and drains of the input-side transistors MR1 to MRN are connected to each other, that is, are diode-connected, and are further connected to a line to which a bias current setting current I _bias is supplied, that is, a bias current setting line BL. The sources of the input side transistors MR1 to MRN are connected to the power supply line Vss. The gates of the output side transistors M1 to MN are connected to the input side transistor MR.
1 to MRN gates and drains, that is, connected to the bias current setting line BL, and the source is the power supply line Vs.
connected to s. Further, output side transistors M1 to M
The drain of N is connected to the circuit that receives the bias current in the amplifier circuits 11 to 1N.

The present embodiment is characterized in that the input side transistors MR1 to MRN in the current mirror circuit forming the bias circuit as described above are arranged in a distributed manner in the amplifier circuits 31 to 3N. That is, in the present embodiment, the bias current setting current Ibias from the bias current setting line BL is input to the transistors MR1 to MRN of the N amplifier circuits 31 to 3N. These input side transistors MR1 to MRN are arranged close to the output side transistors M1 to MN that generate the bias currents of the amplifier circuits 31 to 3N. That is, as shown in FIG. 4, the input side transistor MR is arranged close to the output side transistor M. When the circuit pattern of FIG. 4 constitutes a circuit pattern for all of the amplifier circuits 31 to 3N, a plurality of circuit patterns each showing the circuit pattern of FIG. 4 are connected in a line as shown in FIG.

With the configuration of this embodiment as described above, the conventional problems can be solved as follows.

The gate-source voltage of each of the diode-connected input side transistors MR1 to MRN is
The value is close to the average value of the gate-source voltage of each of the transistors MR1 to MRN when a current of Ibias / N flows in each of the transistors MR1 to MRN.

Here, the input side transistors MR1 to MR
The variation in the threshold voltage (V _t ) of N is ΔV _Ri, and the variation in the threshold voltage of the output transistors M1 to MN is ΔV _Ri.
i . At this time, the statistical expected value of [Delta] V _Ri is zero, the actual average value of the [Delta] V _Ri also takes a value close to the statistical expectation, that is, a value close to zero. Therefore, the threshold voltage of the input side transistors MR1 to MRN, that is, the gate
It is possible to reduce variations in the source-to-source voltage between chips. On the other hand, there is no great difference between the chips in the variation ΔV _i of the threshold voltage of the output side transistors M1 to MN.
Therefore, it is possible to reduce the difference in the consumption current between the chips of the amplifier circuits 31 to 3N and the difference in the characteristics between the chips of the amplifier circuits 31 to 3N.

The above will be further described as follows.

The drain current I _d flowing through the MOS transistor is expressed by the following equation.

I _d ∝ k (V _GS -V _t ) ^{2 (1)} where V _GS is the gate-source voltage of the MOS transistor, V _t is the threshold voltage, and k is a coefficient.

When a large number of transistors are provided,
The sum I _{d of} drain currents is expressed by the following equations (2) and (3). ΔV _i represents the variation in the threshold voltage V _t .

[0033]

[Equation 1]

Can be approximated by Therefore, the sum I _{d of} drain currents is almost constant. Similarly, considering the bias current I _b, the bias current I _b is expressed by the following equation (5).

I _b ∝ k (V _GS −V _t + ΔV _R ) ² (5) When there are a large number of MOS transistors, the bias current I
_b is expressed by the following equation (6). However, ΔV _{R i} represents the variation in the threshold voltage of the transistor MR _j .

[0036]

[Equation 2]

Variation in threshold voltage ΔV_{R i}Is a transistor
As the number of increases, it becomes statistically close to zero. Therefore, the second
The term can be considered statistically zero. Also, ΣΔV_Rj ²Is Σ (VGS
-Vt) ²It is so small compared to that it can be ignored. Therefore,
Bias current I_bIs (V_GS-V_t) ²And is effectively V
_GSDoes not change. That is, the predetermined bias current Ib
If you add multiple transistors connected in parallel,
Even if the Vt of the transistor varies,
There will be no variation.

As described above, according to this embodiment, it is possible to reduce the difference in current consumption and the difference in characteristics between the chips of the amplifier circuits 31 to 3N. Therefore, a chip in which these amplifier circuits 31 to 3N are integrated is used, for example, as an amplifier circuit group 2 shown in FIG.
5 to configure the liquid crystal display drive circuit 12 of the liquid crystal display device shown in FIG. 1, it is possible to reduce variations in current consumption and characteristics among the integrated liquid crystal display drive circuit 12 chips. The design, particularly the design of the power supply, can be facilitated, and the image quality deterioration due to the characteristic variation can be reduced.

Next, an integrated circuit device according to the second embodiment of the present invention will be described with reference to FIG.

In the first embodiment, as described above, the input side transistors MR1 to MRN of the current mirror circuit have a size divided by the number N of the amplifier circuits 31 to 3N in one chip. Here, since the number N of the amplifier circuits 31 to 3N often takes a large value such as 300, the input side transistors MR1 to MRN are transistors having a very small size, which is practically impossible to form. Or it can be very difficult.

The present embodiment shown in FIG. 6 is an improvement of this point, and a plurality of (N) amplifier circuits 41 to 4N arranged in a row are L in number (L is a positive value of 1 or more). The number of input side transistors MR1 to MR (N / L) is distributed and arranged in the amplifier circuit for each number (L = 2 in this embodiment). In other words, the number of divisions of the input side transistor is N /
As L, the divided input side transistors MR1 to MR1
MR (N / L) amplifier circuits 41, 43, ...
It is located at 4N.

As in the first embodiment, the gates and drains of the input side transistors MR1 to MR (N / L) are connected to the bias current setting line to which the current Ibias is supplied, and the source is connected to the power supply line Vss. It is connected.

In this way, the input side transistor M
The size of R1 to MR (N / L) is N / L as compared with the case of the first embodiment, and integration is easier.
Further, it is possible to obtain substantially the same effect as that of the first embodiment.

FIG. 7 shows the configuration of an integrated circuit device according to the third embodiment of the present invention. Of the plurality (N) of amplifier circuits 51 to 5N diode-connected transistors arranged in a row in the chip, the amplifier circuits 51 to 5N
Every M (M is a positive number greater than or equal to 1) P columns (P is
Only a positive number (P ≦ M) is used by wiring so as to form a current mirror circuit together with the output side transistor.

FIG. 7 shows an example in the case of M = 2 and P = 1. Every other amplifying circuit 51, 53, ..., 5 (N-1).
-Connected transistors MR1 and MR
2, ..., MR (N / 2) only, the drain and the gate are connected to the bias current setting line that supplies the bias current setting current Ibias, and the output side transistors M1 to M
A current mirror circuit is constructed with N. , MD (N / 2), which are diode-connected transistors in the other amplifier circuits 52, ..., 5N, have drains and gates connected to the power supply line Vss and do not form a current mirror circuit.

In this way, the structure is suitable for integration into an integrated circuit. Generally, when the same plurality of circuits are integrated, it is often the case that a circuit having one basic pattern is laid out in order to improve the layout efficiency and this is repeatedly used. In this embodiment, this is utilized to improve the layout efficiency.

That is, as shown in FIG. 8A, a basic circuit including a diode-connected transistor and a non-diode-connected transistor is shown in FIG.
N sets of basic patterns shown in (a) are prepared. These N sets of basic patterns are arranged in rows. Then, as shown in FIG. 8B, the drain and gate of the diode-connected transistor and the drain of the transistor not diode-connected in the basic circuit of FIG. Line), and the sources of both transistors are connected to the power supply line Vss (the lower line in the figure). As a result, the circuit pattern shown in FIG. 9B is formed. This circuit pattern corresponds to, for example, the input side transistor MR1 and the output side transistor M1 in FIG.

Further, as shown in FIG.
In the circuit of the basic pattern of (a), only the drains of the transistors not diode-connected are connected to the bias current setting line (the upper line in the figure), and the drains, gates and sources of the diode-connected transistors are diode-connected. The source of the non-transistor is connected to the power supply line Vss (the lower line in the figure). As a result, the circuit pattern shown in FIG. 9C is formed. This circuit pattern corresponds to, for example, the diode-connected transistor MD1 that does not form the current mirror circuit in FIG. 7 and the output side transistor M2 of the current mirror circuit.

In the case of the amplifier circuit 42 of FIG. 6, the transistor MR of FIG.
Only the bias setting line BL and the power supply line are connected.

FIG. 10 is a diagram showing the configuration of an integrated circuit device according to a fifth embodiment of the present invention, which is an array of a plurality (N) of amplifier circuits 61 to 6N arranged in a row in a chip. Input-side transistors MR1 and MR2, which are diode-connected to the current mirror circuit, are arranged at both ends. Further, similarly to the previous embodiments, the gates and drains of the transistors MR1 and MR2 are connected to the bias current setting line BL to which the current Ibias is supplied, and the sources are connected to the power supply line Vss.

According to the present embodiment, the distance between the input side transistors MR1 and MR2 forming the current mirror circuit and the output side transistors M1 to MN in the amplifier circuits 61 to 6N is shortened to improve matching between both transistors. It is possible to reduce variations in characteristics of the current mirror circuit.

Further, in this embodiment, the amplifier circuits 61 to 6N are provided.
Is present as an existing one-chip integrated circuit, there is an advantage that it can be realized only by adding the transistors MR1 and MR2 to this integrated circuit.

FIG. 11 shows the configuration of an integrated circuit device according to the sixth embodiment of the present invention. The present embodiment is an example in which a bias current mirror circuit is provided in the middle of a plurality of amplifier circuits arranged in a chip. That is, the amplifier circuit 7
, ..., 7i, 7 (i + 1), ..., 7N, between the amplifying circuit 7i and the amplifying circuit 7 (i + 1) adjacent thereto, diode-connected input side transistors MR2, MR3 of the current mirror circuit. Are arranged. Further, in the present embodiment, similarly to the fourth embodiment, the diode-connected input side transistors MR1 and MR2 of the current mirror circuit are also provided outside the amplifier circuits 71 and 7N at both ends.
Are arranged respectively.

Further, as in the above-described embodiments, the respective input side transistors MR1, MR2, MR3, M are provided.
The gate and drain of R4 are connected to the bias current setting line BL to which the current Ibias is supplied, and the source is connected to the power supply line Vss.

Next, the amplifier circuits described in the above embodiments will be described. The amplifier circuit shown in FIG. 12 includes an input amplifier stage, an output amplifier stage, and a resistor Rf. The input amplification stage is a pair of differential transistors.
transistors and the transistors Mp1 and Mp2 constituting the transistors and a current source by a transistor Mp4 which gives a tail current to the differential transistor pair.
And a current mirror circuit composed of transistors Mn1 and Mn2 in which a current input terminal and a current output terminal are connected to drains which are two output terminals of the differential transistor pair. The output amplification stage is composed of a complementary transistor pair including transistors Mp3 and Mn3. Mpx is a P-channel MOS transistor, M
nx represents an N-channel MOS transistor, respectively.

According to this amplifier circuit, the open loop frequency characteristic is improved by the resistance component Rf inserted between the output terminal of the output amplification stage (the drains of the transistors Mn3 and Mp3) and the signal output terminal OUT and the capacitive component CL. The first zero point is formed, and the phase advances at this zero point,
The phase delay due to the pole can be compensated. That is, since the phase margin, which is the difference between the phase when the gain is 1 and −180 °, can be increased, the phase compensation capacitance Cf for stabilizing the operation of the amplifier circuit is basically unnecessary, and Even when the phase compensation capacitance Cf is required, its value may be very small, and thus there is an advantage that the chip area can be reduced. Regarding this effect, US Pat. 09 / 128,414.

Here, the diode-connected transistor Mp5 and the bias current source Ib1 in FIG.
Is composed of output side transistors Mi (i = 1, 2, ..., N) of the current mirror circuit for determining the gate bias of the transistors Mp3 and MP4.

FIG. 13 shows another amplifier circuit. In the amplifier circuit shown in FIG. 12, in the case of a voltage follower configuration in which feedback is provided from the output end of the output amplifier stage (the drains of the transistors Mn3 and Mp3) to the negative-side signal input terminal IN-, as shown by the broken line, the voltage riser rises. Slew rate (slew r
ate) is determined by the current supplied from the transistor Mp3 and the value of the capacitive load CL. Since the current supplied from the transistor Mp3 is small, a sufficient slew rate cannot be obtained.

In order to improve this point, the amplifier circuit of FIG. 13 detects that the input signal voltage has changed to the positive side and increases the output current of the transistor Mp3 which supplies the bias current of the output amplifier stage. , The rising slew rate has been improved. That is, the transistors Mn4,
Mp6 detects that the input signal voltage has changed to the positive polarity, turns on the transistor Mp7 when the input signal voltage changes to the positive polarity, and determines the gate bias of the transistor Mp3 with the current supplied from the current source IL. The voltage is applied to the diode-connected transistor Mp5 that is connected to the transistor Mp3 to increase the gate bias voltage of the transistor Mp3.

Explaining in more detail, the transistor M
p6 constitutes a current source, and its gate is connected to the drain and gate of the bias current determining transistor Mp5. The gate of the transistor Mp7 is connected to the drains of the transistors Mn4 and Mp6, the source is connected to the drain and gate of the bias current determining transistor Mp5, and the drain is connected to the current source IL.

To simplify the description, the transistor M
n4 and the transistor Mn1 of the input amplification stage 2 have the same size, that is, W / L (W is the channel width of the MOS transistor, L is the channel length of the MOS transistor) is the same, and the size of the transistor Mp6 (W / L )
It is assumed that Mp6 is 0.6 times the size (W / L) Mp4 of the current source transistor Mp4 of the input amplification stage 2.

[0062] The signal input terminal IN ^+, IN ^- when the voltage applied is zero or negative while, that is, the positive side of the signal input terminal IN ⁺ voltage of the signal input terminal IN of the negative side ^- is lower than the voltage Is a transistor Mp
A current of less than half the current supplied from 4 flows, and the current of this transistor Mn1 is copied by the transistor Mn4. At this time, the current supplied from the transistor Mp6 is 0.6 times the current supplied from the transistor Mp4, and is larger than the current flowing in the transistor Mn4. Therefore, the drain voltage of the transistor Mp6 becomes high and the transistor Mp7 is turned off. Therefore, the current source I
The current supplied from L is not added to the transistor Mp5.

[0063] On the other hand, the signal input terminal IN ^+, IN ^- when the input signal voltage to be applied is equal to or larger than a predetermined positive voltage during, that is, the signal input of the positive-side of the signal input terminal IN ⁺ voltage of the negative side terminal iN ^- is higher than a predetermined value than the voltage of,
A current larger than 0.6 times the current supplied from the transistor Mp4 flows through the transistor Mn1, and the current of the transistor Mn1 is copied by the transistor Mn4. At this time, the current supplied from the transistor Mp6 is 0.6 times the current supplied from the transistor Mp4.
Since it is doubled and smaller than the current flowing through the transistor Mn4, the drain voltage of the transistor Mp6 becomes low,
The transistor Mp7 is turned on. As a result, the current supplied from the current source IL is added to the bias current determination transistor Mp5 via the transistor Mp7, so that the gate-source voltage of the transistor Mp5 increases and the current supplied from the transistor Mp3 also increases. Become.

As described above, the amplifier circuit of FIG. 13 can control so that the current supplied from the transistor Mp3 of the output amplifier stage 3 becomes large when the input signal voltage changes to the positive polarity, so that the rising slew rate is increased. It has the advantage that it can be improved.

Here, the diode-connected transistor Mp5 and the bias current source Ib1 in FIGS. 12 and 13 are for determining the gate bias of the transistors Mp3 and MP4, and the bias current source Ib.
b1 is composed of the output side transistors Mi (i = 1, 2, ..., N) of the current mirror circuit described above.
Further, the current source IL in FIG. 13 can be similarly configured.

FIG. 14 shows an integrated circuit device according to the sixth embodiment of the present invention. This integrated circuit device has a plurality (N)
Of amplifier circuits 120-1 to 120-N. The amplifier circuits 120-1 to 120-N form, for example, a part of the amplifier circuit group 25 in FIG. 2 included in the liquid crystal display drive circuit 12 of the liquid crystal display device shown in FIG. , Are arranged linearly in the chip along the left-right direction of the drawing. The same gate voltage is input to the amplifier circuits 120-1 to 120-N in order to monitor the bias currents supplied from the bias current supply transistors M1 to MN and the bias current supply transistors M1 to MN. Transistors MF1 to MFN are provided respectively. That is, in each of the amplifier circuits 120-1 to 120-N, the gates are connected to each other and the sources are connected to each other.
, And one of the monitoring transistors MF1 to MFN. The drains of the monitoring transistors MF1 to MFN are connected to a current mirror circuit composed of the transistors MB1 and MB2.

The current Ibias for setting the bias current is compared with the sum of the currents output from the monitoring transistors MF1 to MFN via the current mirror circuit composed of the transistors MB1 and MB2, and the current at the drain end of the transistor MB2 is compared. Is converted into a voltage according to the difference between
And is applied to the gates of the transistors M1 to MN and the transistors MF1 to MFN in common.

In order to simplify the explanation, for example, the output transistors Mi (i = 1 to N) have the same size,
Further, the sizes of the monitoring transistors MFi (i = 1 to N) are also the same. Further, the transistor MFi (i =
The gate width / gate length (hereinafter, W / L) of 1 to N) is 1 / N of W / L of the transistor Mi (i = 1 to N).
All transistors Mi and all transistors M
If Fi is matched, the transistor Mi
Since the same voltage is applied to the gate of the transistor MFi, the current Ifi flowing in the transistor MFi is 1 / N of the current Ii flowing in the transistor Mi. Since the drains of the transistors MFi are commonly connected, the currents flowing through the transistors MFi are added, and the sum is equal to the current Ii flowing through the transistor Mi.

The sum of the currents flowing in the transistor MFi is compared with the current Ibias to be set at the drain end of the transistor MB2. If the current Ibias is larger than the sum of the currents flowing in the transistor MFi, the transistor MBi is transmitted.
2 has a higher drain voltage. This drain voltage is amplified by the amplifier A1 to increase the gate voltages of the transistor Mi and the transistor MFi to increase the current flowing through the transistor MFi, and the sum of the currents flowing through the transistor MFi becomes the same as the current Ibias. On the contrary, when the current Ibias is smaller than the sum of the currents flowing in the transistor MFi, the drain voltage of the transistor MB2 becomes low. This drain voltage is amplified by the amplifier A1, lowers the gate voltage of the transistor Mi and the transistor MFi, reduces the current flowing through the transistor MFi, and the sum of the currents flowing through the transistor MFi becomes the same as the current I _bias .

The present embodiment is characterized in that the monitoring transistors are arranged in a distributed manner in each of the amplifier circuits 120-1 to 120-N as described above. That is, the monitoring transistor MF, which is one in the past, is provided with N monitoring transistors MF1 to MFN corresponding to the number N of the amplifier circuits 120-1 to 120-N in the present embodiment, and these monitoring transistors MF1 are provided. ~ MFN is each amplifier circuit 120-
It is arranged close to the output transistors M1 to MN that generate bias currents of 1 to 120-N.

With the structure of this embodiment as described above, the problems due to the variation in the threshold voltage of the conventional transistor are solved as follows.

The gate-source voltage commonly applied to the monitoring transistors MF1 to MFN is the gate-source voltage of each of the transistors MF1 to MFN when a current of I _bias / N flows through each of the transistors MF1 to MFN. The value is close to the average value of the voltage.

Here, the monitoring transistors MF1 to MFN
If the variation in the threshold voltage (Vt) of ΔVF is ΔVF and the variation in the threshold voltage of the output transistors M1 to MN is ΔVN, the statistical expected value of ΔVF is zero, and the actual average value is also statistically expected. The value is close to the value, that is, close to zero.
The total current flowing through the transistor MFi is expressed as:

[0074]

[Equation 3]

This means that when the sum of the currents flowing through the transistors MF9 to MFN is Id, even if there is a variation ΔV _{Fi in the} threshold voltage, the VGS becomes almost equal to that when ΔV _Fi = 0. Therefore, since the average value of the bias currents supplied from the transistors M1 to MN approaches I _bias , the sum of the consumption currents of the amplifier circuits 120-1 to 120-N is the same regardless of the chips. 120-N amplifier circuit when each of the bias current is I _{bi the as} of 120-1
Since the sum of the consumption currents of 120 to N is approached, the difference in the consumption current between the chips can be reduced. Further, by reducing the difference in consumption current between chips, the amplifier circuit 120-
It is also possible to reduce the difference in characteristics between chips of 1 to 120-N. As described above, according to this embodiment, it is possible to reduce the difference in current consumption and the difference in characteristics between the chips of the amplifier circuits 120-1 to 120-N. Therefore, a chip in which these amplifier circuits 120-1 to 120-N are integrated is applied to the amplifier circuit group 25 shown in FIG. 2, for example, to configure a liquid crystal display drive circuit of the liquid crystal display device shown in FIG. Then, the integrated liquid crystal display drive circuit 12
Since it is possible to reduce variations in current consumption and characteristics between chips, it is possible to facilitate the design, especially the design of the bias circuit, and reduce image quality deterioration due to variations in characteristics.

FIG. 15 shows a seventh embodiment in which the amplifier A1 of the integrated circuit device of FIG. 14 is realized by a source follower composed of a transistor MA1 and a current source IB1.

FIG. 16 shows an integrated circuit device according to the eighth embodiment. According to this embodiment, the amplifier A1 of the integrated circuit device of FIG. 14 receives as its input the transistor MA10 that generates a current according to the input voltage of the amplifier A1 and the difference current between the current flowing through the transistor MA10 and the bias current IB2. Diode-connected transistor MA
11, a transistor MA11, which forms a current mirror together with the transistor MA11, returns a difference current between the current flowing in the transistor MA10 and the bias current IB2 and outputs the current, and a diode-connected transistor MA13 which inputs the current. The transistor MA13 forms a current mirror with the output transistors M1 to MN and the monitoring transistors MF1 to MFN.

To simplify the description, the transistor MA
10 to MA12 have the same size, and the transistor MA
It is assumed that the size of 13 is equal to the size of the transistors M1 to MN. Further, IB2 = 2Ibias.

The current generated in the transistor MA10 according to the input voltage of the amplifier A1 is compared with the bias current IB2, and the difference current is reflected by the current mirror formed by the transistors MA11 and MA12. This difference current is I _bias
When larger, the average value of the current flowing through each of the monitoring transistors MF1 to MFN becomes larger than 1 _bias / N,
Therefore, the sum of the currents of the monitoring transistors MF1 to MFN becomes larger than I _bias , and the drain voltage of the transistor MB2 decreases. Therefore, the gate-source voltage of the input transistor MA10 of the amplifier A1 increases, and the difference current from the bias current I _B2 approaches I _bias .

[0080] During differential current between the current and the bias current _{I B2} generated in response to the input voltage of the amplifier A1 at the transistor MA10 is lower than I _bias, monitoring transistor MF1~M
The average value of the current flowing through each of the FNs is smaller than I _bias / N, and thus the sum of the currents of the monitoring transistors MF1 to MFN is smaller than I _bias , and thus the transistor M
The drain voltage of B2 rises. Therefore, the gate-source voltage of the amplifier transistor MA10 of the amplifier A1 becomes small, and the current generated according to the input voltage and the bias current I
The difference current with _B2 approaches I _bias .

In general, when the number of the amplifier circuits integrated on one chip is divided by the number N of the amplifier circuits integrated in one chip, the number of the amplifier circuits generally takes a large value of 300.
The monitoring transistors MFi (i = 1 to N) are very small transistors and may be virtually impossible to form. At this time, the same effect can be obtained by setting the number of divisions to N / L (L is a positive number) and arranging the monitoring transistors MFi every L pieces of the amplifier circuit.

FIG. 17 shows an integrated circuit device according to the ninth embodiment in which L = 2.

As in the integrated circuit device according to the tenth embodiment of FIG. 18, the output transistor Mi (i = 1-N) and the monitoring transistor MFi (i = 1-N) and the amplifier A1 forming a current mirror are formed. A plurality of diode-connected transistors MA13-1 to MA13- (N / 2) are provided in the amplifier circuits 24-1 to 24-N to monitor the plurality of monitoring transistors M.
It may be arranged alternately with Fi.

Further, as in the integrated circuit device according to the eleventh embodiment shown in FIG. 19, two monitoring transistors are arranged at both ends of an array of a plurality of amplifier circuits, so that the monitoring transistors MF1 and MF2 are connected to each other. Variations can be reduced by shortening the distance from the transistors M1 to MN in the amplifier circuit to improve matching. At this time,
The diode-connected transistors MA13-1, 13 of the amplifier A1 as in the twelfth embodiment shown in FIG.
-2 may be arranged at both ends of the array of the plurality of amplifier circuits 126-1 to 126-N.

FIG. 21 shows an integrated circuit device according to the thirteenth embodiment in which the amplifier A1 is constructed by using a differential amplifier circuit. According to this, by connecting the negative input of the differential amplifier circuit to the drain of the diode-connected transistor MB1, it is possible to control so that the drain voltages of the transistors MB1 and MB2 become equal. As a result, the accuracy of the current mirror formed by the transistors MB1 and MB2 can be improved.

The integrated circuit device according to the fourteenth embodiment shown in FIG. 22 is configured by using a differential amplifier circuit for the amplifier A1 of FIG. This differential amplifier circuit includes transistors MA22 and MA23 forming an input differential pair, a transistor MA21 supplying a current to the input differential pair, and a transistor M.
The output current of A22 is input, and the amplifier circuits 128-1 to 12-12
8-N transistors M1 to MN and monitoring transistors MF1 to MFN, and a diode-connected transistor MA24 forming a current mirror. In this example, the drain voltage of the transistor MB1 is level-shifted using the diode-connected transistor MB3 so that the input voltage of the differential amplifier circuit falls within the operating range of the differential amplifier circuit. The diode-connected transistor MB4 is a level shift transistor inserted so that the drain voltage of the transistor MB2 becomes equal to the drain voltage of the transistor MB1.

To simplify the description, the transistor MA2
The W / L of 1 is twice the W / L of the transistor MB1. Therefore, a current twice as large as I _bias flows in the transistor MA21. Also, the transistors MB3 and MB
4, MA22 and MA23 have the same size. further,
It is assumed that the transistor MA24 and the transistors M1 to MN have the same size.

The positive input voltage of the amplifier Al applied to the gate of the transistor MA23 is the negative input voltage applied to the gate of the transistor MA22, that is, the gate-source voltage of the transistor MB3 in which the drain voltage of the transistor MB1 is diode-connected. The voltage is compared with the voltage level-shifted. Monitoring transistors MF1 to MF
The sum of the currents flowing through N is the bias current I _bias folded by the current mirror by the transistors MB1 and MB2.
When it is larger and the positive input voltage is lower than the negative input voltage, half or more of the current supplied from the transistor MA21 flows to the transistor MA23, and the current flowing to the transistor MA22 becomes smaller than Ibias. Transistor MA2
The current flowing through 2 is the diode-connected transistor M
The gate voltage of the transistor MA24 that is input to A24 decreases, the sum of the currents flowing through the monitoring transistors MF1 to MFN decreases, and the transistors operate to approach Ibias. Further, the sum of the currents flowing through the monitoring transistors MF1 to MFN is smaller than the bias current I _bias folded by the current mirror by the transistors MB1 and MB2,
When the positive input voltage is higher than the negative input voltage, the transistor M
Less than half of the current supplied from A21 is transistor M
The current flowing in A23 and flowing in the transistor MA22 is I
_Greater than _bias . The current flowing in the transistor MA22 is input to the diode-connected transistor MA24, the gate voltage of the transistor MA24 increases, the sum of the currents flowing in the monitoring transistors MF1 to MFN increases, and the transistor MA24 operates so as to approach I _bias .

[0089]

As described above, in the integrated circuit device of the present invention, in the current mirror circuit which constitutes the bias circuit of the electronic circuit such as a plurality of amplifier circuits, the output side transistor is provided in each electronic circuit and the input circuit is provided. By arranging the side transistors in multiple electronic circuits, or by arranging them adjacent to the electronic circuits on both sides, it is possible to reduce the variation in the threshold voltage of the input side transistors between chips, and The difference in current consumption and characteristics can be reduced.

Further, according to the present invention, there is provided a liquid crystal display device in which such an integrated circuit device is used for a drive circuit, the design of the power supply is particularly easy, and the image quality deterioration due to the characteristic difference between chips is reduced. be able to.

Further, by arranging the plurality of monitoring transistors adjacent to the output transistor which generates the bias current in each circuit, the matching between the monitoring transistor and the transistor which generates the bias current in each circuit is improved. Therefore, it is possible to reduce the consumption current and the difference in characteristics between chips.

Further, when the amplifier circuit group in the drive circuit of the liquid crystal display device is configured by using the integrated circuit device according to the present invention, the difference in current consumption and characteristics between the chips is small, and therefore the image quality deterioration due to the characteristic variation is small. A liquid crystal display device can be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a liquid crystal display device.

FIG. 2 is a diagram showing a configuration of a liquid crystal display drive circuit in FIG.

FIG. 3 is a diagram showing a configuration of an integrated circuit device according to a first embodiment of the present invention.

FIG. 4 is a diagram showing an arrangement pattern of input side transistors and output side transistors.

5 is a diagram showing a transistor array pattern of the integrated circuit device of FIG.

FIG. 6 is a diagram showing a configuration of an integrated circuit device according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of an integrated circuit device according to a third embodiment of the present invention.

FIG. 8 is a diagram showing a basic circuit and a final circuit of a bias circuit portion for explaining the embodiment.

9 is a diagram showing a basic pattern and a final pattern corresponding to the basic circuit and the final circuit of FIG. 8, respectively.

FIG. 10 is a diagram showing a configuration of an integrated circuit device according to a fourth embodiment of the present invention.

FIG. 11 is a diagram showing a configuration of an integrated circuit device according to a fifth embodiment of the present invention.

FIG. 12 is a diagram showing a configuration example of an amplifier circuit to which the present invention is applied.

FIG. 13 is a diagram showing another configuration example of an amplifier circuit to which the present invention is applied.

FIG. 14 is a diagram showing a configuration of an integrated circuit device according to a sixth embodiment of the present invention.

FIG. 15 is a diagram showing a configuration of an integrated circuit device according to a seventh embodiment of the present invention.

FIG. 16 is a diagram showing a configuration of an integrated circuit device according to an eighth embodiment of the present invention.

FIG. 17 is a diagram showing a configuration of an integrated circuit device according to a ninth embodiment of the present invention.

FIG. 18 is a diagram showing a configuration of an integrated circuit device according to a tenth embodiment of the present invention.

FIG. 19 is a diagram showing a configuration of an integrated circuit device according to an eleventh embodiment of the present invention.

FIG. 20 is a diagram showing a configuration of an integrated circuit device according to a twelfth embodiment of the present invention.

FIG. 21 is a diagram showing a configuration of an integrated circuit device according to a thirteenth embodiment of the present invention.

FIG. 22 is a diagram showing a configuration of an integrated circuit device according to a fourteenth embodiment of the present invention.

[Explanation of symbols]

10 ... Liquid crystal display 11 ... Liquid crystal cell 12 ... Liquid crystal display drive circuit 13 ... Scan line selection circuit 14 ... Signal line 15 ... Scan line 21 ... Shift register 22 ... Storage element 23 ... Storage element 24 ... D / A converter 25 ... Amplifying circuit group 26 ... Bias circuit 31-3N ... Amplification circuit 61-6N ... Amplifying circuit MR1 to MRN ... Input side transistors M1-MN ... Output side transistor Ibias ... Bias current setting current Vss ... power supply line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ identification code FI H03F 3/68 H03F 3/68 Z (58) Fields investigated (Int.Cl. ⁷ , DB name) G09G 3/36 G02F 1 / 133 505 G09G 3/20 611 G09G 3/20 623 H03F 3/343 H03F 3/68

Claims (14)

(57) [Claims] 1. An integrated circuit device in which a plurality of amplifier circuits are integrated in a row in the same chip: A diode provided for every L (L is an integer of 1 or more) of the plurality of amplifier circuits. A plurality of input side transistors connected to each other; and a plurality of output side transistors respectively provided in the plurality of amplifier circuits; a current mirror circuit is formed by the input side transistors and the output side transistors, and the input The side transistor receives an input current for setting a bias current to be supplied to the amplifier circuit, and the output side transistor supplies an output current corresponding to the input current to the amplifier circuit as a bias current, respectively. Integrated circuit device. 2. In an integrated circuit device in which a plurality of amplifier circuits are integrated in a row in the same chip: a plurality of diode-connected transistors arranged in each of the plurality of amplifier circuits; and a plurality of amplifiers. A plurality of output side transistors respectively provided in the circuit; and P for every M (M is an integer of 1 or more) of the plurality of amplifier circuits among the plurality of diode-connected transistors.
Only (P is an integer of P ≦ M) is connected and used as an input side transistor to form a current mirror circuit with the output side transistor, and the input side transistor sets a bias current to be supplied to the amplifier circuit. Receiving an input current for supplying the output current to the amplifier circuit as a bias current, the output side transistor supplies an output current corresponding to the input current to the amplifier circuit. 3. An integrated circuit device in which a plurality of amplifier circuits are integrated in a row in the same chip: two input side transistors arranged at both ends of the plurality of amplifier circuits; A plurality of output side transistors respectively provided in the amplifying circuit; the input side transistor and the output side transistor constitute a current mirror circuit, and the input side transistor sets a bias current to be supplied to the amplifying circuit. The integrated circuit device, wherein the output side transistor supplies an output current corresponding to the input current to the amplifier circuit as a bias current, respectively. 4. A liquid crystal display in which a plurality of pixels, a signal line for selectively applying an image signal to each pixel, and a scanning line intersecting with the signal line are formed; and the signal line is amplified to amplify the image signal. Is configured to include an amplifier circuit group that supplies
In a liquid crystal display device having a drive circuit for driving the signal line; and a selection circuit for selecting the scanning line: In the amplification circuit group, a plurality of predetermined amplification circuits are integrated in a row in the same drive circuit chip. The drive circuit chips are L (where L is 1) of the amplifier circuit.
A plurality of diode-connected input-side transistors that are provided every other integer; and a plurality of output-side transistors that are respectively provided in the amplifier circuit; currents in the input-side transistor and the output-side transistor A mirror circuit is configured, the input side transistor receives an input current for setting a bias current supplied to the amplification circuit, and the output side transistor uses an output current corresponding to the input current as a bias current to the amplification circuit. A liquid crystal display device characterized by being supplied respectively. 5. A liquid crystal display in which a plurality of pixels, a signal line for selectively applying an image signal to each pixel, and a scanning line intersecting with the signal line are formed; and the signal line is amplified to amplify the image signal. Is configured to include an amplifier circuit group that supplies
In a liquid crystal display device having a drive circuit for driving the signal line; and a selection circuit for selecting the scanning line: In the amplification circuit group, a plurality of predetermined amplification circuits are integrated in a row in the same drive circuit chip. The drive circuit chip has two input-side transistors arranged at both ends of the row of the plurality of amplifier circuits; and a plurality of output-side transistors provided in each of the plurality of amplifier circuits. A current mirror circuit is configured by the input side transistor and the output side transistor, the input side transistor receives an input current for setting a bias current to be supplied to the amplification circuit, and the output side transistor receives the input current. A liquid crystal display device, wherein a corresponding output current is supplied to the amplifier circuit as a bias current, respectively. 6. A plurality of amplifying circuits integrated in one chip in an array form; each amplifying circuit provided in each of the plurality of amplifying circuits receives a set voltage for setting a bias current, and outputs an output current from the amplifying circuit. A plurality of output-side transistors that are supplied as bias currents to each of the plurality of L-side amplifiers (L is an integer of 1 or more) distributed in the amplifier circuits and receiving the set voltage. An integrated circuit device comprising: a plurality of monitoring transistors that output a monitoring current; and an amplifier that amplifies a voltage according to a difference between the monitoring current and a set input current and outputs the set voltage. 7. The integrated circuit device according to claim 6, wherein the amplifier comprises a source follower or an emitter follower. 8. A plurality of amplifier circuits integrated in one chip in an array form; each amplifier circuit provided with each of the plurality of amplifier circuits, receiving a set voltage for setting a bias current, and outputting an output current to the amplifier circuit. A plurality of output-side transistors that are supplied as bias currents to the plurality of monitoring transistors; a plurality of monitoring transistors that are distributed in the plurality of amplifier circuits and that output a monitoring current upon receiving the set voltage; An amplifier that amplifies a voltage according to a difference with a current and outputs the set voltage; the amplifier constitutes a current mirror together with the plurality of output side transistors, and a plurality of diode connections connected in parallel An output stage having a transistor, wherein the plurality of diode-connected transistors are provided in each of the plurality of amplifying circuits every M number (M is an integer of 1 or more) of the amplification circuit. Integrated circuit apparatus characterized by being arranged in a dispersed within. 9. A plurality of amplifying circuits integrated in one chip in an array form; each amplifying circuit provided in each of the plurality of amplifying circuits receives a set voltage for setting a bias current, and outputs an output current from the amplifying circuit. A plurality of output-side transistors that are supplied as bias currents to the two; two monitoring transistors that are arranged at both ends of the array of the plurality of amplifier circuits and that output a monitoring current upon receiving the set voltage; An integrated circuit device comprising: an amplifier that amplifies a voltage according to a difference from a current and outputs the set voltage. 10. A plurality of amplifying circuits integrated in one chip in an array form; each amplifying circuit provided in each of the plurality of amplifying circuits, receiving a set voltage for setting a bias current, and outputting the output current to the amplifier circuit. A plurality of output-side transistors that are supplied as bias currents to the plurality of monitoring transistors; a plurality of monitoring transistors that are distributed in the plurality of amplifier circuits and that output a monitoring current upon receiving the set voltage; An amplifier that amplifies a voltage according to a difference with a current and outputs the set voltage; the amplifier constitutes a current mirror together with the plurality of output side transistors, and a plurality of diode connections connected in parallel An output stage having a transistor, the plurality of diode-connected transistors being arranged at opposite ends of the array of amplifier circuits. Integrated circuit device. 11. A liquid crystal display in which a plurality of pixels, a signal line for selectively applying an image signal to each pixel, and a scanning line intersecting with the signal line are formed; and the signal line is amplified to amplify the image signal. In a liquid crystal display device including a drive circuit for driving the signal line, the drive circuit configured to include an amplifier circuit group for supplying to the signal line; and a selection circuit for selecting the scanning line: A plurality of amplifier circuits integrated in an array; the drive circuit chips are respectively provided in the plurality of amplifier circuits, receive a set voltage for setting a bias current, and bias an output current to the amplifier circuit. A plurality of output side transistors which are supplied as currents; L number of the plurality of amplification circuits (L is an integer of 1 or more) are distributed and arranged in the amplification circuit, and the set voltage is set. A liquid crystal display comprising: a plurality of monitoring transistors that receive and output a monitoring current; and an amplifier that amplifies a voltage according to a difference between the monitoring current and a set input current and outputs the set voltage. apparatus. 12. A liquid crystal display in which a plurality of pixels, a signal line for selectively applying an image signal to each pixel, and a scanning line intersecting with the signal line are formed; and the signal line is amplified to amplify the image signal. In a liquid crystal display device including a drive circuit for driving the signal line, the drive circuit configured to include an amplifier circuit group for supplying to the signal line; and a selection circuit for selecting the scanning line: A plurality of amplifier circuits integrated in an array; the drive circuit chips are respectively provided in the plurality of amplifier circuits, receive a set voltage for setting a bias current, and bias an output current to the amplifier circuit. A plurality of output side transistors which are supplied as current; a plurality of monitoring transistors which are dispersedly arranged in the plurality of amplifier circuits and which receive the set voltage and output a monitoring current And; an amplifier that amplifies a voltage corresponding to the difference between the monitoring current and the set input current to output the set voltage; the amplifier constitutes a current mirror together with the plurality of output side transistors, and the parallel An output stage having a plurality of diode-connected transistors connected to each other, wherein the plurality of diode-connected transistors are distributed in the amplifier circuit every M (M is an integer of 1 or more) of the plurality of amplifier circuits. A liquid crystal display device characterized by being arranged. 13. A liquid crystal display in which a plurality of pixels, a signal line for selectively applying an image signal to each pixel, and a scanning line intersecting with the signal line are formed, and the signal line is amplified to amplify the image signal. In a liquid crystal display device including a drive circuit for driving the signal line, the drive circuit configured to include an amplifier circuit group for supplying to the signal line; and a selection circuit for selecting the scanning line: A plurality of amplifier circuits integrated in an array; the drive circuit chips are respectively provided in the plurality of amplifier circuits, receive a set voltage for setting a bias current, and bias an output current to the amplifier circuit. A plurality of output side transistors which are supplied as currents; two monitor transistors which are arranged at both ends of the array of the plurality of amplifier circuits and which receive the set voltage and output a monitor current. Star and; the liquid crystal display device constructed by amplifying a voltage corresponding to the difference between the monitored current and setting the input current by an amplifier for outputting the setting voltage. 14. A liquid crystal display in which a plurality of pixels, a signal line for selectively applying an image signal to each pixel, and a scanning line intersecting with the signal line are formed; and the signal line is amplified to amplify the image signal. Is configured to include an amplifier circuit group that supplies
In a liquid crystal display device having a drive circuit that drives the signal lines; and a selection circuit that selects the scanning lines: the amplifier circuit group includes a plurality of amplifier circuits integrated in an array in the same drive circuit chip. The drive circuit chip is provided in each of the plurality of amplifier circuits, receives a set voltage for setting a bias current, and supplies an output current to the amplifier circuit as a bias current, and a plurality of output side transistors; A plurality of monitoring transistors which are dispersedly arranged in the plurality of amplifier circuits and which output a monitoring current upon receiving the set voltage; and amplifying a voltage according to a difference between the monitoring current and a set input current to set the setting. An amplifier that outputs a voltage; the amplifier constitutes a current mirror together with the plurality of output side transistors, and a plurality of diodes connected in parallel. Includes an output stage having a de-connected transistors, the plurality of diode-connected transistor liquid crystal display apparatus characterized by being arranged at both ends of the array of the plurality of amplifier circuits.