JP4941426B2 - Display device - Google Patents

Description

  The present invention relates to a display device, and in particular, according to a supplied current, such as a current drive type (or current designation type) light emitting element that emits light at a predetermined luminance gradation based on a current corresponding to display data. The present invention relates to a display device including a current generation supply circuit that generates and supplies a drive current having a desired current value to a load whose drive state is controlled.

Conventionally, in order to operate a predetermined load in a desired driving state, a circuit configuration using a current mirror circuit is widely known as a circuit configuration for generating and supplying a driving current having a predetermined current value to the load. ing.
As is well known, a current mirror circuit generally has a configuration in which control terminals of an input side transistor through which an input current flows and an output side transistor through which an output current flows are commonly connected. For example, the transistors of the input side and output side transistors According to the size ratio, an output current having a current value that becomes a predetermined current ratio (amplification ratio) with respect to the input current is taken out.

  On the other hand, as a next-generation display device (display) next to a liquid crystal display (LCD) that is widely used as a monitor or display for personal computers and video equipment in recent years, an organic electroluminescence element (hereinafter abbreviated as “organic EL element”). Display), inorganic electroluminescent elements (hereinafter abbreviated as “inorganic EL elements”), or self-luminous optical elements (light emitting elements) such as light emitting diodes (LEDs) arranged in a matrix Research and development for practical application of a light emitting element type display (display device) having the above has been actively conducted.

  In such a light emitting element type display (particularly, a light emitting element type display to which an active matrix driving method is applied), the display response speed is higher than that of a liquid crystal display device, and there is no dependency on the viewing angle.・ High contrast, high-definition display quality, low power consumption, etc. are possible, and since a backlight is not required unlike a liquid crystal display device, it is extremely advantageous that it can be made thinner and lighter. Has characteristics.

  An example of such a display is roughly a display panel in which display pixels including light emitting elements are arranged in the vicinity of intersections of scanning lines arranged in the row direction and data lines arranged in the column direction, and image display A grayscale current corresponding to a signal (display data) is generated and supplied to each display pixel via a data line, and a scanning signal is sequentially applied at a predetermined timing to select a display pixel in a specific row Each of the light emitting elements emits light with a predetermined luminance gradation corresponding to display data by the gradation current supplied to each display pixel, and desired image information is displayed on the display panel. Is displayed. Note that a specific example of a light-emitting element type display will be described in detail in an embodiment of the invention described later.

  Here, as the display driving operation in the display, the voltage value of the gradation signal voltage applied by the data driver to the display pixels (light emitting elements) in a specific row selected by the scanning driver is set according to the display data. By adjusting the current level, the current value of the light emission drive current that flows to each light emitting element is controlled to drive the light emission operation at a predetermined luminance gradation, or the drive current (gradation current) supplied by the data driver. A current designation type driving method is known in which the current value of the light emission drive current that flows through each light emitting element is controlled by adjusting the current value of ().

  Among such display driving methods, in the voltage designation type driving method, it is necessary to provide a pixel driving circuit that converts the voltage component of the gradation signal voltage into a current component in each display pixel. The characteristics of the active elements (thin film transistors, etc.) are easily affected by the external environment and changes over time. Therefore, the fluctuation of the current value of the light emission drive current increases, and the desired light emission characteristics can be obtained stably over a long period of time. However, in the current designation type driving method that adjusts the current value of the driving current supplied to the display pixel, such a variation in element characteristics can be suppressed. It has sex. A configuration example of the pixel driving circuit applied to the current designation type driving method will be described in detail later.

  As a specific configuration of a data driver applied to a display employing such a current designation type driving method, for example, as shown in FIG. 23, one end side (emitter) of a current path is a power supply terminal TMp. And the other end side (collector) of the current path is connected to the reference current input terminal TMr, and the one end side (emitter) of the current path is connected to the power supply terminal TMp via the common power supply line Lp. The other end side (collector) of the current path is connected to the individual output terminals OUT1, OUT2,... OUTm, and each control terminal (base) is connected to the control terminal (base) of the transistor TPr. ) With a current mirror circuit composed of a plurality of transistors TP1, TP2,... TPm connected in parallel as a basic configuration It can be favorably applied supply circuit.

  In such a data driver, according to the reference current Ir flowing through the transistor TPr, the drive currents IP1, IP2,... IPm having a constant current value flowing through the plurality of transistors TP1, TP2,. .., And OUTm (or further through an output circuit not shown), and collectively supplied to a plurality of display pixels constituting a display panel not shown. The display pixel (light emitting element) can be operated to emit light. Here, for the data driver (constant current generation and supply circuit) as shown in FIG. 23, for example, Patent Document 1 describes a basic configuration and a configuration in which variation between output currents is improved.

  In the prior art shown in FIG. 23, the case where the drive current generated by the data driver is supplied from the data driver side to the display panel (display pixel) side in the flowing direction has been described. As shown, the drive current generated by the data driver is also supplied from the display panel (display pixel) side to the data driver side in the drawing direction. The current mirror circuit constituting the current generation and supply circuit shown in FIG. 23 has a circuit configuration to which a bipolar transistor is applied, but a circuit to which a field effect transistor is applied is also known.

JP 2002-202823 A (Page 3, FIG. 2, FIG. 15)

The current mirror circuit as described above and the data driver (display device) to which the current mirror circuit is applied have the following problems.
(1) That is, in a conventional current mirror circuit, when a load such as a light emitting element is operated in a predetermined driving state, in order to generate an output current (driving current) having a current value corresponding to the driving state, It is necessary to change and control the current value of the input current flowing through the input side transistor (transistor through which the reference current flows). For this reason, when a specific load is continuously operated in different driving states, there is a problem in that input current setting control becomes complicated.

  (2) Further, when the current mirror circuit as described above is applied to a data driver, a gradation current (drive current) corresponding to display data is generated for each display pixel, and each display pixel is connected via each data line. Since the gradation current supplied to each data line changes corresponding to the display data, the input current supplied from the predetermined current source to the input side of each current mirror circuit via the current supply line The (reference current) will also change.

  In general, since the signal wiring has a parasitic capacitance (wiring capacitance), the operation of supplying current through the current supply line as described above charges the parasitic capacitance existing in the signal wiring to a predetermined potential, or This corresponds to discharging. Therefore, particularly when the current supplied through the current supply line is very small, it takes time to charge and discharge, and it takes a relatively long time to stabilize the potential of the current supply line. Become.

  Here, as the number of data lines (that is, the number of display pixels) increases in the operation of the data driver, the operation period allocated to the current holding and supply operations in each data line is shortened, and high-speed operation is required. However, as described above, since a certain amount of time is required for the charge / discharge operation to the current supply line, the operation speed of the data driver is limited due to the speed of the charge / discharge operation. . That is, as the current value of the gray scale current decreases with the miniaturization and high definition (high resolution) of the display panel, the operation speed (or operation period) of the data driver is limited. There has been a problem that it is difficult to realize a good image display operation.

(3) Further, in a display device including a data driver to which a current mirror circuit is applied, when image information is displayed in color, generally each color of red (R), green (G), and blue (B) The light emission luminance of each light emitting element is individually controlled in accordance with each color component included in the display data, so that a desired light emission color can be obtained. Since the luminance relationships (current-luminance characteristics) are different from each other, it is necessary to individually and appropriately control the current value of the input current that flows to the current mirror circuit that supplies the gradation current to the light emitting elements of the respective colors.
Therefore, the drive control for performing color display becomes complicated, and in particular, the white balance for setting the light emission luminance of each light emitting element of RGB can be controlled well so that the display color is recognized as white. This makes it difficult to cause degradation of display image quality.

  Therefore, in view of the above-described problems, the present invention provides a current generation and supply circuit that can quickly generate and supply a drive current having an appropriate current value even when the drive current supplied to the load is very small. By providing a control method thereof, it is possible to quickly generate a gradation current having an appropriate current value corresponding to display data, improve white balance, and improve display response characteristics and display image quality. It is an object to provide a display device that can be used.

The display device according to claim 1, wherein at least a plurality of scanning lines and a plurality of signal lines are arranged to be orthogonal to each other, and a plurality of display pixels are arranged in a matrix at intersections of the scanning lines and the signal lines. A display driving panel, scan driving means for applying a scanning signal for selecting each display pixel in a row unit to each scanning line, and a gray-scale current based on the display signal via each signal line. Signal driving means for supplying the display pixels to each display pixel, and supplying the gradation current having a predetermined current value to the display pixels in a selected state, thereby providing a desired image on the display panel. In the display device for displaying information, the signal driving means corresponds to each of the plurality of signal lines, and at least a signal holding means for holding a digital signal of a plurality of bits based on the display signal for each bit, and An input-side current circuit including one reference current transistor through which a reference current supplied from a constant current source flows, and a plurality of outputs each generating a unit current having a current value of a predetermined current ratio with respect to the reference current An output-side current circuit that includes a current transistor and selectively synthesizes the unit current according to each bit value of the digital signal held in the signal holding unit and supplies the unit current as the gradation current A plurality of current generation and supply circuits, each of the plurality of display pixels having a predetermined value according to a current value of the gradation current supplied from the current generation unit. operates to emit light at a luminance gradation, the red, green, provided with a light emitting element of a current drive type having any of the emission color of the blue, in the current generating means, said output voltage and said reference current transistor Transistors and form a current mirror circuit, the transistor size of the reference current transistor in the input-side current circuit of the current generation supply circuit, the current ratio of each of the unit current to the reference current, the plurality of display of the light emitting element by the pixel, the red, green, and characterized that you have been set to a value that the light emission luminance of the three primary colors the optimum white balance in a particular gradation of blue.

  The display device according to claim 2 is the display device according to claim 1, wherein the input-side current circuit includes a charge storage unit that stores a charge corresponding to a current component of the reference current flowing in the reference current transistor, The output-side current circuit generates a current having a current value of the predetermined current ratio by the output current transistor based on a voltage component corresponding to the amount of charge held in the charge storage unit. .

Display device according to claim 3, wherein, in the display device according to claim 1 or 2, wherein said current generating means, said plurality of unit current, in correspondence with each of the plurality of bits of digital signals, the reference current Are set to have current values at different ratios.

According to a fourth aspect of the present invention, in the display device according to the third aspect , the plurality of output current transistors are formed to have different transistor sizes.
The display device according to claim 5 is the display device according to claim 4 , wherein each of the plurality of output current transistors has a channel width of 2 ^k (k = 0, 1, 2, 3). ,...)), Different ratios are set.

Display device according to claim 6, wherein, in the display device according to claim 2 Symbol placement, the current generating means at a predetermined timing, by flowing the reference current to the reference current transistor, stored in the charge storage means A refresh means for refreshing the charge amount to a charge amount corresponding to the reference current is provided.
Display device according to claim 7, wherein, in the display device according to any one of claims 1 to 6, wherein the signal driving means includes a reference current supply line, wherein the reference current is supplied, the plurality of current generation supply Each of the circuits is connected in parallel to the reference current supply line corresponding to the plurality of display pixels, and the reference current is supplied through the reference current supply line.

The display device according to claim 8 is the display device according to any one of claims 1 to 7 , wherein the signal driving unit includes at least two sets of the current generation and supply circuits for each of the signal lines. , During the operation period in which the gradation current based on the digital signal of the plurality of bits previously held in one of the current generation and supply circuits is supplied to the display pixel, the next plurality of bits in the other current generation and supply circuit The operation of holding the digital signal is repeatedly performed alternately and sequentially.

The display device according to claim 9 is the display device according to any one of claims 1 to 8 , wherein the current generation unit causes the signal polarity of the gradation current to flow in a direction of drawing from the display pixel side. It is characterized by setting.
The display device according to claim 10 is the display device according to any one of claims 1 to 8 , wherein the current generation unit is configured to flow a signal polarity of the gradation current in a direction to flow into the display pixel. It is characterized by doing.
Display device according to claim 11, in the display device according to claim 1, wherein said light emitting element is characterized in that an organic electroluminescence element.

That is, in the display device according to the present invention, a plurality of display pixels having light emitting elements are arranged in a matrix in the vicinity of intersections of a plurality of scanning lines (scanning lines) and a plurality of data lines (signal lines) orthogonal to each other. A data driver provided with a current generation and supply circuit corresponding to each data line (or display pixel) in a display device having an arrayed display panel that generates and supplies gradation currents according to display signals (Signal driving means) A multi-bit digital signal (signal holding means) held in a data latch unit (signal holding means) during a selection period of a display pixel group arranged in a predetermined row of the display panel. Display data) and a constant current supplied from a constant current source, a combined current of a specific unit current generated in a current generator (current generator) is used as a gradation current. Each of the plurality of display pixels is supplied to the display pixel, and each of the plurality of display pixels emits light in accordance with the current value of the grayscale current supplied from the current generation unit, and has a light-emitting type of any one of red, green, and blue In the current generation unit, the reference current transistor and the output current transistor constitute a current mirror circuit, and the transistor size of the reference current transistor of each current generation supply circuit is the current of each unit current with respect to the reference current. The ratio is set to a value at which the light emission luminances of the three primary colors of red, green, and blue of the light emitting elements in the plurality of display pixels are optimal white balance at a specific gradation. As a result, when performing color display of desired image information, even if the current-luminance characteristics of the light emitting elements of RGB colors are different, white display and color display with good luminance can be performed by a simple control method. This can be realized and display image quality can be improved.

  Further, since the gradation current supplied to the display pixel by the gradation current generation circuit is generated based on a constant reference current and a multi-bit digital signal, the display pixel emits light with a relatively low luminance gradation. This is the case when the operation is performed (when the current value of the gradation current is very small), or when the supply time (selection time) of the gradation current to the display pixel is set shorter due to the high definition of the display panel. However, it is possible to eliminate the influence of signal transmission delay caused by the charge / discharge operation to the parasitic capacitance existing in the reference current supply line to which the reference current is supplied, and suppress the decrease in the operation speed of the data driver. Thus, display response characteristics and display image quality in the display device can be improved.

  Note that the display device according to the present invention includes two sets of the above-described gradation current generation circuits (current driving circuits) for each data line of each column to which the display pixels are connected, and the two sets of gradation current generation circuits. Are alternately set to the selected state, and an operation for supplying the grayscale current from one grayscale current generation circuit to the display pixel group in a predetermined row is performed in parallel with the other grayscale current generation circuit. The display data (multi-bit digital signal) corresponding to the display pixel in the next row may be configured to be executed and held. According to this, two sets of gradation currents are an operation for supplying a gradation current to a display pixel in a specific row and an operation for capturing display data for generating a gradation current to be supplied to a display pixel in the next row. By alternately and repeatedly executing the generation circuit, the gradation current can be continuously generated and supplied to the display pixels in each row, so that the operation speed of the data driver is substantially improved, and the display device Image quality can be improved.

  As described above, in the display device according to the present invention, a display including a display panel in which display pixels including light emitting elements are arranged in a matrix in the vicinity of intersections of scanning lines and data lines orthogonal to each other. In the apparatus, a current generation supply circuit that generates and supplies a gradation current according to a display signal is applied to a gradation current generation circuit of a data driver provided corresponding to each data line (or display pixel), Each of the plurality of display pixels includes a current-driven light emitting element having a light emission color of red, green, or blue that emits light according to a current value of a gradation current supplied from a current generation unit, The transistor size of the reference current transistor of each current generation and supply circuit is such that the current ratio of each unit current to the reference current is the light emission of the three primary colors of light emitting elements in a plurality of display pixels. Since the degree is set to an optimal white balance at a specific gradation, when the color display of desired image information is performed, the current-luminance characteristics of the light emitting elements of each RGB color are different. However, it is possible to realize white display and color display with good luminance by a simple control method, and it is possible to improve display image quality.

  Further, since the gradation current supplied to the display pixel by the gradation current generation circuit is generated based on a constant reference current and a multi-bit digital signal, the display pixel emits light with a relatively low luminance gradation. This is the case when the operation is performed (when the current value of the gradation current is very small), or when the supply time (selection time) of the gradation current to the display pixel is set shorter due to the high definition of the display panel. However, it is possible to eliminate the influence of signal transmission delay caused by the charge / discharge operation to the parasitic capacitance existing in the reference current supply line to which the reference current is supplied, and suppress the decrease in the operation speed of the data driver. Thus, display response characteristics and display image quality in the display device can be improved.

Hereinafter, a display device including a current generation and supply circuit according to the present invention will be described in detail with reference to embodiments.
First, a current generation and supply circuit and a control method thereof according to the present invention will be described with reference to the drawings.

<First Embodiment of Current Generation and Supply Circuit>
FIG. 1 is a schematic configuration diagram showing a first embodiment of a current generating and supplying circuit according to the present invention.
As shown in FIG. 1, the current generation supply circuit (current generation means) CLM according to the present embodiment has a p-channel type field effect having a current path (source-drain) between a high potential power supply + V and a contact Npa. Type switch (hereinafter referred to as “p-channel transistor”) TPA, and a switch SWA for controlling the connection state (conduction state) between the contact Npa and the control terminal (gate terminal) of the p-channel transistor TPA and the contact Np. A p-channel transistor TPB having a current path between the high potential power supply + V and the contact Npb, and a switch SWB for controlling a connection state between the contact Npb and the control terminal of the p-channel transistor TPB and the contact Np. , A p-channel transistor (output current) in which the current path is connected between the high potential power supply + V and the output terminal Tout, and the control terminal is connected to the contact Np. And a capacitor (charge storage means) Cp connected between the contact Np and the high potential power supply + V, and further between the contact Np and the low potential power supply (for example, ground potential) -V. In addition, a constant current generation source (constant current source) IR for supplying a reference current Iref having a constant current value is connected.

Here, in the present embodiment, by connecting the high potential power source + V to one end side of the p-channel transistors TPA and TPB and connecting the low potential potential power source −V to the other end side of the constant current generation source IR. As will be described later, the reference current Iref flows in the direction of the constant current generation source IR from the high potential power source + V and the p-channel transistors TPA and TPB.
In the present embodiment, a circuit including a p-channel transistor TPA and a switch SWA, a p-channel transistor TPB, and a switch are provided between the high-potential power supply + V and the contact Np (or constant current generation source IR). Although a configuration in which circuits composed of SWBs are connected in parallel has been shown, the present invention is not limited to this, and may have a configuration in which a plurality of circuits of two or more systems are connected in parallel.

  The p-channel transistors TPA and TPB (reference current transistors) constituting the current generation and supply circuit are set to have different channel widths, and the switches SWA and SWB (changeover switches) are not shown in the drawing. Based on the control signal CNT (switching control signals CNa and CNb) supplied from the unit, only one of them is controlled to be in a conductive state, and the gate terminal and the current path of the p-channel transistor TPA or TPB are connected to the contact Np. Configured to selectively connect to.

  Thus, based on the control signal CNT (switching control signals CNa and CNb), either one of the p-channel type transistors TPA or TPB is electrically connected between the high potential power supply + V and the contact Np, and is fixed. A reference current Iref having a constant current value is supplied to the p-channel transistor by the current source IR, so that the reference current Iref and the p-channel transistor TPA or TPB are supplied to each gate terminal (contact Np). A constant voltage component (reference voltage) corresponding to the channel width is generated and applied to the gate terminal of the p-channel transistor TPC. That is, the p-channel transistor TPA or TPB and the p-channel transistor TPC form a current mirror circuit.

  Here, since the p-channel transistors TPA and TPB are set to have different channel widths, the voltage component generated at the contact Np has two different levels depending on the conduction state of the switches SWA and SWB. It becomes. As a result, the conduction state of the p-channel transistor TPC is controlled according to the voltage component generated at the contact Np, and the current Iout output from the high-potential power supply + V via the p-channel transistor TPC and the output terminal Tout is 2 It will be set to the type of current value. That is, two types of current ratios (drive characteristics) that define the current value of the output signal Iout can be set with respect to a constant reference current Iref. The circuit configuration including the p-channel transistors TPA and TPB and the switches SWA and SWB constitutes the input-side current circuit in the present invention, and the circuit configuration including the p-channel transistor TPC includes the output-side current circuit in the present invention. Constitute.

  In the present embodiment, as described above, the configuration in which the output current Iout is supplied in the direction of flowing out from the current generation supply circuit (hereinafter referred to as “current application method” for convenience) is shown. The present invention is not limited to this, and as shown in FIG. 1B, a configuration for supplying the output current Iout so as to draw it in the direction of the current generation and supply circuit (hereinafter referred to as “current sink method” for convenience) May be included). In this case, as shown in FIG. 1B, in the current generation and supply circuit CLM shown in FIG. 1A, an n-channel field effect transistor (n-channel) is used instead of the p-channel transistors TPA to TPC. A high potential power source + V is connected to the other end of the constant current source IR so that the reference current Iref is supplied from the constant current source IR side to the current generation supply circuit CLM by applying the TNA to TNC. The n-channel transistors TNA to TNC are connected, and one end side thereof is connected to the low potential power source −V.

<Second Embodiment of Current Generation and Supply Circuit>
FIG. 2 is a schematic configuration diagram showing a second embodiment of the current generating and supplying circuit according to the present invention. Here, about the structure equivalent to 1st Embodiment mentioned above, the same or equivalent code | symbol is attached | subjected and the description is simplified.
As shown in FIG. 2A, the current generation and supply circuit ILA according to the present embodiment includes a multi-bit digital signal (in this embodiment, a case of 4 bits) d0 for designating a current value. A data latch unit (signal holding unit) 10 including latch circuits LC0, LC1, LC2, LC3 (LC0 to LC3) that individually capture and hold (latch) d1, d2, and d3 (d0 to d3), and a constant current A reference current Iref having a constant current value supplied from a generation source (constant current source) IR via a reference current supply line Ls is taken in and output from the data latch unit 10 (each latch circuit LC0 to LC3). signal (inverted output ^{signal) d10 *, d11 *, d12} *, d13 * (d10 * ~d13 *; hereinafter, in this specification, the symbol indicating the inverted polarity, a conveniently ^"*" 2A and 2B), a load drive current (drive current) ID having a current value of a predetermined ratio with respect to the reference current Iref is generated, and the drive current supply line Ld is generated. And a current generation unit (drive current generation means) 20A that outputs to a load (not shown). Here, in the present embodiment, the constant current generation source IR is connected to the low potential power supply (ground potential) Vgnd at the other end so as to flow in the direction of extracting the reference current Iref from the current generation unit 20A.

Note that the configuration of the data latch unit 10 illustrated in FIG. 2A is represented by a circuit symbol as illustrated in FIG. In FIG. 2B, IN0 to IN3 respectively indicate the input contacts IN of the respective latch circuits LC0 to LC3 shown in FIG. 2A, and OT0 to OT3 respectively indicate the non-intervals of the respective latch circuits LC0 to LC3. It shows the inverted output contact ^OT, OT0 ^* ~OT3 *, respectively, showing the inverted output contact OT ^* of the latch circuits LC0～LC3.

Hereafter, each said structure is demonstrated concretely.
(Data latch unit 10)
As shown in FIG. 2A, the data latch unit 10 has a configuration in which a number of latch circuits LC0 to LC3 corresponding to the number of bits (4 bits) of the digital signals d0 to d3 are provided in parallel. Based on timing control signals (non-inverted clock signal) CLK and (inverted clock signal) CLK ^* output from a timing generator, a shift register, etc., omitted, the timing control signal CLK is at a high level (CLK ^* is at a low level). At the same time, the digital signals d0 to d3 supplied individually are simultaneously captured, and the timing control signal CLK is a signal based on the captured digital signals d0 to d3 when the timing control signal CLK becomes low level (CLK ^* is high level). Outputs and holds the level (non-inversion level and inversion level) (signal holding operation)

(Current generator 20A)
FIG. 3 is a circuit configuration diagram illustrating a specific example of a current generation unit applied to the current generation and supply circuit according to the present embodiment. FIG. 4 illustrates a specified gradation in the current generation and supply circuit according to the present embodiment. It is a characteristic view showing an example of current characteristics (gradation-current characteristics).
As shown in FIG. 3, the current generator 20A generates a plurality of unit currents Isa, Isb, Isc, Isd (Isa to Isd) each having a current value with a different ratio with respect to the reference current Iref. Of the circuit unit 21A and the plurality of unit currents Isa to Isd, output signals (inverted output signals) d10 ^{* to} d13 ^* (shown in FIG. 2) output from the latch circuits LC0 to LC3 of the data latch unit 10 described above. And a switch circuit portion (selection switch) 22A for selecting an arbitrary unit current based on the inverted output contacts OT0 ^{* to} OT3 ^* . The current mirror circuit unit 21A further includes a reference current transistor unit and a unit current transistor unit.

  Specifically, the reference current transistor unit (input current circuit) that constitutes the current mirror circuit unit 21A includes p-channel transistors TPA and TPB, switches in the current generation and supply circuit CLM shown in the first embodiment described above. A current input contact INi (contact Nga) that has a configuration equivalent to a circuit composed of SWA, SWB, and capacitor Cp, and is supplied (pulled out) from the constant current generation source IR via the reference current supply line Ls. ) And the high potential power source + V, a circuit including a reference current transistor TP11a and a switch SAa made of a p-channel transistor, and a circuit having a reference current transistor TP11b and a switch SAb made of a p-channel transistor Each has a configuration connected in parallel. A capacitor (charge storage means) Ca is connected between the contact Nga to which the current input contact INi is connected and the high potential power supply + V.

  Here, the current path and the control terminal (gate) of the p-channel transistor TP11a are connected to the current input contact INi and the contact Nga via the switch SAa whose conduction state is controlled by the switching control signal CNa, and p The current path and the control terminal (gate) of the channel type transistor TP11b are connected to the current input contact INi and the contact Nga via the switch SAb whose conduction state is controlled by the switching control signal CNb.

Further, the unit current transistor portion (output current circuit) constituting the current mirror circuit portion 21A specifically has current paths between the respective contacts Na, Nb, Nc, Nd and the high potential power supply + V. The unit current transistors (output current transistors) TP12, TP13, TP14, TP15 (TP12) are connected in parallel and each control terminal is connected in common to the contact point Nga, and each of which is a p-channel transistor having a predetermined channel width. To TP15). Here, as will be described later, the unit current transistors TP12 to TP15 are configured to have different transistor sizes at a predetermined ratio.
In FIG. 3, the magnitude relationship between the transistor sizes of the field-effect transistors constituting the current mirror circuit unit 21A is shown for convenience and concept by changing the width of the circuit symbol of the transistor.

The switch circuit unit 22A has a current path connected between the current output contact OUTi to which a load is connected and the contacts Na, Nb, Nc, and Nd, and each of the data latch units 10 is connected to a control terminal. Switch transistors TP16, TP17, TP18, TP19 (TP16 to TP19) composed of a plurality of (four) p-channel transistors to which output signals d10 ^{* to} d13 ^* individually output from the latch circuits LC0 to LC3 are applied in parallel. ).

In the current generating unit 20A according to the present embodiment, in particular, the unit currents Isa to Isd flowing through the unit current transistors TP12 to TP15 constituting the current mirror circuit unit 21A described above are the reference current transistor unit (reference current transistor). TP11a or TP11b) is set to have a different current ratio with respect to a certain reference current Iref flowing in TP11a or TP11b).
Specifically, the unit current transistors TP12 to TP15 have different transistor sizes, for example, in the field effect transistors constituting the unit current transistors TP12 to TP15, the channel width when the channel length is constant. The ratio is W12: W13: W14: W15 = 1: 2: 4: 8. Here, W12 represents the channel width of the unit current transistor TP12, W13 represents the channel width of the unit current transistor TP13, W14 represents the channel width of the unit current transistor TP14, and W15 represents the unit current transistor TP15. Indicates the channel width.

As a result, the current values of the unit currents Isa to Isd flowing through the unit current transistors TP12 to TP15 are Isa = (W12), where W11 is the channel width of the reference current transistor portion (either the reference current transistor TP11a or TP11b). / W11) × Iref, Isb = (W13 / W11) × Iref, Isc = (W14 / W11) × Iref, Isd = (W15 / W11) × Iref. Therefore, the channel widths of the unit current transistors TP12 to TP15 are set to be 2 ^k (k = 0, 1, 2, 3,...; 2 ^k = 1, 2, 4, 8,...), Respectively. By setting so as to be, the current value between the unit currents Isa to Isd can be set to a ratio defined by 2 ^k .

  In particular, the current generator 20A according to the present embodiment has a configuration including two systems of reference current transistors TP11a and TP11b each having a different channel width as the reference current transistor unit. By selectively switching the reference current transistor TP11a or TP11b that constitutes, two types of current values of the unit currents Isa to Isd generated by the unit current transistors TP12 to TP15 can be set.

Then, from each unit current Isa to Isd in which the current value is set in this way, as will be described later, a plurality of digital signals d0 to d3 (that is, output signals d10 ^{* to} d13 ^* from the data latch unit 10). Based on this, by selecting and synthesizing arbitrary unit currents, as shown in FIG. 4, a load drive current ID having a current value of 2 ^k steps is generated and a control signal CNT (switching control signal CNa, CNb) generates two types of load drive currents having different current characteristics with respect to gradations (designated gradations) designated based on the multi-bit digital signals d0 to d3. Here, in FIG. 4, SPa indicates a current characteristic when the reference current transistor TP11a is selected, and SPb indicates a current characteristic when the reference current transistor TP11b is selected. Thereby, as shown in FIGS. 2 and 3, when the 4-bit digital signals d0 to d3 are applied, according to the ON state of the switch transistors TP16 to TP19 connected to the unit current transistors TP12 to TP15, For each current characteristic, a load drive current ID having different current values in 2 ⁴ = 16 steps (gradation) is generated.

That is, in the current generation unit 20A having such a configuration, a specific switch in the switch circuit unit 22A according to the signal level of the output signals d10 ^{* to} d13 ^* output from the latch circuits LC0 to LC3 ^. The transistor is turned on (including the case where any one or more of the switch transistors TP16 to TP19 is turned on), and is connected to the switch transistor that is turned on. The unit current transistor (a combination of any one or more of TP12 to TP15) of the current mirror circuit unit 22A with respect to the reference current Iref flowing through the reference current transistor TP11a or TP11b (a × 2 ^k times; a Is a reference current transistor TP11a or TP Unit current Isa to Isd having a current value of a constant defined by a channel width W11 of 1b, and, as described above, a load drive having a current value that is a combined value of these unit currents at the current output contact OUTi. The current ID is illustrated from the high potential power supply + V via the unit current transistor (any one of TP12 to TP15) connected to the switch transistor (any one of TP16 to TP19) and the current output contact OUTi. Flow in the omitted load direction.

Thereby, in the current generation supply circuit ILA according to the present embodiment, according to the multi-bit digital signals d0 to d3 input to the data latch unit 21A at the timing defined by the timing control signals CLK and CLK ^* , A load driving current ID composed of an analog current having a predetermined current value is generated by the current generator 22A and supplied to the load (in the present embodiment, as described above, from the current generation supply circuit side) Load drive current flows in the load direction).

Therefore, in the current generation and supply circuit ILA having the above-described configuration, for example, control signals CNT (switching control signals CNa and CNb) for switching and controlling current characteristics output from a control unit (controller) or the like (not shown). The switch SAa or SAb is selectively set to a conductive state based on the above, and either of the two reference current transistors TP11a or TP11b is connected to one of the reference current transistors via the current input contact INi. A reference current Iref having a constant current value is supplied (extracted) from the IR.
As a result, a predetermined voltage level is uniquely generated at the gate terminal (contact Nga) of the reference current transistor based on the reference current Iref and the channel width, and is commonly applied to the gate terminal of each unit current transistor. Therefore, the current ratio of the unit currents Isa to Isd flowing through the unit current transistors TP12 to TP15 with respect to the reference current Iref is uniquely defined, and the current characteristic of the load drive current ID is set.

  For this reason, when the load is operated in a driving state with a relatively low gradation, as shown by the current characteristic SPa in FIG. 4, the change in the load driving current with respect to the designated gradation is in a gradual state. When the control signal CNT is set so that the reference current Iref flows to the reference current transistor TP11a side and the load is operated in a relatively high gradation driving state, the current characteristic SPb in FIG. 4 is indicated. In addition, the current supplied to the current generation and supply circuit ILA is set by passing the reference current Iref through the reference current transistor TP11b by the control signal CNT so that the change of the load driving current with respect to the specified gradation becomes steep. The load can be operated with different driving characteristics while keeping the component (reference current) constant.

  In this embodiment as well, as in the first embodiment described above, the current polarity is set so that the load drive current ID flows from the current generation supply circuit side to the load connected to the current generation supply circuit. However, the present invention is not limited to the configuration applying the current application method, but has a configuration using the current sink method in which the current polarity is set so as to draw the load drive current ID from the load side toward the current generation supply circuit. May be. Hereinafter, a current generation and supply circuit corresponding to the current sink method will be briefly described later.

<Third Embodiment of Current Generation and Supply Circuit>
FIG. 5 is a schematic configuration diagram illustrating a third embodiment of a current generation and supply circuit according to the present invention, and FIG. 6 illustrates a specific example of a current generation unit applied to the current generation and supply circuit according to the present embodiment. FIG. Here, about the structure equivalent to embodiment mentioned above, the same or equivalent code | symbol is attached | subjected and the description is simplified or abbreviate | omitted.

  As shown in FIG. 5, the current generation supply circuit ILB according to the present embodiment includes a data latch unit 10 and the data latch unit 10 (latch circuit LC0) as in the second embodiment (see FIG. 2). To LC3) and a current generator 20B connected to the non-inverting output terminal OT. Here, in the present embodiment, the constant current generation source IR connected to the current generation unit 20B has the other end connected to the high potential power supply + V so as to flow the reference current Iref into the current generation unit 20B.

  Further, as shown in FIG. 6, the current generation unit 20B according to the present embodiment includes a current mirror circuit unit 21B and a switch circuit unit 22B that have a circuit configuration substantially equivalent to that of the above-described embodiment (see FIG. 3). And a reference current Iref based on output signals (non-inverted output signals) d10 to d13 from the latch circuits LC0 to LC3 and control signals CNT (switching control signals CNa and CNb) output from the control unit. In contrast, a load driving current ID generated by selectively combining a plurality of unit currents Ish, Isi, Isj, Isk (Ish to Isk) having a current value of a predetermined ratio is supplied to the load. ing.

  Specifically, in the current generation unit 20B, all the transistors TN21a, TN21b, and TN22 to TN29 constituting the current mirror circuit unit 21B and the switch circuit unit 22B are n-channel transistors, and the reference current transistors TN21a and TN21b are The current path is connected in parallel between the current input contact INi and the low potential power source −V (for example, ground potential) via the switches SBa and SBb, respectively, and each control terminal connects the switches SBa and SBb. To the contact Ngb connected to the current input contact INi. A capacitor Cb is connected between the contact Ngb and the low potential power supply Vgnd. Each of the unit current transistors TN22 to TN25 has a current path connected between the contacts Nh, Ni, Nj, Nk and the low potential power source -V, and a control terminal commonly connected to the contact Ngb. Each of the switching transistors TN26 to TN29 has a current path connected between the contacts Nh, Ni, Nj, and Nk and the current output contact OUTi, and the data latch unit 10 (latch circuits LC0 to LC0) at the control terminal. The output signals (non-inverted output signals) d10 to d13 output from the LC3) are applied in parallel.

  Here, also in this embodiment, the transistor size of each of the unit current transistors TN22 to TN25 constituting the current mirror circuit unit 21B (that is, the channel width when the channel length is constant) is the same as that of the reference current transistor TN21a or TN21b. As a reference, the unit currents Ish to Isk that are formed to have a predetermined ratio and flow through the respective current paths are set to have different predetermined ratio current values with respect to the reference current Iref.

  Thereby, also in the current generation unit 20B according to the present embodiment, the specific transistor of the switch circuit unit 22B according to the signal level of the output signals d10 to d13 output from the data latch unit 10 (latch circuits LC0 to LC3). TN26 to TN29 are turned on, and unit currents Ish to Isk having a current value that is a predetermined ratio times the reference current Iref flow through the unit current transistors TN22 to TN25, and these combined currents pass through the current output contact OUTi. The load drive current ID is supplied to a load (not shown) (in this embodiment, the load drive current flows from the load side toward the current generation supply circuit).

Therefore, in the current generation and supply circuits ILA and ILB shown in the second and third embodiments described above, constant current is generated in the current generation units 20A and 20B directly connected to the load via the drive current supply line Ld. A constant reference current Iref whose signal level does not vary is supplied from the source IR via the reference current supply line Ls, and a plurality of digital signals d0 to d3 (output signals d10 to d13, d10 ^{* to} d13 ^{* of the} data latch unit 10) ^. ) To generate a load drive current ID having a current value that allows the load to operate in a desired drive state, thereby providing a reference supplied in connection with the generation of the load drive current Since the current is kept constant, when the current value of the load drive current ID is very small, the supply time of the load drive current ID to the load (or the drive time of the load) Even if the current is set to be short, it is possible to eliminate the influence of signal delay due to the charge / discharge operation to the parasitic capacitance such as the wiring capacitance, and to suppress the decrease in the operation speed of the current generation and supply circuit. The load can be operated more quickly and accurately.
In addition, in order to set the current value of the load drive current ID, a reference current Iref having a constant current value is supplied as a current supplied to the current generation and supply circuit, and the signal level of a multi-bit digital signal is applied as it is. Thus, the load drive current ID can be generated by selectively synthesizing a plurality of unit currents, so that it is possible to easily perform drive control (load drive current generation and supply operation) at the time of gradation driving of the load. it can.

  In the second and third embodiments described above, as multi-bit digital signals, display data (display signals) for displaying desired image information on the display device can be applied as will be described later. In this case, the load driving current generated and output by the current generation and supply circuit corresponds to the gradation current supplied to cause each display pixel constituting the display panel to perform a light emission operation with a predetermined luminance gradation. Hereinafter, a display device in which the current generation and supply circuits ILA and ILB having the configurations and functions as described above are applied to a data driver will be specifically described.

<First Embodiment of Display Device>
FIG. 7 is a schematic block diagram showing a first embodiment of a display device to which the current generation and supply circuit according to the present invention can be applied, and FIG. 8 is a schematic diagram showing the main configuration of the display device according to this embodiment. It is a block diagram. Here, a structure including a display pixel corresponding to an active matrix system as a display panel will be described. Further, in the present embodiment, a case where a current application method in which a grayscale current (drive current) is supplied from the data driver side to the display pixel will be described, and the current generation supply circuit (shown in the above-described embodiment) Please refer to FIG. 2 and FIG. 3 as appropriate.

  As shown in FIG. 7 and FIG. 8, the display device 100A according to the present embodiment is roughly arranged with a display panel 110A in which a plurality of display pixels (loads) are arranged in a matrix and in the row direction of the display panel 110A. For each display pixel group, for each display pixel group arranged in the column direction of the display panel 110A, a scanning driver (scanning driving means) 120A connected to the scanning lines (scanning lines) SLa and SLb connected in common. , A data driver (signal driving means) 130A connected to the commonly connected data lines (signal lines) DL1, DL2,... (DL), and various types for controlling operation states of the scanning driver 120A and the data driver 130A. Based on the system controller 140A that generates and outputs the control signal and the video signal supplied from the outside of the display device 100A, the display data and It includes a display signal generation circuit 150A for generating a timing signal, etc., a is configured.

Hereafter, each said structure is demonstrated.
(Display panel 110A)
As shown in FIG. 8, the display panel 110A corresponds to the display pixel group for each row, and corresponds to the pair of scanning lines SLa and SLb arranged in parallel and the display pixel group for each column. At the same time, the data lines DL arranged so as to be orthogonal to the scanning lines SLa, SLb, and a plurality of display pixels arranged in the vicinity of the intersections of these orthogonal lines (in FIG. 8, the pixel driving circuits DCx and A configuration comprising an organic EL element OEL).

The display pixel is, for example, a scanning signal Vsel applied from the scanning driver 120A via the scanning line SLa, a scanning signal Vsel ^* applied via the scanning line SLb (the polarity inversion of the scanning signal Vsel applied to the scanning line SLa). Signal; see the reference numeral in FIG. 8), and the gradation current Ipix write operation in each display pixel based on the gradation current (load drive current) Ipix supplied from the data driver 130A via the data line DL; A pixel driving circuit DCx for controlling the light emitting operation, and a known organic EL element (light emitting element) OEL whose light emission luminance is controlled in accordance with the current value of the light emission driving current supplied from the pixel driving circuit DCx. Configured. In this embodiment, the organic EL element OEL is applied as the light emitting element of the display pixel. However, the present invention is not limited to this, and the current of the light emission driving current supplied to the light emitting element. Other light-emitting elements such as light-emitting diodes may be applied as long as they are current-driven light-emitting elements that emit light with a predetermined luminance gradation according to the value.

Here, the pixel driving circuit DCx roughly controls the selection / non-selection state of each display pixel based on the scanning signals Vsel, Vsel ^* , and takes in the gradation current Ipix corresponding to the display data in the selection state to obtain the voltage level. And the light emission drive current based on the held voltage level in the non-selected state is supplied to the organic EL element OEL to maintain the operation of emitting light at a predetermined luminance gradation. A circuit configuration example applicable to the pixel drive circuit DCx will be described later.

(Scanning driver 120A)
As shown in FIG. 8, the scan driver 120A includes a plurality of stages of shift blocks SB each composed of a shift register and a buffer corresponding to the scan lines SLa and SLb of each row, and a scan control signal (scan) supplied from the system controller 140A. Based on the start signal SSTR, the scanning clock signal SCLK, and the like, a shift signal that is sequentially shifted from the upper side to the lower side of the display panel 110A by the shift register is output through a buffer to a predetermined voltage level (selection level; for example, Is applied to each scanning line SLa as a scanning signal Vsel having a high level, and a voltage level obtained by inverting the polarity of the scanning signal Vsel is applied to each scanning line SLb as a scanning signal Vsel ^* . As a result, the display pixel group for each row is selected, and the gradation current Ipix based on the display data supplied from the data driver 130A via each data line DL is controlled to be written to each display pixel.

(Data driver 130A)
As shown in FIG. 8, the data driver 130A includes a plurality of data signals supplied from the display signal generation circuit 150A based on data control signals (a shift start signal STR, a shift clock signal SFC, etc. described later) supplied from the system controller 140A. The display data composed of bit digital signals is captured and held, a gradation current Ipix having a current value corresponding to the display data is generated, and set to the selected state by the scan driver 120A via each data line DL. Control is performed so as to supply each display pixel in parallel. The specific circuit configuration and drive control operation of the data driver 130A will be described in detail later.

(System controller 140A)
Based on a timing signal supplied from a display signal generation circuit 150A, which will be described later, the system controller 140A sends at least a scan control signal (scan start signal SSTR and scan clock described above) to each of the scan driver 120A and the data driver 130A. Signal SCLK and the like) and data control signals (the shift start signal STR and the shift clock signal SFC and the like described above) are generated and output, so that each driver is operated at a predetermined timing, and the display panel 110A receives the scanning signal Vsel, Vsel ^* and gradation current Ipix are output, and predetermined control operation (details will be described later) in the pixel drive circuit DCx is continuously executed to display predetermined image information based on the video signal on the display panel 110A. Take control.

(Display signal generation circuit 150A)
For example, the display signal generation circuit 150A extracts a luminance gradation signal component from a video signal supplied from the outside of the display device 100A, and converts the luminance gradation signal component into a plurality of bits for each row of the display panel 110A. Is supplied to the data driver 130A as display data comprising the digital signal. Here, when the video signal includes a timing signal component that defines the display timing of image information, such as a television broadcast signal (composite video signal), the display signal generation circuit 150A displays the luminance gradation signal component. In addition to the function of extracting the timing signal component, the timing signal component may be extracted and supplied to the system controller 140A. In this case, the system controller 140A generates the scan control signal and the data control signal supplied to the scan driver 120A and the data driver 130A based on the timing signal supplied from the display signal generation circuit 150A.

  In the present embodiment, the mounting structure of the display panel 110A and peripheral circuits such as drivers and controllers attached around the display panel 110A is not particularly limited. For example, at least the display panel 110A and the scan transistor 120A are provided. The data driver 130A may be formed on a single substrate, or only the data driver 130A described later, or the scanning driver 120A and the data driver 130A are provided separately from the display panel 110A. An electrical connection may be used.

(First configuration example of data driver)
Next, a configuration of a data driver applied to the display device described above will be described.
The data driver 130A applied to the display device 100A according to the present embodiment is roughly configured such that the current generation supply circuit ILA (data latch unit 10, current generation unit 20A) illustrated in FIG. 2 corresponds to each data line DL. Provided individually as a gradation current generation circuit, for each gradation current generation circuit, for example, from a single constant current generation source (constant current source) IR via a common reference current supply line A reference current Iref having a current value is supplied (in this embodiment, the reference current Iref is supplied so as to be extracted).

  For example, as shown in FIG. 8, the data driver 130A according to the present embodiment shifts the shift start signal STR based on a shift clock signal SFC supplied as a data control signal from the system controller 140A, and performs a predetermined timing. Shift signal SR1, SR2, SR3,... (Corresponding to the timing control signal CLK described above) sequentially, and shift signals SR1, SR2, SR3,... From the shift register circuit 131A,. The display data D0 to Dq for one row sequentially supplied from the display signal generation circuit 150A based on the output timing (1) (here, the digital signal input to the current generation supply circuit ILA shown in FIGS. 2 and 3) corresponding to d0 to d3, q = 3 for convenience) A gray scale current generation circuit PXA1, PXA2 that generates a gray scale current Ipix corresponding to the light emission luminance in the indicated pixel and supplies the gray scale current Ipix to each data line (corresponding to the drive current supply line Ld) DL1, DL2,. , PXA3,... (Corresponding to the above-described current generation supply circuit ILA; hereinafter also referred to as “gradation current generation circuit PXA” for convenience) and the outside of the data driver 130A. Constant current generation for constantly supplying a reference current Iref having a constant current value to each gradation current generation circuit PXA1, PXA2, PXA3,... Via a common reference current supply line Ls. And a source IR.

  Here, each of the grayscale current generation circuits PXA1, PXA2, PXA3,... Has a data latch unit (signal holding means) 101, 102, 103, which is equivalent to the above-described current generation supply circuit ILA (FIGS. 2 and 3). , And current generation units (current generation means) 201, 202, 203,..., And based on control signals CNT (switching control signals CNa, CNb) supplied as data control signals from the system controller 140A. The reference current transistors (not shown; refer to FIG. 3) provided in each of the current generators 201, 202, 203... Are controlled so as to change the gradation for the designated gradation based on the display data D0 to D3. The current characteristic of the current Ipix is changed and set.

  In this embodiment, the reference current Iref is shared from a single constant current generation source IR to all the gradation current generation circuits PXA1, PXA2, PXA3,... Provided in the data driver 130A. Although the structure to be supplied is shown, the present invention is not limited to this. For example, when a plurality of data drivers are provided for the display panel, a constant current corresponding to each data driver is provided. A generation source may be provided individually, or a constant current generation source may be provided for each of a plurality of gradation current generation circuits provided in a single data driver.

(First configuration example of display pixel)
Next, a pixel drive circuit applied to each display pixel of the display device (display panel 110A) described above will be briefly described.
FIG. 9 is a circuit configuration diagram showing a first example of a display pixel (pixel drive circuit) applied to this embodiment. Note that the pixel driving circuit shown here is merely an example applicable to a display device employing a current application method, and other circuit configurations having equivalent functions may be applied. Needless to say.

  As shown in FIG. 9, the pixel driving circuit DCx according to the present embodiment has a gate terminal at the scanning line SLa, a source terminal and a drain terminal at the power contact Vdd near the intersections of the scanning lines SLa, SLb and the data line DL. And a p-channel transistor Tr31 connected to the contact Nxa, a gate terminal connected to the scanning line SLb, a p-channel transistor Tr32 connected to the data line DL and the contact Nxa, respectively, and a gate terminal A p-channel transistor Tr33 having a source terminal and a drain terminal connected to the contact Nxa and the contact Nxc, a gate terminal connected to the scanning line SL, and a source terminal and a drain terminal connected to the contact Nxb and the contact Nxc, respectively, to the contact Nxb. N-channel transistor Tr34 is connected between contact Nxa and contact Nxb. And it has capacitor and (storage capacitor) Cx, a configuration with a. Here, the power contact Vdd is connected to a high potential power supply via a power supply line (not shown), for example, and a constant high potential voltage is applied constantly or at a predetermined timing.

  Further, in such an organic EL element OEL in which the light emission luminance is controlled by the light emission drive current supplied from the pixel drive circuit DCx, the anode terminal is at the contact Nxc of the pixel drive circuit DCx and the cathode terminal is at a low potential power source (for example, , And ground potential Vgnd). Here, the capacitor Cx may be a parasitic capacitance formed between the gate and the source of the transistor Tr33, or in addition to the parasitic capacitance, a capacitive element is separately added between the gate and the source. It may be a thing.

The drive control operation of the organic EL element OEL in the pixel drive circuit DCx having such a configuration is as follows. First, in the write operation period, for example, a high level (selection level) scan signal Vsel is applied to the scan line SLa, and A low level scanning signal Vsel ^* is applied to the scanning line SLb, and in synchronization with this timing, a gradation current Ipix for causing the organic EL element OEL to emit light at a predetermined luminance gradation is supplied to the data line DL. Here, a positive current is supplied as the gradation current Ipix, and the current is supplied (applied) from the data driver 130A side to the display pixel (pixel drive circuit DCx) via the data line DL. To do.

  As a result, the transistors Tr32 and Tr34 constituting the pixel drive circuit DCx are turned on, and the transistor Tr31 is turned off, so that a positive potential corresponding to the gradation current Ipix supplied to the data line DL is applied to the contact Nxa. Is done. Further, the contact Nxb and the contact Nxc are short-circuited, and the gate and drain of the transistor Tr33 are controlled to the same potential, so that the transistor Tr33 is turned off and both ends of the capacitor Cx (between the contact Nxa and the contact Nxb). Causes a potential difference corresponding to the gradation current Ipix, and charges corresponding to the potential difference are accumulated and held (charged) as voltage components.

Next, in the light emission operation period, a low level (non-selection level) scanning signal Vsel is applied to the scanning line SLa, and a high level scanning signal Vsel ^* is applied to the scanning line SLb. The supply of the regulating current Ipix is cut off. As a result, the transistors Tr32 and Tr34 are turned off and the data line DL and the contact Nxa are electrically disconnected, and the contact Nxb and the contact Nxc are electrically disconnected, so that the capacitor Cx is accumulated in the above-described write operation. Hold the charge.

  In this way, the capacitor Cx holds the charging voltage during the writing operation, whereby the potential difference between the contact Nxa and the contact Nxb (between the gate and the source of the transistor Tr33) is held, and the transistor Tr33 is turned on. Operate. Further, since the transistor Tr31 is simultaneously turned on by the application of the scanning signal Vsel (low level), the gradation current Ipix (from the power supply contact (high potential power supply) Vdd to the organic EL element OEL via the transistors Tr31 and Tr33). More specifically, a light emission drive current corresponding to the charge held in the capacitor Cx flows, and the organic EL element OEL emits light with a predetermined luminance gradation. Thus, in the pixel drive circuit DCx according to the present embodiment, the transistor Tr33 has a function as a light emission drive transistor.

<Display device drive control method>
Next, the operation of the display device having the above-described configuration will be described with reference to the drawings.
FIG. 10 is a timing chart showing an example of the control operation in the data driver according to the present embodiment, and FIG. 11 is a timing chart showing an example of the control operation in the display panel (display pixel) according to the present embodiment. FIG. 12 is a characteristic diagram showing an example of the light emission luminance (gradation-luminance characteristic) of the display pixel with respect to the designated gradation in the display device according to the present embodiment. Here, in addition to the configuration of the data driver shown in FIG. 8, the configuration of the current generation and supply circuit shown in FIGS.

(Data driver control operation)
The control operation in the data driver 130 is first supplied from the display signal generation circuit 150A to the data latch units 101, 102, 103,... Provided in each gradation current generation circuit PXA1, PXA2, PXA3,. The display data D0 to D3 to be captured and held, and an output signal (inverted output signal) based on the display data D0 to D3 is output for a certain period, and the data latch units 101, 102, 103,. Are generated by the current generators 201, 202, 203,... Corresponding to the display data D0 to D3, and the data lines DL1, DL2, DL3,. And a current generation / supply operation for individually supplying each display pixel (pixel drive circuit DCx) via the.

  Here, in the signal holding operation, as shown in FIG. 10, each of the data latch units 101, 102, 103 is based on the shift signals SR1, SR2, SR3,... Sequentially output from the shift register circuit 131. ,..., The operation of sequentially fetching display data D0 to D3 switching corresponding to the display pixels in each column (that is, each data line DL1, DL2, DL3,...) Is continuously executed for one row. The state in which output signals are output to the current generators 201, 202, 203,... In order from the data latch units 101, 102, 103,. A period (for example, a period until the next high level shift signals SR1, SR2, SR3,... Are output) is held.

  In the current generation and supply operation, a plurality of current generation units 201, 202, 203,... Provided on the basis of output signals output from the data latch units 101, 102, 103,. ON / OFF states of the switch transistors (switch transistors TP16 to TP19 shown in FIG. 3) are controlled, and the units flow to the unit current transistors (transistors TP12 to TP15 shown in FIG. 3) connected to the switch transistors that are turned on. A combined current of the currents is sequentially supplied as the gradation current Ipix through the data lines DL1, DL2, DL3,.

  At this time, in the data driver 130A according to the present embodiment, as described above, each current of each gradation current generation circuit PXA is based on the control signal CNT (switching control signals CNa and CNb) output from the system controller 140. .. By selectively switching a plurality of (two in the current generation and supply circuit shown in FIG. 3) reference current transistors provided in the generation units 201, 202, 203,... A plurality of unit current ratios with respect to the reference current Iref are set in accordance with the channel width. For example, by operating the control signal CNT prior to the signal holding operation, an arbitrary gradation-current characteristic is obtained. A gradation current Ipix is generated and supplied.

Here, for example, the gradation current Ipix is set so as to be supplied in parallel for at least a fixed period to all the data lines DL1, DL2, DL3,. Further, in the present embodiment, as described above, a predetermined ratio (for example, a × 2 ^k ; k = 0, 1, 2, 3,...) Defined in advance by the transistor size with respect to the reference current Iref. A plurality of unit currents having a current value of 1 are generated, and the switch transistor is turned on / off based on the inverted output signal, whereby a predetermined unit current is selected and synthesized, and the positive polarity gradation current Ipix is obtained. The gradation current Ipix is generated so as to flow in the direction of the data lines DL1, DL2, DL3,... From the data driver 130 side.

  In the data driver 130A according to the present embodiment, as shown in FIG. 8, the common reference current supply line Ls to which the reference current Iref having a constant current value is supplied from the constant current generation source IR. , A plurality of gradation current generation circuits PXA1, PXA2, PXA3,... Are connected in parallel, and as shown in FIG. 10, each gradation current generation circuit PXA1, PXA2, PXA3,. In FIG. 5, since the gradation current Ipix to be supplied to each data line DL1, DL2, DL3,... (Display pixel) is generated in parallel at the same time based on the display data D0 to D3, the reference current supply line Ls The current supplied to each of the gradation current generation circuits PXA1, PXA2, PXA3,... Is not the reference current Iref itself supplied by the constant current generation source IR, but the gradation current generation circuit. The current having a current value (Iref / m) that is substantially equally divided is supplied according to the number of data lines (ie, corresponding to the number of data lines arranged on the display panel 110; for example, m). become.

  Therefore, the current ratio of each unit current to the reference current Iref set in the current mirror circuit unit constituting the current generation unit 201, 202, 203,... Of each gradation current generation circuit PXA1, PXA2, PXA3,. (Ie, the ratio of the channel width of the unit current transistor to the reference current transistor) in consideration of the current value (Iref / m) supplied to each of the gradation current generation circuits PXA1, PXA2,. The ratio may be set to m times the ratio in the circuit configuration shown in FIG.

  As another configuration, each of the gradation current generation circuits PXA1, PXA2, PXA3,... Is selectively selected based on, for example, the shift signals SR1, SR2, SR3,. The switching means for turning on is provided, and each of the current generators 201, 202, 203,... Has the constant current only during the period of the current generation and supply operation in which the gradation current Ipix is generated based on the display data D0 to D3. The reference current Iref from the generation source IR may be selectively supplied to each gradation current generation circuit PXA1, PXA2, PXA3,.

(Control operation of display panel 110)
As shown in FIG. 11, the control operation in the display panel 110A (display pixel) is performed within one scanning period Tsc, with one scanning period Tsc for displaying desired image information on one screen of the display panel 110A as one cycle. A write operation period (selection) in which a display pixel group connected to a specific scanning line is selected, and the gradation current Ipix corresponding to the display data D0 to D3 supplied from the data driver 130A is written and held as a signal voltage. Period) based on the Tse and the held signal voltage, a light emission operation period corresponding to the display data is supplied to the organic EL element OEL to perform a light emission operation at a predetermined luminance gradation (of the display pixel). (Non-selection period) Tnse is set (Tsc = Tse + Tnse), and in each operation period, drive control equivalent to the above-described pixel drive circuit DCx is executed. Here, the write operation period Tse set for each row is set so that there is no time overlap. Further, the write operation period Tse is set to a period including at least a certain period in which the gradation current Ipix is supplied in parallel to the data lines DL in the current generation supply operation in the data driver 130A.

That is, in the writing operation period Tse to the display pixels, as shown in FIG. 11, the scanning lines SLa and SLb are set to predetermined signal levels by the scanning driver 120A with respect to the display pixels in a specific row (i-th row). , The gradation current Ipix supplied in parallel to each data line DL by the data driver 130A is simultaneously held as a voltage component, and in the subsequent light emission operation period Tnse, the write operation is performed. By continuously supplying the light emission drive current based on the voltage component held in the operation period Tse to the organic EL element OEL, the operation of emitting light at the luminance gradation corresponding to the display data is continued.
As shown in FIG. 11, a series of drive control operations as described above are sequentially executed for the display pixel groups of all the rows constituting the display panel 110A, whereby display data for one screen of the display panel is written. Each display pixel emits light with a predetermined luminance gradation, and desired image information is displayed.

  Therefore, according to the data driver and the display device according to the present embodiment, the gradation current generation circuits PXA1, PXA2, PXA3,... Are supplied to the display pixel group in a specific row via each data line DL. The adjustment current Ipix is a display composed of a constant reference current Iref supplied from a single constant current generation source IR (via a common reference current supply line Ls) and a digital signal having a plurality of bits. Since it is generated based on the data D0 to D3, when the display pixel is operated to emit light with a relatively low luminance gradation (when the current value of the gradation current Ipix is very small), or with higher definition of the display panel, etc. Even when the supply time (selection time) of the gradation current Ipix to the display pixel is set short, the data driver (each gradation current generation circuit PXA1) is related to the generation of the gradation current Ipix. PXA2, PXA3,...)) Can be eliminated to suppress a decrease in the operation speed of the data driver, and the gradation current generation circuits PXA1, PXA2, PXA3,. .. Can be made uniform to improve display response characteristics and display image quality in the display device.

  Further, in this case, the current characteristics of the gradation current Ipix individually supplied to the data lines DL1, DL2, DL3,... From the gradation current generation circuits PXA1, PXA2, PXA3,. Therefore, as in the case shown in FIG. 4, for example, as shown in FIG. 12, in the display pixel (light emitting element) for the gradation specified based on the display data, as shown in FIG. Two types (Ea, Eb) of gradation-luminance characteristics (light emission characteristics) representing changes in the emission luminance (that is, the current value of the gradation current Ipix) can be set. Without changing and controlling the current Ipix and the display data D0 to D3, the switching can be easily set by operating only the control signal CNT.

  Therefore, for example, when an electronic device including the display device according to the present embodiment is used under conditions of relatively low environmental illuminance, such as indoors, as shown in the luminance characteristic Ea in FIG. When the electronic device is used under a high environmental illuminance condition, such as outdoors, as shown by the luminance characteristic Eb in FIG. By setting the gradation-luminance characteristics of the display pixel to a state that changes sharply, the display pixel can be operated to emit light at an appropriate emission luminance according to the ambient illuminance, so that desired image information can be displayed with high visibility. Can be displayed.

  In the above-described embodiment, the configuration corresponding to the current application method is shown as the data driver and the display pixel (pixel driving circuit). However, the present invention is not limited to this, and FIGS. The current generation and supply circuit ILB shown in FIG. 5 is applied to the gradation current generation circuit, and has a configuration corresponding to the current sink method for supplying the gradation current Ipix from the display pixel side in the data driver direction. Needless to say, it may be.

<Second Embodiment of Display Device>
Next, a second embodiment of a display device to which the current generation and supply circuit according to the present invention can be applied will be briefly described.
(Second configuration example of data driver)
FIG. 13 is a schematic configuration diagram illustrating a second example of the data driver applied to the display device according to the second embodiment. Here, about the structure equivalent to embodiment mentioned above, an equivalent code | symbol is attached | subjected and the description is simplified or abbreviate | omitted.

  In general, the data driver applied to the display device according to the present embodiment is provided with two sets of gradation current generation circuits each having a basic configuration of the current generation supply circuit ILA shown in FIG. Each set of gradation current generation circuits is configured to execute display data fetching and holding, generation of gradation current, and supply operation in a complementary and continuous manner at the operation timing. Here, the present configuration example is configured such that a negative reference current Iref having a constant current value is supplied from a single constant current generation source to each of the two groups of gradation current generation circuit groups. Has been.

  As shown in FIG. 13, the data driver 130B according to the present embodiment specifically includes a non-inverted clock signal CKa and a non-inverted clock signal CKa based on a shift clock signal SFC supplied as a data control signal from a system controller (not shown). Based on the inversion latch circuit 133B that generates the inversion clock signal CKb, and the non-inversion clock signal CKa and the inversion clock signal CKb, the sampling start signal STR is shifted, and the shift signals SR1, SR2,. The shift register circuit 131B that sequentially outputs the timing control signal CLK described above; hereinafter also referred to as “shift signal SR” for convenience, and the shift signals SR1, SR2,. Display not shown based on input timing Gradation-current characteristics (or gradations) set on the basis of a control signal CNT supplied as a data control signal from the system controller by sequentially fetching display data D0 to D3 for one row sequentially supplied from the signal generation circuit In accordance with (luminance characteristics), two sets of gradation currents are generated and supplied (applied) via the data lines DL1, DL2,... Selection setting for selectively operating one of the gradation current supply circuit groups 132B and 132C based on the supply circuit groups 132B and 132C and the switching control signal SEL supplied as a data control signal from the system controller. Selection setting circuit 134B for outputting signals (non-inverted signal SLa and inverted signal SLb of switching control signal SEL), and a grayscale current supply circuit group , And PXC-1, PXC-2,... (Hereinafter also referred to as “gradation current supply circuit units PXB, PXC”). ) And a constant current generation source IR that supplies a constant reference current Iref through a common reference current supply line Ls (supplying and extracting a negative current).

(Gradation current generation circuit PXB, PXC)
FIG. 14 is a configuration diagram showing a specific example of the gradation current generating circuit applied to the data driver according to this embodiment, and FIG. 15 shows the gradation current supply circuit applied to this embodiment. It is a block diagram which shows one specific example of an electric current generation part. Here, the description will be made in association with the configuration of the above-described current generation and supply circuit (FIGS. 2 and 3). Moreover, about the structure equivalent to embodiment mentioned above, an equivalent code | symbol is attached | subjected and the description is simplified or abbreviate | omitted.

  As shown in FIG. 14, each of the gradation current generation circuits PXB and PXC constituting the gradation current generation circuit group 132B and 132C includes the current generation supply circuit ILA (data latch unit 10 and current generation unit 20A) shown in FIG. And the grayscale current generation circuits PXB and PXC based on the selection setting signal (non-inverted signal SLa or inverted signal SLb) output from the selection setting circuit 134B. And an operation setting unit 40C for selectively setting the operation state.

  Here, as shown in FIG. 15, the current generation unit 20C includes p-channel transistors TP61a, TP61b, TP62 to TP65 that constitute the current mirror circuit unit 21C, and switches as in the current generation unit shown in FIG. In addition to the p-channel transistors TP66 to TP69 constituting the circuit unit 22C, a current is generated based on a timing control signal (corresponding to the non-inverted clock signal CLK shown in FIG. 2) CK output from an operation setting unit 40C described later. The circuit configuration includes a refresh control transistor (refresh means) Tr60 composed of an n-channel transistor that controls the conduction state between the input contact INi and the contact Ngc.

  That is, by the refresh control transistor Tr60, the charge based on the reference current Iref is supplied to the contact Ngc at the timing when the timing control signal (non-inverted clock signal) CK output from the operation setting unit 40C becomes high level, and the capacitor Cc And the voltage of the contact Ngc (that is, the reference voltage applied to the gate terminals of the unit current transistors TP66 to TP69) is recharged (refreshed) to a constant voltage. The reference voltage refresh operation will be described later.

  As shown in FIG. 14, the operation setting unit 40C applied to the gradation current generation circuits PXC and PXD according to the present embodiment has a selection setting signal (non-inverted signal SLa or inverted signal SLb) output from the selection setting circuit 134B. ), A p-channel transistor TP41 in which a current path is provided in the data line DL, and an inverted signal of the selection setting signal (output signal of the inverter 42) is applied to the control terminal, and a selection setting signal A NAND circuit 43 that receives the inverted signal of the non-inverted signal SLa or the inverted signal SLb and the shift signal SR from the shift register circuit 131B, an inverter 44 that inverts the logic output of the NAND circuit 43, and the inverter 44 The inverter 45 that further inverts the inverted output of the reference current Iref and the supply current of the reference current Iref to the current generator 20C Current path has provided a current supply control transistor TP46 comprising a p-channel transistor to which an output signal of the inverter 45 is applied to the control terminal, a configuration with the.

In the gradation current supply circuit units PXB and PXC having such a configuration, a selection setting signal (non-inverted signal SLa or inverted signal SLb) of the selection level (high level) is input from the selection setting circuit 134B to the operation setting unit 40C. Then, when the signal polarity is inverted and applied by the inverter 42, the p-channel transistor TP41 is turned on, and the current output contact OUTi of the current generator 20C is connected via the p-channel transistor TP41. Connected to the data line DL. At the same time, a low-level timing control signal (non-inverted clock signal) is applied to the non-inverted input contact CK of the data latch unit 10 by the NAND circuit 43 and the inverters 44 and 45 regardless of the output timing of the shift signal SR. The high-level timing control signal (inverted clock signal) is constantly input to the inverting input contact CK ^* and the control terminal of the p-channel transistor TP46, and the display data D0 to D3 held in the data latch unit 10 Inverted output signals d10 ^{* to} d13 ^* based on are supplied to the gradation current generation unit 20C and the supply of the reference current Iref to the gradation current generation unit 20C is cut off.

On the other hand, when a selection setting signal (non-inverted signal SLa or inverted signal SLb) of a non-selection level (low level) is input from the selection setting circuit 134B, the signal polarity is inverted by the inverter 42 and applied. The p-channel transistor TP41 is turned off, and the current output contact OUTi of the gradation current generator 20C is disconnected from the data line DL. At the same time, a high-level timing control signal is applied to the non-inverting input contact CK of the data latch unit 10 in accordance with the output timing of the shift signal SR by the NAND circuit 43 and the inverters 44 and 45. A low-level timing control signal is input to the contact CK ^* and the control terminal of the p-channel transistor TP46, the display data D0 to D3 are fetched and held in the data latch unit 10, and the reference current Iref is stored in the current generator 20C. Is supplied.

Thus, when a selection setting signal of a selection level is input, the current generation unit 20C according to the display data D0 to D3 based on the inverted output signals d10 ^{* to} d13 ^* output from the data latch unit 10. The gradation current Ipix is generated and supplied to the display pixel via the data line DL, and the gradation current supply circuit PXB or PXC is set to the selected state. On the other hand, when the selection setting signal of the non-selection level is input, the display data D0 to D3 are fetched and held in the data latch unit 10, but the gradation current Ipix is not generated and supplied to the data line DL. As a result, the gradation current supply circuit PXB or PXC is set to a non-selected state. In this non-selected state, a refresh operation is performed in which the reference current Iref is supplied to the gradation current generator 20C, and the potential of the gate terminal (contact Ngc) of the reference current transistor TP61a or TP61b is recharged to a predetermined voltage. Executed.

  Therefore, the signal level of the selection setting signal (the non-inverted signal SLa or the inverted signal SLb of the switching control signal SEL) input to the two sets of gradation current supply circuit groups 132B and 132C is appropriately set by the selection setting circuit 134B described later. Thus, one of the two sets of gradation current supply circuit groups 132B and 132C can be set to the selected state, and the other can be set to the non-selected state.

(Inverted latch circuit 133B / selection setting circuit 134B)
In general, when the shift clock signal SFC or the switching control signal SEL is applied to the inverting latch circuit 133B or the selection setting circuit 134B, the signal level is held, and the non-inverted signal and the inverted signal of the signal level are respectively non-inverted. Output from the inverting output terminal and the inverting output terminal, to the shift register circuit 131B as a non-inverted clock signal CKa and an inverted clock signal CKb, and a gradation current generation circuit group 132B (each gradation current generation circuit PXB1, PXB2,. ..) And 132C (each gradation current supply circuit unit PXC1, PXC2,...) Are supplied as a non-inverted signal SLa and an inverted signal SLb (selection setting signal).

(Shift register circuit 131B)
The shift register circuit 131B takes in the shift start signal STR supplied from the system controller based on the non-inverted clock signal CKa and the inverted clock signal CKb output from the inversion latch circuit 133B described above, and sequentially shifts them at a predetermined timing. The shift signals SR1, SR2,... Are output to the gradation current generation circuit groups 132B and 132C.

(Data driver control operation)
FIG. 16 is a timing chart illustrating an example of a control operation in the data driver according to the present embodiment.
The control operation in the data driver 130B as described above is performed by inputting display data D0 to D3 to the data latch unit 10 of the gradation current supply circuit PXB or PXC by inputting a selection setting signal of a non-selection level (low level). In the signal holding operation period for capturing and holding, both the refresh control transistor Tr60 provided in the current mirror circuit unit 21C and the current supply control transistor TP46 provided in the operation setting unit 40C are turned on, whereby the reference A reference current Iref flows through the current path of the current transistor TP61a or TP61b, and a charge based on the reference current Iref is supplied to the gate terminal and the contact Ngc of the reference current transistor TP61a or TP61b. As a result, the charge is accumulated (charged) in the capacitor Cc, and the potential of the gate terminal (reference voltage Vref) is refreshed to a predetermined voltage. At this time, since the p-channel transistor TP41 provided in the operation setting unit 40C is in the OFF state, the current generation unit 20 does not generate the gradation current and supply it to the data line DL.

  Further, by inputting a selection setting signal of a selection level (high level) to the data driver 130B, a gradation current is generated in the gradation current supply circuits PXB and PXC based on the captured and held display data D0 to D3. In the current generation and supply operation period to be supplied, both the refresh control transistor Tr60 and the current supply control transistor TP46 are turned off, so that the supply of charge to the gate terminal and the contact Ngc of the reference current transistor TP61a or TP61b is cut off. Is done.

  At this time, since the potential (reference voltage) of the contact Ngc is held at a predetermined voltage by the voltage component charged in the capacitor Cc, the gradation current supply circuits PXB and PXC are based on the display data D0 to D3. By selectively synthesizing unit currents flowing through the unit current transistors, a gradation current Ipix having a desired current value is generated. Accordingly, the gradation current Ipix having a current value corresponding to the display data D0 to D3 is continuously supplied from the gradation current supply circuits PXB and PXC to each display pixel via the data line DL.

  That is, as shown in FIG. 16, such a signal holding operation and a current generation / supply operation are alternately and repeatedly executed by the two sets of gradation current generation circuit groups 132B and 132C at a predetermined cycle, for example, In the non-selection period of the grayscale current generation circuit group 132B, while performing a signal holding operation for capturing the display data D0 to D3, at the same time, in the selection period set for the other grayscale current generation circuit group 132C, The gradation current Ipix based on the display data D0 to D3 captured at the timing is generated and the current generation and supply operation to be supplied is executed in parallel.

  Next, in the selection period of one gradation current generation circuit group 132B, the current generation supply operation based on the display data D0 to D3 captured in the previous non-selection period is executed, and at the same time, the other gradation current generation circuit In a non-selection period set for the group 132C, a series of operations for executing a signal holding operation for fetching the next display data D0 to D3 are alternately performed.

  Therefore, each data line is provided with two sets of gradation current generation circuits (groups), and the operation state of each gradation current generation circuit is alternately and repeatedly executed so that the data driver continues to each display pixel. In addition, since the gradation current having a current value appropriately corresponding to the display data can be supplied, the display pixel can be quickly lit at a predetermined luminance gradation, and the display response speed of the display device and The display image quality can be further improved.

  Further, the potential (reference voltage) applied to the gate terminals (contacts Ngc) of the unit current transistors TP62 to TP65 constituting the gradation current supply circuits PXB and PXC (current generation unit 20C) is periodically set to a predetermined constant. Since the voltage can be recharged (refreshed), it is possible to suppress a decrease in the reference voltage due to current leakage or the like in the unit current transistor, and the gradation current (that is, due to the variation in the conduction state of each unit current transistor) Further, it is possible to suppress a phenomenon in which the luminance gradation of the display pixel) is nonuniform and to realize a favorable gradation display operation (improvement of display image quality).

  Further, also in the display device (data driver) according to the present embodiment, the gradation current Ipix generated by the gradation current generation circuits PXB and PXC based on the control signal CNT (CNa and CNb) output from the system controller. In the same manner as shown in FIG. 12, two types of gradation-luminance characteristics representing changes in light emission luminance with respect to the designated gradation in the display pixel (light-emitting element) are set by controlling the gradation-current characteristics of the display pixels. Therefore, by appropriately switching and setting these gradation-luminance characteristics, it is possible to cause the display pixels to perform a light emission operation with an appropriate light emission luminance according to the use environment (environmental illuminance) of the display device. Information can be displayed with good visibility.

<Third Embodiment of Display Device>
Next, a third embodiment of the display device according to the present invention will be described.
In each of the above-described embodiments, a plurality of reference current transistors having different transistor sizes are provided, and these are appropriately selectively switched and controlled (that is, at the gate terminal of each reference current transistor with respect to a constant reference current Iref). By controlling the generated voltage to be different), the current value of the unit current (current ratio to the reference current) generated corresponding to the multi-bit digital signal based on the display data is set differently. The configuration and the control method for changing and setting the current characteristic of the gradation current with respect to the tone and the luminance characteristic of the light emitting element have been described. In the present invention, such a technical idea is applied to red (R ), Green (G), and blue (B), applied to a gradation current generation circuit provided corresponding to each light emitting element, and gradation-luminance characteristics It can also be optimized. This will be specifically described below.

  FIG. 17 is a circuit configuration diagram illustrating an example of a gradation current generation circuit (current generation unit) applied to the display device according to the third embodiment. FIG. 18 illustrates a gradation configuration according to the present embodiment. It is a partial circuit diagram which shows the reference current transistor part applied to a current generation circuit. Further, FIG. 19 is a characteristic diagram showing current-luminance characteristics and gradation-luminance characteristics in each of the RGB emission colors of the light-emitting element applied to the display device according to the present embodiment, and FIG. It is a characteristic diagram which shows the gradation-luminance characteristic in each luminescent color of RGB of the light emitting element which concerns, and a figure which shows the setting concept of white balance. Here, a configuration in which the technical idea according to the present invention is applied to the current generation section of the current generation and supply circuit shown in FIG. 3 is shown, and the equivalent configuration will be described with the same or equivalent reference numerals.

  As shown in FIG. 17, the current generator 20D applied to the grayscale current generator according to the present embodiment has a high potential power supply + V and a current input contact INi substantially the same as the current generator 10A shown in FIG. A reference current transistor portion STD provided with a reference current transistor TP71 and a capacitor Cd, a current mirror circuit portion 21D including a plurality of unit current transistors TP72 to TP75, and a switch including p-channel transistors TP76 to TP79. And a circuit portion 22D.

  Here, the reference current transistor TP71 constituting the reference current transistor unit STD has, for example, the emission color according to the emission color emitted from the light emitting element based on the gradation current Ipix generated by the current generation unit 20D. As shown in FIG. 18A, a circuit configuration including a p-channel transistor TP71r with a relatively short channel width is applied, and when the emission color is blue, as shown in FIG. As shown in FIG. 18C, a circuit configuration including a p-channel transistor TP71b having a relatively long channel width is applied, and when the emission color is green, the circuit configuration shown in FIG. As shown, the p-channel is set to the channel width between the reference current transistors (p-channel transistors TP71r, TP71b) corresponding to the red and blue colors. Circuit configurations with transistors TP71g is applied.

As a result, the channel width of the reference current transistor can be individually set according to the emission color of each light emitting element, so that the current ratio of each unit current to the reference current is optimized for the current-luminance characteristics of each light emitting element. It is possible to arbitrarily change and set to a state that can be converted into a state.
That is, in general, current-luminance characteristics (light emission luminance with respect to a specified current) in a light emitting element that emits each color of RGB are as shown in FIG. 19A in which the current value of the drive current supplied to the light emitting element increases. Along with this, it is known that the emission luminance increases with linearity, and the inclinations indicating the change tendency of the emission luminance in each color are different. In the example of the current-luminance characteristic shown in FIG. 19A, when a drive current having the same current value is supplied to the light emitting element, the green light emission luminance is high (characteristic line Sg) and is recognized extremely brightly. On the other hand, the blue light emission luminance is relatively low (characteristic line Sb) and is recognized as dark.

  For this reason, a gray-scale current generation circuit (current generation unit) provided individually corresponding to each of the RGB color light-emitting elements due to the color dependence of the current-luminance characteristics of such light-emitting elements is shown in FIG. In the current generating unit 20D having such a current mirror circuit, a circuit configuration in which the reference current transistor unit STD includes the reference current transistor TP71 having the same channel width (that is, the reference current transistor TP71 and the unit current transistors TP72 to TP75 have the same channel width). When the same circuit configuration in which the channel width ratio is fixed is applied, as shown in FIG. 19B, the light emission luminance (gradation− The luminance characteristic) tends to be different for each color. In FIG. 19B, SErp indicates the luminance characteristic in the red light emitting element, SErg indicates the luminance characteristic in the green light emitting element, and SErb indicates the luminance characteristic in the blue light emitting element.

  In the case where the gray-scale current generation circuit having the same circuit configuration corresponding to the light emitting elements of each RGB color is individually applied as described above, white light emission is realized by mixing RGB three colors. As shown in FIG. 19B, the designated gradation of each color is set based on the ratio (white balance) of the light emission luminance of each color component constituting white light. That is, the emission luminance EPrw of the other two colors (red and green) based on the emission luminance EPbw of the blue light emitting element having the lowest emission luminance at the highest gradation (the 15th gradation in FIG. 19B), EPgw is controlled to emit light at each specific (different from each other) designated gradation at which the predetermined ratio is obtained, thereby defining the maximum value of the white light emission luminance EPw.

  Therefore, gradation control in each color of RGB for obtaining white balance for realizing good white light becomes complicated, and the maximum value of white light emission luminance is the lowest at the highest gradation. It is defined based on the gradation-luminance characteristics of the light-emitting element of the color component, and the setting range of the light emission luminance of white light is relatively narrow (the maximum value of the light emission luminance of white light is defined to be relatively low). Had a problem.

  Therefore, in the current generation and supply circuit according to the present embodiment, as shown in FIG. 20, each light emission luminance at the highest gradation (fifteenth gradation) of each RGB color is a ratio at which a good white balance can be obtained. In this manner, the gradation-luminance characteristics SEr, SEg, and SEb for each color of RGB are set. That is, the emission luminances Erw, Egw, Ebw at the highest gradation (fifteenth gradation) of each RGB color are set so that the ratio of the emission luminances of the respective colors in the white balance shown in FIG. 19B is maintained. The 18A to 18B so that the above-described emission luminances Erw, Egw, and Ebw can be obtained by the gradation current at the highest gradation generated in the gradation current generation and supply circuit (current generation unit) for each color. As shown in c), channel widths of the p-channel transistors TP71r, TP71g, and TP71b provided in the reference current transistor unit STD are set.

  Therefore, in the gradation current generation circuit to which the current mirror circuit having only the reference current transistor shown in FIGS. 17 and 18 is applied, the channel width of the reference current transistor is set to a predetermined gradation − for each light emitting element of RGB. By setting so that the luminance characteristics (SEr, SEg, SEb shown in FIG. 20) can be obtained, as shown in FIG. 20, white light emission having a good white balance at the highest gradation of each color is realized. Since the luminance gradations in this case are all the highest gradations, white light emission (light emission luminance Ew) with higher luminance than the gradation-luminance characteristics shown in FIG. ) And display image quality can be improved.

<Fourth Embodiment of Display Device>
Next, a fourth embodiment of the display device according to the present invention will be described.
FIG. 21 is a circuit configuration diagram illustrating an example of a gradation current generation circuit (current generation unit) applied to the display device according to the fourth embodiment, and FIG. 22 illustrates the gradation according to the present embodiment. It is a partial circuit diagram which shows the reference current transistor part applied to a current generation circuit. Here, the current generation and supply circuit shown in FIGS. 3 and 17 will be referred to as appropriate, and the same components will be described with the same or equivalent reference numerals.

  In this embodiment, in the gradation current generation circuit (see FIGS. 17 and 18) shown in the third embodiment described above, the channel width is set individually (differently) corresponding to each RGB color. As shown in the second embodiment, a plurality of reference current transistors each having a different channel width are provided in each reference current transistor section having only a channel type transistor, and these are selectively switched as necessary. The gradation-luminance characteristics of each color light emitting element can be changed and set.

  As shown in FIG. 21, the current generator 20E applied to the gradation current generator according to the present embodiment has a high potential power supply + V and a current input contact INi substantially the same as the current generator 10D shown in FIG. A reference current transistor unit STE provided with a plurality of reference current transistors TP81a and TP81b and a capacitor Ce, a current mirror circuit unit 21E composed of a plurality of unit current transistors TP82 to TP85, and a p-channel type transistor TP86 to And a switch circuit unit 22E made of TP89.

  Here, as shown in FIGS. 22A to 22C, the reference current transistor unit STE includes a plurality of (two types in the present embodiment) p-channel transistors (reference types) having different channel widths for each color of RGB. Current transistor) Transistors TP81ra and TP81rb, TP81ga and TP81gb, TP81ba and TP81bb, and switches SWa and SWb for connecting one of the plurality of reference current transistors between the high potential power supply + V and the current input contact INi, and current Capacitors Cer, Ceg, and Ceb connected to the input contact INi, and appropriately switching and controlling the p-channel transistors of the reference current transistor units STE of RGB colors based on the control signal CNT (CNa and CNb) The gradation-luminance characteristics of the light emitting elements of RGB colors are shown in FIG. As shown in FIG. 2, a plurality of types are changed and set, and each gradation-luminance characteristic in each RGB color can obtain a good white balance in each emission luminance in the highest gradation as shown in FIG. It is set to be a proportion that can.

  According to the gradation current generating circuit having such a configuration, the unit current (steps) with respect to the reference current Iref in the current generating unit can be obtained by a simple control method for operating the control signal CNT without changing the current value of the reference current. The gradation-brightness characteristic of the display pixel (light emitting element) can be changed and set by switching the current ratio of the control current, so that the appropriate light emission luminance according to the use environment (environmental illuminance) of the display device Thus, the display pixel can be operated to emit light, and desired image information can be displayed with high visibility. In addition, the gradation-luminance characteristics of the light emitting elements for each of the RGB colors set by the switching control signal are set so that white light emission having a good white balance can be realized at the highest gradation of each color. Therefore, it is possible to achieve higher luminance white light emission and further improve the display image quality.

  In each of the above-described embodiments, only a configuration in which two sets of reference current transistors for selectively supplying a constant reference current are provided, but the present invention is not limited to this, and two or more reference current transistors are provided. Needless to say, an arbitrary characteristic may be selected from a plurality of gradation-current characteristics (or gradation luminance characteristics). In addition, as a method for controlling the switching of the plurality of reference current transistors, a method for selectively controlling the switches provided in the current paths of the respective reference current transistors based on the control signal CNT has been shown. The method for generating CNT is not particularly limited. For example, it may be generated by a system controller or the like by a user of an electronic device on which a display device is mounted. An illuminance sensor or the like that detects illuminance may be provided, and the control signal CNT may be generated based on the detection signal.

1 is a schematic configuration diagram illustrating a first embodiment of a current generation and supply circuit according to the present invention. It is a schematic block diagram which shows 2nd Embodiment of the electric current generation supply circuit which concerns on this invention. It is a circuit block diagram which shows one specific example of the current generation part applied to the current generation supply circuit which concerns on this embodiment. It is a characteristic view which shows an example of the current characteristic (gradation-current characteristic) with respect to the designated gradation in the current generation supply circuit according to the present embodiment. It is a schematic block diagram which shows 3rd Embodiment of the electric current generation supply circuit which concerns on this invention. It is a circuit block diagram which shows one specific example of the current generation part applied to the current generation supply circuit which concerns on this embodiment. 1 is a schematic block diagram showing a first embodiment of a display device to which a current generation and supply circuit according to the present invention can be applied. It is a schematic block diagram which shows the principal part structure of the display apparatus which concerns on this embodiment. It is a circuit block diagram which shows the 1st Example of the display pixel (pixel drive circuit) applied to this embodiment. It is a timing chart which shows an example of control operation in a data driver concerning this embodiment. It is a timing chart which shows an example of control operation in a display panel (display pixel) concerning this embodiment. FIG. 10 is a characteristic diagram illustrating an example of light emission luminance (gradation-luminance characteristic) of a display pixel with respect to a designated gradation in the display device according to the present embodiment. It is a schematic block diagram which shows the 2nd Example of the data driver applied to the display apparatus which concerns on 2nd Embodiment. It is a block diagram which shows one specific example of the gradation current generation circuit applied to the data driver which concerns on a present Example. It is a block diagram which shows one specific example of the electric current generation part which comprises the gradation current supply circuit applied to a present Example. It is a timing chart which shows an example of control operation in a data driver concerning this example. It is a circuit block diagram which shows one Example of the gradation current generation circuit (current generation part) applied to the display apparatus which concerns on 3rd Embodiment. It is a partial circuit diagram which shows the reference current transistor part applied to the gradation current generation circuit which concerns on this embodiment. It is a characteristic view which shows the current-luminance characteristic and gradation-luminance characteristic in each RGB light emission color of the light emitting element applied to the display apparatus which concerns on this embodiment. FIG. 4 is a characteristic diagram showing gradation-luminance characteristics in RGB emission colors of the light emitting element according to the present embodiment and a diagram showing a white balance setting concept. It is a circuit block diagram which shows one Example of the gradation current generation circuit (current generation part) applied to the display apparatus which concerns on 4th Embodiment. It is a partial circuit diagram which shows the reference current transistor part applied to the gradation current generation circuit which concerns on this embodiment. It is a circuit block diagram which shows the example of 1 structure of the data driver in a prior art.

Explanation of symbols

CLM, ILA, ILB Current generation supply circuit 10 Data latch units 20A-20E Current generation units 21A, 21B Current mirror circuit units 22A, 22B Switch circuit unit 100A Display device 110A Display panel 120A Scan driver 130A, 130B Data driver IR Constant current generation Sources PXA to PXC gradation current generation circuit DCx pixel drive circuit

Claims (11)

A display panel in which at least a plurality of scanning lines and a plurality of signal lines are arranged so as to be orthogonal to each other, and a plurality of display pixels are arranged in a matrix at intersections of the scanning lines and the signal lines; A scanning driving means for applying a scanning signal for selecting pixels in a row unit to each scanning line, and a signal for supplying a gradation current based on a display signal to each display pixel via each signal line A display device that displays desired image information on the display panel by supplying the gradation current having a predetermined current value to the display pixels in a selected state.
The signal driving means is supplied from a constant current source and a signal holding means for holding a digital signal of at least a plurality of bits based on the display signal for each bit corresponding to each of the plurality of signal lines. An input-side current circuit including one reference current transistor through which a reference current flows, and a plurality of output current transistors each generating a unit current having a current value of a predetermined current ratio with respect to the reference current, the signal holding Current generation means comprising: an output-side current circuit that selectively synthesizes the unit current according to each bit value of the digital signal held in the means and supplies the unit current as the gradation current; A plurality of current generation and supply circuits comprising:
Each of the plurality of display pixels has a light emission color of red, green, or blue that emits light at a predetermined luminance gradation according to a current value of the gradation current supplied from the current generation unit. A current-driven light-emitting element having
In the current generation means, the reference current transistor and the output current transistor constitute a current mirror circuit,
The transistor size of the reference current transistor in the input current circuit of each current generation supply circuit is such that the current ratio of each unit current to the reference current is red, green, a display device 3 primary light emitting luminance of the blue characterized that you have been set to a value that an optimum white balance in a particular tone.   The input-side current circuit includes charge storage means for storing a charge corresponding to a current component of the reference current flowing through the reference current transistor, and the output-side current circuit has a charge amount held in the charge storage means. The display device according to claim 1, wherein a current having a current value of the predetermined current ratio is generated by the output current transistor based on a corresponding voltage component. The current generating means is set such that the plurality of unit currents have current values at different ratios with respect to the reference current, corresponding to each of the plurality of bits of the digital signal. The display device according to claim 1 or 2 . 4. The display device according to claim 3, wherein the plurality of output current transistors are formed to have different transistor sizes. In the plurality of output current transistors, the channel widths of the output current transistors are set to different ratios defined by 2 ^k (k = 0, 1, 2, 3,...). The display device according to claim 4 . The current generation means includes refresh means for causing the reference current to flow through the reference current transistor at a predetermined timing and refreshing the charge amount stored in the charge storage means to a charge amount corresponding to the reference current. claim 2 Symbol placement of the display device, characterized in that the. The signal driving unit includes a reference current supply line to which the reference current is supplied, and each of the plurality of current generation and supply circuits is connected in parallel to the reference current supply line corresponding to the plurality of display pixels. is, the display device according to any one of claims 1 to 6, characterized in that the reference current through the reference current supply line is supplied. The signal driving means includes at least two sets of the current generation and supply circuits for each of the signal lines,
During an operation period in which the gradation current based on the digital signal of the plurality of bits previously held in one of the current generation and supply circuits is supplied to the display pixel, the next generation of the plurality of bits in the other current generation and supply circuit. display device according to any one of claims 1 to 7 the operation of holding the digital signal, characterized in that successively repeatedly executed alternately. It said current generating means, the display device according to any one of claims 1 to 8 signal polarity of the gradation current, and sets to flow in a direction to retract from the display pixels side. It said current generating means, the display device according to any one of claims 1 to 8 signal polarity of the gradation current, and sets to flow in a direction flow into the display pixels.   The display device according to claim 1, wherein the light emitting element is an organic electroluminescent element.

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