JP3369805B2 - Digital signal receiver - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an intermediate processing device which is connected between data processing devices for transmitting and receiving digital data and which processes the digital data, and more particularly to data obtained by encrypting the digital data. In addition, the present invention relates to an intermediate processing device that performs the decoding process.

[0002]

2. Description of the Related Art In recent years, as one of broadcasts providing new services, practical application of FM multiplex broadcasting in which a digital signal is multiplexed and transmitted in a vacant spectrum region of a baseband signal of FM stereo broadcasting has been advanced. There is.

In particular, the mobile reception FM multiplex broadcasting is the current F
It is a new medium that newly digitally multiplexes digital signals in a frequency band higher than the audio signal of M stereo broadcasting, and provides traffic information, character / graphic information and the like to mobile objects, and has the following advantages. That is, since the frequency can be effectively used, the broadcasting facility can be easily realized, and the data can be received by the mobile body, it is possible to easily transmit the traffic information to the mobile body such as an automobile.
As an advantage.

For example, a car navigation system currently installed in an automobile or the like operates based on fixed record information recorded in a CD-ROM or the like. Therefore, the driver cannot know the traffic congestion information and the like in real time.

Therefore, the FM multiplex broadcasting is the cheapest transmission line for mobiles that can access necessary information anytime, anywhere, as a means of eliminating chronic traffic congestion in large cities, or in addition to traffic information. As a result, its practical application is being promoted.

[0006] In the case of transmitting traffic information using FM multiplex broadcasting, as a method of providing only to members for a fee,
A method for encrypting a digital signal for transmitting the traffic information (hereinafter referred to as "scrambling") has been proposed.

Before describing the scrambling method, an outline of the data structure in FM multiplex broadcasting will be described below. [FM Multiplex Broadcasting System] Since mobile reception suffers from multipath interference and fading interference, it is necessary to implement an error correction method that copes with these interferences. Therefore, in order to correct bit errors and burst errors that occur in received data, in FM multiplex broadcasting, transmitted data has a data structure having a hierarchical structure as described below.

As a concrete example of the above hierarchical structure, the document: Pro
c. of Vehicle Navigation & Information Systems Con
The FM multiplex broadcasting system disclosed in ference (1994) A4-2 pp. 111-116 will be described.

FIG. 7 shows the specifications of the hierarchical structure. In the layer 1, the transmission line characteristic is designated. Normal F
In addition to the L + R signal and the L-R signal which are M stereo broadcast signals, the multiplexed signal is superimposed on the higher frequency side than the L-R signal.

This superposition method considers that the interference from the multiplex signal to the voice signal becomes remarkable when the voice modulation degree is small, so that the multiplexing level is controlled by the modulation degree of the LR signal. Minimum Shift
Keying) method is adopted.

Layer 2 defines the frame structure of data including an error correction method. Each frame consists of 272 blocks, with a 16-bit BIC (Block
Identification Code) is added, and frame synchronization and block synchronization are performed based on this BIC. Two
Of the 72 blocks, 190 blocks are packets for transmitting data, and 82 blocks are parity packets for transmitting column-direction parity. Each packet is 176
Bit information part, 14-bit CR which is an error correction code
It is composed of a C (Cyclic Redundancy Code) and an 82-bit parity part.

That is, the transmission data is first subjected to error correction at this stage using this one frame as a basic unit.

Layer 3 defines the structure of a data packet. The data packet is the BI of each row in the frame.
It consists of 176 bits excluding C, CRC and parity. Further, this data packet is composed of a prefix and a data block. The prefix includes information for identifying the content of the data, and, for example, specifies which program content described later the data packet belongs to.

Layer 4 defines the structure of the data group. A data group consists of one or more data blocks. The data group also includes a CRC which is an error correction code, and the transmission data is error-corrected also in this hierarchy.

Layer 5 defines the structure of program data. A program of character and graphic information is composed of a plurality of data groups, and the first data group is, as program management data, coded information relating to the entire program such as the total number of program number pages. Further, the program management data is followed by a plurality of page data, and the data for each page is encoded.

That is, in the above data structure, the program data on the receiving side constitutes one group of data indicating one group of information. For example, in the case of traffic information, the program information indicates the congestion status at each junction on a specific route (highway, etc.). [Construction of Conventional FM Multiplex Broadcasting Receiver] FIG. 8 shows a conventional FM multiplex broadcasting receiving apparatus when scrambled data is not transmitted.
2 is a schematic block diagram showing the configuration of an M-multiplex broadcast receiver 10. FIG.

The FM multiplex broadcast signal received by the antenna 12 and the tuner 14 is detected by the detection circuit 16, further passed through the band pass filter 18, and given to the LMSK demodulation circuit 20. The LMSK demodulation circuit 20 is L
Data demodulation of an FM multiplex broadcast signal that is MSK modulated is performed. The demodulated data signal is B in the synchronous reproduction circuit 22 as described in the hierarchy in FIG.
Frame synchronization and block synchronization are performed based on the IC. The synchronized data signal is error-corrected in the error correction circuit 24 based on the parity code and the CRC.

Therefore, the error correction circuit 24 outputs the FM multiplex broadcast packet data (having the structure shown in the layer 3 in FIG. 7) which is normally received or subjected to error correction.

The central processing unit 40 (hereinafter referred to as CPU) extracts data blocks from the input packet data, reconstructs data groups, corrects errors at the data group stage, and converts the packet data into program data. After the reconstruction, the program data is output to the display device 42.
The display device 42 outputs the input program data as a figure or a character.

[0020]

Since the conventional FM multiplex broadcast receiving apparatus 10 has the above-mentioned configuration, it adopts a broadcasting system in which the information is provided only to the members by using the FM multiplex broadcast. I couldn't.

For the above-mentioned purpose, it is necessary to scramble the transmission data at the FM multiplex broadcast transmission side, and at the reception side a decoding process (hereinafter,
Call it “descramble”. ) Is necessary.

In this case, when realizing the structure which enables the descramble of data on the receiving side, the structure of the conventional FM multiplex broadcasting receiving apparatus is not essentially changed, and for example, a decoding processing apparatus is simply added. If it can be realized in, it will be advantageous in terms of device manufacturing cost.

More specifically, the conventional F shown in FIG.
In the configuration of the M multiplex broadcasting receiver, the error correction circuit 24
It is necessary to add a decoding processing device between the CPU and the CPU 40 so that descrambling is possible.

However, the error correction circuit 24 and CP are simply
Only connecting the decoding processing device between U40 has the following problems.

FIG. 9 shows an error correction circuit 24 and a CPU 40 in the conventional FM multiplex broadcast receiving apparatus 10 shown in FIG.
3 is a timing chart showing the timing of data input / output with and.

At time t1, the error correction circuit 24
A pulse-shaped “H” level interrupt signal INTR indicating that the reception of data corresponding to one packet is completed
Output to U40.

At time t2, CPU 40 responds to activation ("H" level) of interrupt signal INTR to generate external clock signal Ext. Output CLK.

The error correction circuit 24 receives the external clock signal Ext. In response to CLK, the received data is output bit by bit for each pulse of the clock signal. Therefore,
The CPU 40 outputs a clock pulse for one packet, that is, for 176 bits, so that the error correction circuit 2
The input / output of packet data from 4 to the CPU 40 is completed.

Therefore, this error correction circuit 24 and CP
When a decoding processing circuit is connected to U40, a delay of the decoding processing time occurs. To deal with this, for example, the clock signal Ext. CL
Increasing the K cycle leads to an increase in data processing time.

The addition of a decoding processing device may change the data input / output interface.
It is also not desirable from the viewpoint of user friendliness of the decryption processing device.

Therefore, a main object of the present invention is to provide an intermediate processing device which can be applied as it is without changing the conventional interface configuration even when connected between devices for transmitting and receiving digital signals. Is.

Another object of the present invention is a decoding process which has an optimum structure for the data structure of FM multiplex broadcasting, is capable of high-speed operation, and can be applied as it is without changing the conventional interface structure. It is to provide an intermediate processing device to perform.

[0033]

According to a first aspect of the present invention, there is provided a digital signal receiving apparatus, wherein frame data is composed of a plurality of packets, and the frame data is transmitted in FM multiplex communication in which the frame data is multiplexed into an FM broadcast for communication. A digital signal receiving apparatus for receiving the frame data, wherein the transmission data is a data packet including prefix data defining the contents of information data included in each packet and a data block including the information data. The prefix data includes a number of a data group to which the data packet belongs and a data bucket number of the data packet in the data group, and further, when the transmission data is encrypted and transmitted, the transmission data is transmitted. The data is the data group number and / or data Data packet number and demodulation of the frame data that is encrypted based on an initial value generated by the master key data included in a predetermined data packet of the plurality of data packets, that receives the transmission data, and is multiplexed. Demodulation means 20, 22 for performing
Error correction is performed on the frame data demodulated by the demodulation means 20 and 22, the data packet after error correction is output as data, and reception of data corresponding to one packet of the data packet is completed. An error correction unit 24 which detects and outputs the first trigger signal INTR1 and an output of the error correction unit 24 are received to detect the presence or absence of encryption for each data packet,
Key data extracting means 300 for extracting master key data from the predetermined data packet when encrypted.
And an intermediate processing unit 100 that performs a decryption process of the information data encrypted for each corresponding data packet based on the initial value, and an output of the intermediate processing unit 100 to receive a plurality of the data packets. Data processing means 40 for extracting the data block from the data block, reconstructing and outputting the data group, and the intermediate processing means 1
00 performs initial value determination processing for generating the initial value based on the output data from the error correction means 24, performs decoding processing based on the determined initial value, and outputs the data to the data operation means 40 side. Data processing means 102, 10
4, 108, an internal clock generating means 112 for outputting an internal clock signal, and the first trigger signal INTR1.
In response to the input, the internal clock signal is set to the initial value of the data processing means 102, 104, 108 during a period in which the output data from the error correction means 24 is data corresponding to the prefix data. Output as an operation control clock signal during the determination processing period, and after the lapse of the initial value determination processing period, the second trigger signal INTR2
The data calculation means 40 and the data processing means 10
2, 104, 108, and an external clock signal output from the data calculation means 40 side in response to the input of the second trigger signal INTR2.
Clock signal output means 11 for outputting as an operation control clock signal during the decoding processing period of 02, 104, 108.
4, 116, 118, and 120.

A digital signal receiving apparatus according to a second aspect is
The structure of the digital signal receiving apparatus according to claim 1,
The clock signal output means 114, 116, 118, 1
20 is timing detection means 116, 118, 12 for detecting the start of the initial value determination processing of the data processing means 102, 104, 108 and outputting a timing detection signal.
0, a clocking means 110 which starts clocking in response to the input of the timing detection signal and outputs the second trigger signal INTR2 after a preset waiting time has elapsed, and the internal clock signal which is the operation control clock. The switching means 114 includes a switching means 114 for switching between a first state in which the signal is output as a signal and a second state in which the external clock signal is output as the operation control clock signal. The switching means 114 includes the first trigger signal INTR1. In response to the input, the output data from the error correction means 24 is kept in the first state and is input to the second trigger signal INTR2 during a period in which the data corresponding to the prefix data is input. Accordingly, the second state is maintained during the period in which the external clock signal is output.

A digital signal receiving apparatus according to claim 3 is
The structure of the digital signal receiving apparatus according to claim 2,
In the timing detecting means 116, 118, 120, the count value is reset in response to the input of the first trigger signal INTR1, and the data processing means 102, 104, 1
Bit counting means 116 for counting the number of bits of the output data from the error correcting means 24 input to 08, and detecting that the counted value corresponds to the position corresponding to the prefix data of the data packet, and detecting the bit position. The comparison means 118 for outputting a signal and the timing detection signal are canceled in response to the input of the first trigger signal INTR1 and held in a state of outputting the timing detection signal in response to the input of the bit position detection signal. Latching means 120 for controlling the data processing means 102,
The 104 and 108 perform the decoding process on the information data included in the data packet based on the result of the initial value determination process.

The digital signal receiving apparatus according to claim 4 is
The structure of the digital signal receiving apparatus according to claim 3,
The data processing means sequentially inputs the output data from the error correction means 24 in series, outputs the data in series, and outputs the stored data in parallel, and the data processing means for each data packet. The storage unit 102 detects that the prefix data included in the data packet is input, and is determined by the master key data and the data group number and / or the data packet number included in the storage data output in parallel. Based on the initial value, the random number generation means 104 for outputting a pseudo random number sequence and the switching means 114 are in the second state, the pseudo random number sequence and the error correction means 2
The exclusive OR operation of the output data from 4 is sequentially performed,
The logical operation means 108 is included.

[0037]

[0038]

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an FM according to an embodiment of the present invention.
It is a schematic block diagram showing a configuration of an intermediate processing device 100 that performs a decoding process in a multiplex broadcast receiving device.

The intermediate processing device 100 is connected between the error correction circuit 24 and the CPU 40 in the configuration of the conventional FM multiplex broadcast receiving device shown in FIG. Therefore,
The output D _in from the error correction circuit 24 is input to the intermediate processing device 100. The intermediate processing device 100 performs a decoding process on the signal D _in and then outputs an output signal D _out to the CPU 40.

Before describing the details of the configuration and operation of the intermediate processing device 100, the configuration of transmitted packet data will be described below with reference to FIG.

As shown in Layer 3 in FIG. 7, the data packet is composed of a prefix of 32 bits and a data block of 144 bits following the prefix. FIG. 2 is a block diagram showing the data structure of this data packet.

The first 4 bits of the prefix are a service identification code. For example, when this value is 4, 5 or 6, it is assumed that the data block of the data packet to which this prefix belongs is scrambled. For the 1-bit decoding identification code following the service identification code, whether the error correction is performed with the correction code in the horizontal direction only,
Alternatively, it indicates whether to decode using a product code. The subsequent 1-bit information output code is "1" when the data group ends, and "0" otherwise.
Further, a 2-bit update code that follows the update code indicates an update of the data group.

The data group number existing in 9 to 22 bits means the data group to which the data packet belongs, and the data packet number existing in 23 to 32 bits means the order of the data packet transmitted for each data group number. Indicates.

The data blocks existing in 33 to 176 bits are the conventional FM multiplex broadcasting receiver 10 shown in FIG.
In the CPU 40, the CPU 40 is a part that is further reconfigured into a data group and program data, and is a main part of the data to be transmitted.

When the transmission data is scrambled and transmitted, the data in the data block area has an initial value generated by, for example, the master key data common to the data group and the data group number and the data packet number. Is encrypted and decrypted based on

That is, the data block data is encrypted based on different key data (initial value) for each packet, which makes it more difficult to decipher the information data and improves the confidentiality of the transmission data. ing.

FIG. 3 is a schematic diagram showing the principle of the method of scrambling the transmission data and the method of descrambling the encrypted reception data.

FIG. 3 (a) shows the structure for scrambling the transmission data, and FIG. 3 (b) shows the structure for descrambling the reception data.
Referring to FIG. 9A, when scrambling transmission data, a pseudo random binary sequence generation circuit 104 that generates, for example, an m-sequence (maximum-length sequence) based on predetermined key data is used. 2 generated
The result of the logical operation of the decimal pseudo random number and the transmission data by the exclusive OR circuit 108 is transmitted as the encrypted transmission data.

On the other hand, referring to FIG. 3B, on the side receiving the encrypted transmission data, a pseudo-random binary sequence generation circuit is generated based on the predetermined key data used for encryption in the transmission system. An exclusive OR circuit 1 for the binary pseudo random number generated by 104 and the encrypted received data
The result of the logical operation in 08 is output as the decoded reception data.

The following points are characteristic of the above-described scramble method and descramble method.

That is, first, the same key data is used on the transmitting side and the receiving side.

Secondly, when the same key data is used, the pseudo random binary sequence generation circuit 104 always outputs a predetermined binary pseudo random number (for example, m sequence).

Thirdly, the binary transmission data returns to the original value when the exclusive OR operation with the same binary pseudo data is performed twice.

FIG. 4 is an operation explanatory view for explaining the operations when the transmission data is scrambled and descrambled by the above scrambling method and descrambling method.

FIG. 4A is a diagram showing an operation when scrambling the transmission data TD, and FIG. 4B is a diagram showing an operation when descramble the encrypted reception data CRD.

It is assumed that the output RS of the pseudo-random binary sequence generation circuit 104 is an m sequence that changes in the cycle n.
In FIG. 4, all data are assumed to be 4 bits for the sake of simplicity.

Referring to FIG. 4A, when the transmission data TD is scrambled, for example, the key data is 0.
001 and the transmission data TD is 1010,
The exclusive OR value of the signals RS and TD is 1011.
This signal is transmitted as scrambled encrypted transmission data. Similarly, for the next transmission data TD 1101, the exclusive OR operation is performed with the output 0100 of the pseudo random binary sequence generation circuit 104, and the encrypted transmission data 1001 is transmitted. . The signal RS changes in the cycle n, and the transmission data TD and this signal R
The exclusive OR operation result with S will be sequentially transmitted as encrypted transmission data.

Referring to FIG. 4B, also on the receiving side, based on the same key data 0001 as on the transmitting side, the pseudo random binary sequence generation circuit 104 outputs an m-sequence signal RS. In this case, as described above, when the key data is based on the same key data, the same binary sequence as that on the transmitting side is output as the signal RS at the cycle n.

A series of signals obtained by sequentially performing an exclusive OR of the signal RS and the encrypted received data CRD is shown in the right column of FIG. 4 (b). That is, the encrypted reception data CRD is the same signal RS and the exclusive OR operation performed twice on the transmission data TD. This value is the transmission data TD
It turns out that it agrees with.

The scrambling method and descrambling method for the digital signal represented by a binary number have been described above in a very simplified manner.

As described above, in the case of scrambling the data transmitted by FM multiplex broadcasting, the reliability of the encryption mainly depends largely on the confidentiality of the key data.

Therefore, as described above, the key data is
A value that is updated for each packet is used instead of a single value, and as will be described later, a value that is further randomized for the master key data, data packet number, and data group number is used. .

The master key data is transmitted by being included in a predetermined position in a predetermined data packet for each group data, for example.

Therefore, after the master key data is extracted in the decryption processing apparatus 100,
There is a certain delay time until the key data is generated together with the data group number and the data packet number.

Returning to FIG. 1, the intermediate processing circuit 100 according to the embodiment of the present invention receives the outputs of the shift register 102, the pseudo random number generation circuit 104, and the pseudo random number generation circuit 104, and controls the timing detection signal. It includes a logic gate circuit 106 that outputs the converted data and an exclusive OR circuit 108 that receives the input data D _in from the error correction circuit 24, performs an exclusive OR operation and outputs the exclusive OR operation to the shift register 102.

The intermediate processing device 100 is further reset in response to the first interrupt signal INTR1 from the error correction circuit 24, and a counter circuit 116 for counting the number of bits of data input to the shift register 102, and a counter circuit. A comparator circuit 1 that receives the count value of 116 and detects that a data prefix is input to the shift register 102.
18, an RS flip-flop circuit 120 whose output is set by the signal INTR1 and whose output is reset by the output of the comparison circuit 118, and an internal clock circuit 112.
And the internal clock signal int. CLK and the external clock signal Ext. In response to the CLK, the output signal of the SR flip-flop circuit 120 is controlled so that either one of the shift register 102 and the pseudo random number generation circuit 1 is controlled.
04 and the error correction circuit 24 and the output of the switching circuit 114 and the SR flip-flop circuit 120 are set, the clocking is started, and after the elapse of a predetermined time, the second interrupt signal INTR2 is output. A timer circuit 110 for outputting to the CPU 40 is included.

Although not particularly limited, the shift register 102 is, for example, a 32-bit shift register,
The packet data output from the error correction circuit 24 is sequentially input. When the pseudo random number generation circuit 104 detects that the packet data prefix is input to the shift register 102, the pseudo random number generation circuit 104 receives the parallel output from the shift register 102, extracts the data group number and the data packet number, and extracts the key data extraction circuit in advance. An initial value for generating a pseudo-random number is generated based on the master key data extracted by (not shown), and based on the initial value, a pseudo-random binary sequence (for example, m-sequence (maximu
m-length sequence)) is generated. The operation of the pseudo random number generation circuit 104 to output the pseudo random binary sequence is the second interrupt signal I output from the timer circuit 110.
NTR2 is activated in response to the operation control clock signal Cont. Controlled by CLK.

The logic gate circuit 106 receives the output of the pseudo random number generation circuit 104 and the output of the SR flip flop circuit 120, and generates the pseudo random number during the period when the output of the SR flip flop circuit 120 is at "L" level. Circuit 1
The output of 04 is output to the exclusive OR gate 108.

The exclusive OR gate circuit 108 performs an exclusive OR operation between the output signal of the logic gate circuit 106 and the input signal D _in to perform the decoding process of the input signal D _in , and the shift register 102. Output to.

Therefore, in the decoding process in the exclusive OR circuit 108, the second interrupt signal INTR2 output from the timer circuit 110 when the output of the SR flip-flop circuit 120 is in the reset state (“L” level). In response to the external clock signal Ext. It is performed only during the period when CLK is output.

The pseudo-random binary sequence output from the pseudo-random number generation circuit 104 is generated by the same initial value and the same arithmetic processing used for encryption when transmitting the FM multiplex broadcast, so that the pseudo-random number in the encryption is pseudo. As with the random binary sequence, the decoding process is performed according to the principle described in FIGS. 3 and 4.

FIG. 5 is a schematic block diagram showing the structure of the pseudo random number generation circuit 104. Pseudo random number generation circuit 104
Is a randomization circuit 501 that receives the parallel output of the shift register 102, an exclusive OR circuit 503 that receives the output of the randomization circuit 501 and the output of the key data extraction circuit 300,
Random number generators 504 to 506 that generate pseudo random numbers using the output of the exclusive OR circuit 503 as an initial value, and the random number generator 5.
It includes a non-linear circuit 507 which receives the outputs of 04 to 506 and outputs a non-linear operation result.

The randomization circuit 501 outputs the 9th to 32nd bits of the shift register 102 in parallel, that is, the data group number and the data packet, in response to the output signal of the comparison circuit 118 becoming "H" level. Receives the number and performs randomization processing. Key data extraction circuit 3
00 extracts and outputs the key data included in a predetermined data packet. The exclusive OR circuit 503 performs an exclusive OR operation on each bit of the output of the key data extraction circuit 300 and the output of the randomization circuit 501 and outputs it as initial data.

Random number generators 504, 505 and 506
Starts its operation in response to the activation of the signal INTR2, and the clock signal Cont. The m-sequence generator is controlled by CLK and generates a pseudo-random binary sequence with the output of the exclusive OR circuit 503 as an initial value.

In this case, although not particularly limited, among the initial data output from the exclusive OR circuit 503, the higher-order bit data having a predetermined number of bits is set as the initial value of the random number generator 504, and the predetermined number of bits is set. It is possible to adopt a configuration in which the order bit data is used as the initial value of the random number generator 505, and the data of the lower bits of a predetermined number of bits is used as the initial value of the random number generator 506.

The non-linear circuit 507 includes random number generators 504 ...
The output of 506 is nonlinearly processed and output. Random number generator 5
The m-series generators 04 to 506 are generally composed of feedback registers, and by performing such non-linear processing on the pseudo-random binary series signal output from the m-series generator, it is more difficult to decipher the cipher. I am trying.

The operation of the intermediate processing circuit 100 according to the embodiment of the present invention will be described below. FIG. 6 is a timing chart showing the operation of the intermediate processing circuit 100.

At time t0, the error correction circuit 24 detects that the reception of one packet of data is completed, and activates the first interrupt signal INTR1 ("H" level). In the intermediate processing device 100, in response to activation of the first interrupt signal INTR1, at time t1,
The output of the RS flip-flop circuit 120 enters the set state (“H” level), and the count value of the counter circuit 116 is reset.

In response to the output of the RS flip-flop circuit 120 being in the set state, the switching circuit 114
The output signal int. In response to the operation control clock signal Cont. The state is switched to output as CLK. Therefore, at the time t2, the operation control clock signal Cont.
CLK starts to be output. Operation clock signal Cont.
In response to the CLK pulse, the shift register 102 inputs the input signal D _in bit by bit. At this time, the output of the AND circuit 106 holds the “L” level because the output of the RS flip-flop circuit 120 is the “H” level. Therefore, the exclusive OR circuit 108 outputs the input data D _in as it is, and the shift register 102
To enter.

The counter circuit 116 includes the shift register 1
The latest 1 bit in 02 indicates which bit data in the packet. In this case, the counter circuit 116 has a data length of 1 packet, that is, 17
The counting operation is performed with 6 bits as a cycle.

The comparator circuit 118 sends an "H" level signal to the RS flip-flop circuit 120 when the count value of the counter circuit 116 reaches 32, that is, when all the prefixes in the packet data are input to the shift register 102. Output.

Therefore, at the time t3, the output of the RS flip-flop circuit 120 is in the reset state ("L" level).

On the other hand, the pseudo random number generation circuit 104 receives the parallel output from the shift register 102 and extracts the data group number and the data packet number.
Generate an initial value for random number generation based on master key data.

The timer circuit 110, at time t3,
In response to the output of the RS flip-flop circuit 120 becoming "L" level, the counting operation is started, and after the elapse of a predetermined delay time τ (time t4), the interrupt signal INTR2 is changed to C
It is output to the PU 40 and the pseudo random number generation circuit 104. Random number generators 504 to 50 in the pseudo random number generation circuit 104
6 starts its operation in response to the activation of the interrupt signal INTR2.

The CPU 40 uses the second interrupt signal INTR2.
In response to the external clock signal Ext. Start outputting CLK. Switching circuit 114 receives external clock signal Ext.CLK in response to the output of RS flip-flop circuit 120 being reset. In response to the operation control clock signal Cont. It has been switched to the state of outputting as CLK.

Therefore, at time t4, in response to activation of second interrupt signal INTR2, external clock signal Ext. C
LK is the operation control clock signal Cont. As CLK,
It is applied to shift register 102, pseudo random number generation circuit 104 and error correction circuit 24.

Signal Cont. Depending on the toggle of CLK,
The input signal D _in is input from the error correction circuit 24 to the intermediate processing circuit 100 bit by bit.

The pseudo random number generation circuit 104 also receives the signal Con.
t. A pseudo random binary sequence is output according to CLK. At this time, since the output of the RS flip-flop circuit 120 is at “L” level, the output of the pseudo random number generation circuit 104 is directly output to the exclusive OR circuit 108.

In the exclusive OR circuit 108, the data after the prefix, that is, the data block data is subjected to the exclusive OR operation with the output of the pseudo random number generation circuit 104, that is, the decoding process, It is output to the shift register 102.

The shift register 102 receives the external clock signal Ext. CLK that is the same as the operation control clock signal Cont. It is controlled by CLK and outputs data bit by bit to the CPU 40.

As a result of the above operation, when viewed from the error correction circuit 24, when the error correction circuit 24 detects the completion of reception of the data of one packet and outputs the first interrupt signal INTR1, the error correction is first performed. In the circuit 24, the operation control clock signal Cont. CLK is given. Then, after a lapse of a predetermined time, the error correction circuit 24 displays the operation control clock signal Cont. CL
K is given and the data output for one packet is completed.
In this case, the output from the error correction circuit 24 is the operation control clock signal Cont. Controlled by CLK,
There is no need to change the interface of the error correction circuit 24.

On the other hand, when viewed from the CPU 40, the CPU 4
0 receives the second interrupt signal INTR2 and outputs a clock signal for 176 bits, that is, one packet, to the intermediate processing circuit 100, thereby completing the input of data for one packet. Therefore, from the perspective of the CPU 40, it is possible to input data with the same interface configuration as when there is no intermediate processing device 100.

That is, with the configuration of the embodiment of the present invention, the error correction circuit 24 can be simply connected by connecting the intermediate processing device 100 without making any changes to the configuration of the interface of the error correction circuit 24 and the CPU 40. It is possible to perform a decoding process on the data output from the.

Moreover, the number of bits of the shift register 102 can be made smaller than the number of bits of one packet, and the delay caused by the data passing through the shift register 102 can be suppressed to the minimum. Is.

[0096]

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing a configuration of an intermediate processing device 100 according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the structure of packet data in FM multiplex broadcasting.

3A and 3B are principle diagrams showing the principle of a scramble method and a descramble method. FIG. 3A shows the principle of a scramble method in a transmission system, and FIG. 3B shows the principle of a descramble method in a reception system.

4A and 4B are operation explanatory diagrams showing operations of the scramble method and the descramble method shown in FIG. 3, where FIG. 4A shows an operation of the scramble method and FIG. 4B shows an operation of the descramble method.

FIG. 5 is a schematic block diagram showing a configuration of a pseudo random binary sequence generation circuit 104 in the intermediate processing device according to the present invention.

FIG. 6 is a timing chart showing the operation of the intermediate processing device 100 of the present invention.

FIG. 7 is a specification diagram showing an example of a data structure in FM multiplex broadcasting.

FIG. 8 is a schematic block diagram showing a configuration of a conventional FM multiplex broadcast receiving apparatus.

FIG. 9 is a timing chart showing input / output of data in the conventional FM multiplex broadcast receiving apparatus.

[Explanation of symbols]

10 Conventional FM multiplex broadcasting receiver 12 antennas 14 Tuner 16 Detection circuit 18 bandpass filter 20 LSMK demodulation circuit 22 Synchronous playback circuit 24 Error correction circuit 40 CPU 42 display device 100 Intermediate processor 102 shift register 104 Pseudo random number generator 106 logic gate circuit 108 Exclusive OR circuit 110 timer circuit 112 clock circuit 114 switching circuit 116 counter circuit 118 comparison circuit 120 SR flip-flop circuit

─────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-5-95296 (JP, A) Yutaka Hirasha, Outline of FM character multiplex LSI, broadcasting technology, Japan, 47, 704-708 (58) Survey Areas (Int.Cl. ⁷ , DB name) H04H 1/00-1/02

Claims (4)

(57) [Claims] 1. The frame data is composed of a plurality of packets.
The frame data is multiplexed and transmitted to the FM broadcast.
The frame transmitted in FM multiplex communication
A digital signal receiving device for receiving data, wherein each packet of the transmission data is included in the packet.
Prefix data that defines the content of the information data
And a data pattern including a data block including the information data.
And the prefix data is
The number of the data group to which the data packet belongs and the data group
Data packet of the data packet in the data group
In addition, the transmission data is encrypted.
When transmitted by the data group, the transmission data is
Packet number and / or data packet number and the plurality of data packets.
Data contained in a given data packet
Based on the initial value generated by the
Has been encoded , received the transmission data, and multiplexed the frame data.
Demodulation means 20, 22 for demodulating the data, and the frame data demodulated by the demodulation means 20, 22.
Data for which data has been corrected and the data has been corrected.
Data output of the packet and the data packet
Has received the data corresponding to one packet of
Is detected and outputs the first trigger signal INTR1
Error correction means 24 and the output of the error correction means 24 to receive the data packet.
If it is encrypted by detecting the presence or absence of encryption for each
The master key data from the specified data packet.
The key data extraction means 300 to be output and the corresponding data packet based on the initial value.
Intermediate for decrypting the information data encrypted to and
The output of the processing means 100 and the intermediate processing means 100 is received, and the plurality of data are received.
The data block is extracted from the data packet and the data block is extracted.
Data calculating means 40 for reconstructing and outputting data groups
And the intermediate processing means 100 , based on the output data from the error correction means 24,
It is decided by performing the initial value determination process to generate the initial value.
The data calculation means for performing a decoding process based on an initial value
Data processing means 102, 104 , 10 for outputting to the 40 side
8 and internal clock generation means 11 for outputting an internal clock signal
2 and in response to the input of the first trigger signal INTR1
The output data from the error correction means 24 is the prefix
Data corresponding to the input data is input to the data processing means 102, 10.
4, 108 as an operation control clock signal during the initial value determination processing period, and after the initial value determination processing period elapses
To the second trigger signal INTR2
Output to the stage 40 and the data processing means 102, 104, 108, and in response to the input of the second trigger signal INTR2.
The external clock output from the data computing means 40 side
A clock signal to the data processing means 102, 104, 108.
Clock signal output means 114, 116, 118 for outputting as an operation control clock signal during the decoding processing period of
120, and a digital signal characterized by having
Receiver . 2. The clock signal output means 114, 11
6 , 118 and 120 are the initials of the data processing means 102, 104 and 108.
Timing detection means 116 , 118 , 120 that detect the start of the value determination process and output a timing detection signal, and start timing in accordance with the input of the timing detection signal, and set a preset waiting time. A clock means 110 for outputting the second trigger signal INTR2 after a lapse of time, a first state for outputting the internal clock signal as the operation control clock signal, and a first state for outputting the external clock signal as the operation control clock signal Switching means 114 for switching between the second state and the second state, wherein the switching means 114 has the first trigger signal INTR.
In response to the input of 1, the output data from the error correction means 24
During the period in which the data corresponding to the prefix data is input to the data , the first state is maintained and the second state is maintained.
2. The digital signal receiving apparatus according to claim 1, wherein the second state is held during a period in which the external clock signal is output in response to the input of the trigger signal INTR2 . [Claim 3] before Symbol timing detection means 116,11
8,120 the count value in response to input of the first trigger signal INTR1 is reset, the data processing means 102,
The output data from the error correction means 24 input to 108
And bit counting means 116 for counting the number of bits data, the counted value is the prefix data of the data packet
It detects that correspond to the position corresponding to data, a comparing means 118 for outputting the bit position detection signal, in response to input of the first trigger signal INTR1, cancel the timing detection signal, the bit position detection signal depending on the input, and a latch means 120 for holding a state of outputting the timing detection signal, the data processing means 102, 104, 108, the first
Included in the data packet based on the result of the period value determination process.
The digital signal receiving apparatus according to claim 2, wherein the decoding process is performed on the information data to be included . 4. The data processing means sequentially inputs the output data from the error correction means 24 in series.
Output in series and output stored data in parallel.
Data storage means 102, and the data storage means 102 for each of the data packets.
Is included in the data packet.
Data is detected and input in parallel.
The data group number and / or included in the memory data
By the data packet number and the master key data
Outputs a pseudo-random number sequence based on the determined initial value
The random number generating means 104 and the switching means 114 are in the second state,
Exclusion of the output data from the similar random number sequence and the error correction means 24
Logical operation means 108 for sequentially performing other logical OR operation
The digital signal receiving apparatus according to claim 3, comprising.