JP3369806B2 - Digital signal receiver - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an intermediate processing device which is connected between data processing devices for transmitting and receiving digital data and which processes the digital data, and more particularly to data obtained by encrypting the digital data. In addition, the present invention relates to an intermediate processing device that performs the decoding process.

[0002]

2. Description of the Related Art In recent years, as one of broadcasts providing new services, practical application of FM multiplex broadcasting in which a digital signal is multiplexed and transmitted in a vacant spectrum region of a baseband signal of FM stereo broadcasting has been advanced. There is.

In particular, the mobile reception FM multiplex broadcasting is the current F
It is a new medium that newly digitally multiplexes digital signals in a frequency band higher than the audio signal of M stereo broadcasting, and provides traffic information, character / graphic information and the like to mobile objects, and has the following advantages. That is, since the frequency can be effectively used, the broadcasting facility can be easily realized, and the data can be received by the mobile body, it is possible to easily transmit the traffic information to the mobile body such as an automobile.
As an advantage.

For example, a car navigation system currently installed in an automobile or the like operates based on fixed record information recorded in a CD-ROM or the like. Therefore, the driver cannot know the traffic congestion information and the like in real time.

Therefore, the FM multiplex broadcasting is the cheapest transmission line for mobiles that can access necessary information anytime, anywhere, as a means of eliminating chronic traffic congestion in large cities, or in addition to traffic information. As a result, its practical application is being promoted.

[0006] In the case of transmitting traffic information using FM multiplex broadcasting, as a method of providing only to members for a fee,
A method for encrypting a digital signal for transmitting the traffic information (hereinafter referred to as "scrambling") has been proposed.

Before describing the scrambling method, an outline of the data structure in FM multiplex broadcasting will be described below. [FM Multiplex Broadcasting System] Since mobile reception suffers from multipath interference and fading interference, it is necessary to implement an error correction method that copes with these interferences. Therefore, in order to correct bit errors and burst errors that occur in received data, in FM multiplex broadcasting, transmitted data has a data structure having a hierarchical structure as described below.

As a concrete example of the above hierarchical structure, the document: Pro
c. of Vehicle Navigation & Information Systems Con
The FM multiplex broadcasting system disclosed in ference (1994) A4-2 pp. 111-116 will be described.

FIG. 7 shows the specifications of the hierarchical structure. In the layer 1, the transmission line characteristic is designated. Normal F
In addition to the L + R signal and the L-R signal which are M stereo broadcast signals, the multiplexed signal is superimposed on the higher frequency side than the L-R signal.

This superposition method considers that the interference from the multiplex signal to the voice signal becomes remarkable when the voice modulation degree is small, so that the multiplexing level is controlled by the modulation degree of the LR signal. Minimum Shift
Keying) method is adopted.

Layer 2 defines the frame structure of data including an error correction method. Each frame consists of 272 blocks, with a 16-bit BIC (Block
Identification Code) is added, and frame synchronization and block synchronization are performed based on this BIC. Two
Of the 72 blocks, 190 blocks are packets for transmitting data, and 82 blocks are parity packets for transmitting column-direction parity. Each packet is 176
Bit information part, 14-bit CR which is an error correction code
It is composed of a C (Cyclic Redundancy Code) and an 82-bit parity part.

That is, the transmission data is first subjected to error correction at this stage using this one frame as a basic unit.

Layer 3 defines the structure of a data packet. The data packet is the BI of each row in the frame.
It consists of 176 bits excluding C, CRC and parity. Further, this data packet is composed of a prefix and a data block. The prefix contains information that identifies the content of the data, for example:
It specifies which program content to be described later the data packet belongs to.

Layer 4 defines the structure of the data group. A data group consists of one or more data blocks. The data group also includes a CRC which is an error correction code, and the transmission data is error-corrected also in this hierarchy.

Layer 5 defines the structure of program data. A program of character and graphic information is composed of a plurality of data groups, and the first data group is, as program management data, coded information relating to the entire program such as the total number of program number pages. Further, the program management data is followed by a plurality of page data, and the data for each page is encoded.

That is, in the above data structure, the program data on the receiving side constitutes one group of data indicating one group of information. For example, in the case of traffic information, the program information indicates the congestion status at each junction on a specific route (highway, etc.). [Construction of Conventional FM Multiplex Broadcasting Receiver] FIG. 8 shows a conventional FM multiplex broadcasting receiving apparatus when scrambled data is not transmitted.
2 is a schematic block diagram showing the configuration of an M-multiplex broadcast receiver 10. FIG.

The FM multiplex broadcast signal received by the antenna 12 and the tuner 14 is detected by the detection circuit 16, further passed through the band pass filter 18, and given to the LMSK demodulation circuit 20. The LMSK demodulation circuit 20 is L
Data demodulation of an FM multiplex broadcast signal that is MSK modulated is performed. The demodulated data signal is passed through the sync reproducing circuit 22 as described in the hierarchy in FIG.
Frame synchronization and block synchronization are performed based on C. The synchronized data signal is error-corrected in the error correction circuit 24 based on the parity code and the CRC.

Therefore, the error correction circuit 24 outputs the FM multiplex broadcast packet data (having the structure shown in the layer 3 in FIG. 7) which is normally received or subjected to error correction.

The central processing unit 40 (hereinafter referred to as CPU) extracts data blocks from the input packet data, reconstructs data groups, corrects errors at the data group stage, and converts the packet data into program data. After the reconstruction, the program data is output to the display device 42.
The display device 42 outputs the input program data as a figure or a character.

[0020]

Since the conventional FM multiplex broadcast receiving apparatus 10 has the above-mentioned configuration, it adopts a broadcasting system in which the information is provided only to the members by using the FM multiplex broadcast. I couldn't.

For the above-mentioned purpose, it is necessary to scramble the transmission data at the FM multiplex broadcast transmission side, and at the reception side a decoding process (hereinafter,
Call it “descramble”. ) Is necessary.

In this case, when realizing the structure which enables the descramble of data on the receiving side, the structure of the conventional FM multiplex broadcasting receiving apparatus is not essentially changed, and for example, a decoding processing apparatus is simply added. If it can be realized in, it will be advantageous in terms of device manufacturing cost.

More specifically, the conventional F shown in FIG.
In the configuration of the M multiplex broadcasting receiver, the error correction circuit 24
It is necessary to add a decoding processing device between the CPU and the CPU 40 so that descrambling is possible.

However, the error correction circuit 24 and CP are simply
Only connecting the decoding processing device between U40 has the following problems.

FIG. 9 shows an error correction circuit 24 and a CPU 40 in the conventional FM multiplex broadcast receiving apparatus 10 shown in FIG.
3A is a timing chart showing the timing of data input / output to and from the error correction circuit 24 to the CPU 40.
When the demodulated data is output to C,
The case where the control data is output from the PU 40 to the FM multiplex broadcast demodulation LSI including the error correction circuit 24 is shown.

First, the case where the demodulated data is output from the error correction circuit 24 to the CPU 40 (serial data output mode) will be described below.

Referring to FIG. 9A, at time t1, CPU 40 starts outputting address signals B0-B3 and A0-A3 together with clock signal CLK to error correction circuit 24. Further, at time t2, the CPU
The signal CE is changed from the "L" level to the "H" level to indicate that the output of the address signal is completed.

The error correction circuit 24 has address signals B0 to B0.
Upon receiving B3 and A0-A3, it is detected that the serial data output mode has been entered, and at time t3 after time t _{ES has} elapsed from time t2, demodulation is performed according to the clock signal CLK output from the CPU 40. Data D
O0 to DO175 (corresponding to 1 packet of data)
Are sequentially output to the CPU 40 bit by bit.

Although not shown in FIG. 9A, at the time t1 when the CPU 40 starts outputting the address signals B0 to B3 and A0 to A3 together with the clock signal CLK, the error correction circuit 24 makes one packet. It is determined according to an interrupt signal INTR which is output to notify that the preparation for the output of minute data has been completed.

Next, the timing when the CPU 40 outputs the control data DI0 to DI15 to the error correction circuit 24 will be described.

Referring to FIG. 9 (b), at time t1, CPU 40 sends address signal B0-B3 and A0-A3 together with clock signal CLK to error correction circuit 24.
Start outputting to.

At time t2, the CPU 40 sends the signal C to notify that the output of the address signal is completed.
E is changed from "L" level to "H" level. The error correction circuit 24 detects that the output of the address signal is completed in response to the signal CE becoming "H" level, and inputs the serial data according to the values of the address signals B0 to B3 and A0 to A3. Detects that the mode has been entered.

Time t when time t _{ES has} elapsed from time t2
3, the CPU 40 sends the control data DI0 to DI15 together with the clock signal CLK to the error correction circuit 24.
Output to.

At time t4, the signal CE also changes to "L" level in response to the completion of output of the control data DI15.

In the FM multiplex broadcast demodulation LSI including the error correction circuit 24, for example, modes and parameters for error correction are set according to the control data DI0 to DI15.

Therefore, the error correction circuit 24 and the CP
When an intermediate processing device that performs a decoding process or the like is connected to U40, a delay corresponding to the time required for the decoding process or the like occurs. To cope with this, for example, lengthening the cycle of the clock signal CLK output from the CPU 40 causes an increase in data processing time.

Further, it is not desirable that the interface of the data input / output is changed by adding the intermediate processing device for performing the decoding process from the viewpoint of the ease of use for the user of the intermediate processing device.

Therefore, a main object of the present invention is to provide an intermediate processing device which can be applied as it is without changing the conventional interface configuration even when connected between devices for transmitting and receiving digital signals. Is.

Another object of the present invention is a decoding process which has an optimum structure for the data structure of FM multiplex broadcasting, can operate at high speed, and can be applied as it is without changing the conventional interface structure. It is to provide an intermediate processing device for performing.

[0040]

According to a first aspect of the present invention, there is provided a digital signal receiving apparatus, wherein frame data is composed of a plurality of packets, and the frame data is transmitted in FM multiplex communication in which the frame data is multiplexed into an FM broadcast for communication. A digital signal receiving apparatus for receiving the frame data, wherein the transmission data is a data packet including prefix data defining the contents of information data included in each packet and a data block including the information data. The prefix data includes a number of a data group to which the data packet belongs and a data bucket number of the data packet in the data group, and further, when the transmission data is encrypted and transmitted, the transmission data is transmitted. The data is the data group number and / or data Data packet number and demodulation of the frame data that is encrypted based on an initial value generated by the master key data included in a predetermined data packet of the plurality of data packets, that receives the transmission data, and is multiplexed. Demodulation means 20, 22 for performing
Error correction means 24 for performing error correction on the frame data demodulated by the demodulation means 20, 22 and outputting the data packet after the error correction, and the data packet after receiving the output of the error correction means 24 For each of the corresponding data packets, the key data extracting means for detecting the presence or absence of encryption for each of the predetermined data packets and extracting the master key data from the predetermined data packet when the data is encrypted The intermediate processing unit 100 that performs the decoding process of the information data that has been processed, and the output of the intermediate processing unit 100 that extracts the data blocks from the plurality of data packets and reconfigures and outputs the data group. And a data calculation means 40,
The output mode in which the data packet is output from the error correction means 24 to the data calculation means 40 side in accordance with the operation mode designation data given to the error correction means 24 and the data from the data calculation means 40 are One of the input modes to be input to the error correction means 24 is designated, the intermediate processing means 100 includes a control means 120, and the control means 120 (i) the error correction means 2
4, it is detected that the output preparation of the data packet is completed, and the operation mode designating data designating the output mode is outputted to the error correcting means 24, and the first operation control signal is outputted. Activate CS1 and (ii)
When the operation mode designation data output from the data operation unit 40 specifies the output mode, the second operation control signal CS2 is activated, and (iii) the operation output from the data operation unit 40. When the mode designating data designates the input mode, the operation mode designating data designating the input mode is output to the error correcting means 24, and the data from the data calculating means 40 is sent to the error correcting means 24. Output as it is, and further,
The intermediate processing means 100 outputs the first operation control signal C
The prefix data is input from the error correction means 24 in response to the activation of S1, and the packet data is sequentially input in series and output in series in response to the activation of the second operation control signal CS2. Further, based on the data storage means 102 for outputting the storage data in parallel and the initial value determined according to the prefix data received in parallel from the data storage means 102, the data is sequentially input to the data storage means. Data decoding processing means 110 for decoding the packet data.

The digital signal receiving apparatus according to claim 2 is
The structure of the digital signal receiving apparatus according to claim 1,
The storage capacity of the data storage means 102 is smaller than the bit length of one packet of the data packet.

The digital signal receiving apparatus according to claim 3 is
The structure of the digital signal receiving apparatus according to claim 2,
The intermediate processing means 100 outputs data to the error correcting means 24, and a first input terminal DI1 receiving the output of the error correcting means 24, a second input terminal DI2 receiving the output of the data calculating means 40. A first output terminal DO1 and a second output terminal D for outputting data to the data calculation means 40.
O2 is further provided, the output of the data storage means 102 and the second output terminal DO2 are connected, and the data decoding processing means 110 receives the data from the first input terminal DI1 and performs the data decoding processing. The result is the data storage means 1
02, the control means 120 sequentially inputs the data from the second input terminal DI2 in series, outputs the data in series to the first output terminal DO1, and inputs / outputs the data in parallel. Receiving parallel outputs from the second data storage means 126 and the second data storage means 126, the parallel output, input mode designation data designating the input mode and output mode designation data designating the output mode And a control circuit 122 that outputs a comparison result with
(I) the control circuit 122 detects that the output preparation of the data packet is completed in response to the trigger signal INTR1 from the error correction means 24, and the control circuit 122 stores the data in the second data storage means 126. On the other hand, the operation mode designating data designating the output mode is output in parallel,
The data is output in series to the first output terminal DO1, and (ii) the second input terminal DI2 is stored in the second data storage means 126.
When the output mode is designated in response to the comparison result of the comparison circuit 124 with respect to the operation mode designation data input from, the second operation control signal CS2 is activated, and (iii) the comparison result is received. When the input mode is designated, the second data storage means 1
24 to output the operation mode designation data in series to the first output terminal DO1 and to output the second input terminal DI2.
Data is sequentially input in series and output in series.

The digital signal receiving apparatus according to claim 4 is
The structure of the digital signal receiving apparatus according to claim 3,
The data decryption processing means 110 is based on the data group number and / or data packet number included in the prefix data received from the data storage means 102 and the master key data extracted by the key data extraction means. , An initial value determination processing means 112 for generating the initial value, a random number generation means 114 for outputting a pseudo random number sequence based on the initial value, and an activation of the second operation control signal CS2 by receiving the pseudo random number. In response to the conversion, the logic gate 116 that outputs corresponding data, the output of the logic gate 116 and the data from the first input terminal DI1 are received, and the exclusive OR operation result is stored in the data storage means 102. Exclusive-OR operation means 11 for outputting
8 and.

[0044]

[0045]

[0046]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows an F of an embodiment of the present invention.
FIG. 3 is a schematic block diagram showing a configuration of an intermediate processing device 100 that performs a decoding process in the M-multiplex broadcast receiving device.

The intermediate processing device 100 is connected between the error correction circuit 24 and the CPU 40 in the configuration of the conventional FM multiplex broadcast receiving device shown in FIG. Therefore, in the intermediate processing device 100, the address signals B0 to B3, A0 to A3 and the control data DI0 to DI from the CPU 40 are transmitted.
15 and demodulated data DI1 from the error correction circuit 24
To enter.

The intermediate processing device 100 performs a decoding process on the demodulated signal DI1, then outputs an output signal DO2 to the CPU 40, and outputs an output signal corresponding to an address signal and control data to the error correction circuit 24. Output to.

Before describing the details of the configuration and operation of the intermediate processing device 100, the configuration of transmitted packet data will be described below with reference to FIG.

As shown in Layer 3 in FIG. 7, a data packet is composed of a 32-bit prefix and a 144-bit data block following the prefix. FIG. 2 is a block diagram showing the data structure of this data packet.

The first 4 bits of the prefix are a service identification code. For example, when this value is 4, 5 or 6, it is assumed that the data block of the data packet to which this prefix belongs is scrambled. For the 1-bit decoding identification code following the service identification code, whether the error correction is performed with the correction code in the horizontal direction only,
Alternatively, it indicates whether to decode using a product code. The subsequent 1-bit information output code is "1" when the data group ends, and "0" otherwise.
Further, a 2-bit update code that follows the update code indicates an update of the data group.

The data group number existing in 9 to 22 bits means the data group to which the data packet belongs, and the data packet number existing in 23 to 32 bits means the order of the data packet transmitted for each data group number. Indicates.

The data blocks existing in 33 to 176 bits are the conventional FM multiplex broadcasting receiver 10 shown in FIG.
In the CPU 40, the CPU 40 is a part that is further reconfigured into a data group and program data, and is a main part of the data to be transmitted.

When the transmission data is scrambled and transmitted, the data in the data block area has an initial value generated by, for example, the master key data common to the data group and the data group number and the data packet number. Is encrypted and decrypted based on

That is, the data block data is encrypted based on different key data (initial value) for each packet, so that it is more difficult to decipher the information data and the confidentiality of the transmission data is improved. ing.

FIG. 3 is a schematic diagram showing the principle of a method of scrambling transmitted data and a method of descrambled encrypted received data.

FIG. 3 (a) shows the configuration for scrambling the transmission data, and FIG. 3 (b) shows the configuration for descrambling the reception data.
Referring to FIG. 3A, when scrambling transmission data, a pseudo-random binary sequence generation circuit 200 that generates, for example, an m-sequence (maximum-length sequence) based on predetermined key data is used. 2 generated
The result of the logical operation of the decimal pseudo random number and the transmission data by the exclusive OR circuit 202 is transmitted as the encrypted transmission data.

On the other hand, referring to FIG. 3B, on the side that receives the encrypted transmission data, a pseudo random binary sequence generation circuit is generated based on the predetermined key data used for the encryption in the transmission system. An exclusive OR circuit 2 for the binary pseudo-random number generated by 200 and the encrypted received data.
The result of the logical operation in 02 is output as decoded reception data.

The following points are characteristic of the above-described scramble method and descramble method.

That is, first, the same key data is used on the transmitting side and the receiving side.

Secondly, when the same key data is used, the pseudo random binary sequence generation circuit 200 always outputs a predetermined binary pseudo random number (for example, m sequence).

Thirdly, the binary transmission data returns to the original value when the exclusive OR operation with the same binary pseudo data is performed twice.

FIG. 4 is an operation explanatory view for explaining the operations when the transmission data is scrambled and descrambled by the above scramble method and descramble method.

FIG. 4A is a diagram showing an operation when scrambling the transmission data TD, and FIG. 4B is a diagram showing an operation when descramble the encrypted reception data CRD.

It is assumed that the output RS of the pseudo random binary sequence generation circuit 200 is an m sequence that changes in a cycle n.
In FIG. 4, all data are assumed to be 4 bits for the sake of simplicity.

Referring to FIG. 4A, when the transmission data TD is scrambled, for example, the key data is 0.
001 and the transmission data TD is 1010,
The exclusive OR value of the signals RS and TD is 1011.
This signal is transmitted as scrambled encrypted transmission data. Similarly, for the next transmission data TD 1101, the exclusive OR operation is performed with the output 0100 of the pseudo random binary sequence generation circuit 104, and the encrypted transmission data 1001 is transmitted. . The signal RS changes in the cycle n, and the transmission data TD and the exclusive OR operation result of the signal RS are sequentially transmitted as encrypted transmission data.

Referring to FIG. 4B, also on the receiving side, based on the same key data 0001 as on the transmitting side, the pseudo random binary sequence generation circuit 200 outputs an m-sequence signal RS. In this case, as described above, when the key data is based on the same key data, the same binary sequence as that on the transmitting side is output as the signal RS at the cycle n.

A signal sequence obtained by sequentially performing an exclusive OR of the signal RS and the encrypted received data CRD is shown in the right column of FIG. 4 (b). That is, the encrypted reception data CRD is the same signal RS and the exclusive OR operation performed twice on the transmission data TD. This value is the transmission data TD
It turns out that it agrees with.

The scrambling method and descrambling method for a digital signal represented by a binary number have been described above in a very simplified manner.

As described above, when scrambling the data transmitted by FM multiplex broadcasting, the reliability of the encryption mainly depends largely on the confidentiality of the key data.

Therefore, as described above, the key data is
A value that is updated for each packet is used instead of a single value, and as will be described later, a value that is further randomized for the master key data, data packet number, and data group number is used. .

The master key data is transmitted by being included in a predetermined position in a predetermined data packet for each group data, for example.

Therefore, in the intermediate processing device 100, after extracting the master key data,
There is a certain delay time until the key data is generated together with the data group number and the data packet number.

Returning to FIG. 1, the intermediate processing circuit 100 according to the embodiment of the present invention is roughly the first shift register 1
02, a data decoding processing circuit 110, and a control unit 120.

The data decoding processing circuit 110 receives predetermined data from the first shift register 102 and receives an output from the initial value determination processing circuit 112 for generating an initial value and the initial value determination processing circuit 112. From the error correction circuit 24, a pseudo random number generation circuit 114 that generates a pseudo random binary sequence, a logic gate circuit 116 that receives the output of the pseudo random number generation circuit 114, and outputs under the control of a second operation control signal. And an exclusive OR circuit 118 which receives the input data DI1 of the above, performs an exclusive OR operation, and outputs the exclusive OR operation to the first shift register 102.

The control section 120 is controlled by the control circuit 122 and the second shift register 1 which is controlled by the control circuit 122 and receives the address signal and the control data from the CPU 40.
26 and the address signal input to the second shift register 126 in parallel to detect whether the input mode is specified or the output mode is specified.
24 and 24.

[Operation of Intermediate Processing Device in Output Mode] In the following, first, the operation of the intermediate processing device 100 receiving the demodulated data DI1 output from the error correction circuit 24, performing decoding processing, and then outputting it to the CPU 40. (Serial data output mode) will be described.

In the following description, the shift register 10
In order to control the operations of 2 and 126 and the like, clock signals given to them are actually necessary, but they are omitted for simplicity of explanation.

FIG. 5 is a timing chart showing the operation of the intermediate processing device 100 in the serial data output mode operation.

Referring to FIGS. 1 and 5, when the error correction circuit 24 detects that the demodulation of the data corresponding to one packet of the received data transmitted by the FM multiplex broadcasting is completed, at time t0. , And outputs a pulse-shaped “H” level first interrupt signal INTR1.

When the control circuit 122 detects that the interrupt signal INTR1 has become "H" level, it outputs address signals B0-B3 and A0-A3 designating an output mode to the second shift register 126. Output in parallel.

The second shift register 126 has a time t2.
At the time, under the control of the control circuit 122, the address signal and the error correction circuit 24 are started to be output in series.

The control circuit 122 causes the second circuit at the time t4.
When the output of the address signal from the shift register 126 is completed, the signal CE1 is changed from the "L" level to the "H" level. In response to this, the error correction circuit 24
It is detected that the output of the address signal is completed, and the address signals B0 to B3 and A0 to A3 are data for designating the output mode, that is, BO0 to BO3 and AO0 to AO3.
Is detected.

The control circuit 122 starts from time t4 to time t _ES.
At time t6 that has passed, the first operation control signal CS1
The operation of the first shift register 102 is controlled by
Data (32 bits) corresponding to the prefix of the packet data is input from the error correction circuit 24 to the first shift register 102.

At this time, since the signal CS2 is at "L" level, the output of the AND circuit 116 is also at "L" level, and the exclusive OR gate circuit 118 outputs the demodulated data DI.
1 is output as it is to the first shift register 102.

The first shift register 102 is, for example, a 32-bit shift register, although not particularly limited, and sequentially inputs the packet data output from the error correction circuit 24.

When the initial value determination processing circuit 112 detects that the prefix of the packet data is input to the first shift register 102 at time t7, it receives a parallel output from the first shift register 102 and outputs the data group number and The data packet number is extracted, and based on the master key data previously extracted by the key data extraction circuit (not shown), the generation of the initial value for generating the pseudo random number is started, and is completed at time t9.

On the other hand, the control circuit 122 requires, for example, until the initial value determination processing circuit 112 generates an initial value after the first interrupt signal INTR1 is activated ("H" level state). After the delay time has elapsed (time t
In 3), a pulsed second interrupt signal INTR2 is output to the CPU 40.

The CPU 40 uses the second interrupt signal INTR2.
In response to the activation of, the address signals B0 to B3 and A0 to A3 corresponding to the output mode are output after a lapse of a predetermined time after the fall of the interrupt signal INTR2. The second shift register 126 inputs this address signal, receives the parallel output from the second shift register 126, and the comparison circuit 124 detects that the output mode is designated.

When the control circuit 122 detects that the CPU 40 specifies the serial data output mode based on the comparison result of the comparison circuit 124, it activates the second operation control signal CS2.

The random number generation circuit 114 generates a pseudo random binary sequence (for example, m sequence (maximum-length sequence)) based on the initial value from the initial value determination processing circuit 112 in response to the activation of the signal CS2. To generate.

The AND circuit 116 is the pseudo random number generation circuit 1
The signal CS2 is “H” in response to the output of the signal No. 14 and the signal CS2.
The output of the pseudo random number generation circuit 114 is output to the exclusive OR gate circuit 118 during the level period.

The exclusive OR gate circuit 118 performs an AND operation.
By performing an exclusive OR operation between the output signal of the circuit 116 and the input signal DI1 from the error correction circuit 24, the input signal DI1 is decoded and output to the first shift register 102.

The first shift register 102 sequentially outputs the output from the exclusive OR gate circuit 118 to 1 at time t10 in response to the activation of the second operation control signal CS2.
Bit by bit input in series and output to the CPU 40 starts.

At this time, the first shift register 10 has already been
Data of prefix part DO0 input in 2
The DO 31 is output to the CPU 40 as it is and the data D03 of the data block portion following the prefix
2 to DO175 are sequential exclusive OR gate circuits 118
Then, the data is decrypted and then output to the CPU 40.

Since the pseudo random binary sequence output from the pseudo random number generation circuit 114 is generated by the same initial value and the same arithmetic processing used for encryption when transmitting the FM multiplex broadcast, As with the pseudo-random binary sequence in encryption, the decryption process is performed according to the principle described with reference to FIGS. 3 and 4.

As a result of the above operation, when viewed from the error correction circuit 24, when the error correction circuit 24 detects the completion of receiving one packet of data and outputs the first interrupt signal INTR1, first, the error correction is performed. The circuit 24 outputs data for 32 bits, that is, data for only prefix data. Then, after a lapse of a predetermined time, the error correction circuit 24 starts from 33 bits to 17 bits of the data of one packet.
6-bit data, that is, data corresponding to the data block data is output, and the data output for one packet is completed. In this case, the error correction circuit 24 has the first
After the interrupt signal INTR1 of 1 is activated, the address signals BO0 to BO3 and AO0 to AO3 designating the serial data output mode are applied, and the data for one packet is sequentially output bit by bit. There is no need to change the interface of the correction circuit 24.

On the other hand, when viewed from the CPU 40, the CPU 4
0 receives the second interrupt signal INTR2 and sequentially inputs data for 176 bits, that is, for one packet, bit by bit. Therefore, even when viewed from the CPU 40, it is possible to input data with the same interface configuration as when there is no intermediate processing device 100.

In the above description, the second interrupt signal IN
After the activation of TR2, if the comparison circuit 124 detects that the address signals B0 to B3 and A0 to A3 input from the CPU 40 to the second shift register 126 specify the serial data input mode, the following is performed. As described, the control data from the CPU 40 is output to the error correction circuit 24 via the second shift register 126.

[Operation of Intermediate Processing Device in Input Mode] Next, the serial data input mode is designated by the CPU 40, and the control data DI0 to DI0 are sent from the CPU 40 to the FM multiplex broadcast demodulation LSI including the error correction circuit 24.
The operation of the intermediate processing device 100 when the DI 15 is output will be described.

FIG. 6 is a timing chart showing the operation of the intermediate processing device 100 in the serial data input mode.

At time t1, address signals BI0-B0 for specifying the serial data input mode from CPU 40.
The output of I3 and AI0 to AI3 is started.

In order to notify that the output of the address signal from the CPU 40 is completed, the signal C is output at the time t2.
E2 changes from "L" level to "H" level.

The control circuit 122 receives the second signal from the comparison circuit 124 in response to the signal CE2 becoming "H" level.
The result of comparison between the address signal in shift register 126 and the data designating the serial data input mode is received.

When the control circuit 122 detects that the address signal specifies the serial data input mode,
At time t3, the data input to the second shift register 126 is sequentially output as the signal DO1 and output to the error correction circuit 24 is started.

When the output of the address signal from the second shift register 126 is completed, at time t4, the control circuit 122 changes the signal CE1 from the "L" level to the "H" level to cause the error correction circuit. 24 is informed that the output of the address data is completed.

On the other hand, the CPU 40 at time t2
The output of the control data DI0 to DI15 is started after the time t _ES elapses after the signal CE2 is set to the “H” level.

The second shift register 126 receives the signal CE.
Time t after 1 becomes "H" level _ESIt will be input sequentially after the elapse
The corrected control data DI0 to DI15 are sent to the error correction circuit 24.
Output to. By the above operation, the error correction circuit 24
From the intermediate processing device 100, the address signal
B0 to B3 and A0 to A3 are output, and the output is completed.
Is detected when the signal CE1 goes to "H" level.
It Furthermore, after the signal CE1 changes to the “H” level,
Time t_ESAfter the lapse of time, the output of the control data DI0 to DI15 is
Will be started. Therefore, the error correction circuit 24
Address signal and control data input to the intermediate processing
The interface configuration is exactly the same as when there is no device 100.
Will be done.

On the other hand, when viewed from the CPU 40, after the address signals B0 to B3 and A0 to A3 are output and the completion of the output is indicated by setting the signal CE2 to the "H" level,
After the time t _{ES has} elapsed, the control data DI0 to DI15 are output.

Therefore, even when viewed from the CPU 40,
Address data and control data can be output with the same interface configuration as when there is no intermediate processing device 100.

That is, by adopting the configuration of the embodiment of the present invention, the error correction circuit 24 can be simply connected by connecting the intermediate processing device 100 without making any changes to the configuration of the interface of the error correction circuit 24 and the CPU 40. It is possible to perform the decoding processing of the data output from the CPU and the transmission of the control data output from the CPU 40 to the error correction circuit 24.

Moreover, the number of bits of the first shift register 102 can be made smaller than the number of bits of one packet, and the delay caused by the data passing through this shift register 102 is suppressed to the minimum. It is possible.

[0113]

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing a configuration of an intermediate processing device 100 according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the structure of packet data in FM multiplex broadcasting.

3A and 3B are principle diagrams showing the principle of a scramble method and a descramble method. FIG. 3A shows the principle of a scramble method in a transmission system, and FIG. 3B shows the principle of a descramble method in a reception system.

4A and 4B are operation explanatory diagrams showing operations of the scramble method and the descramble method shown in FIG. 3, where FIG. 4A shows an operation of the scramble method and FIG. 4B shows an operation of the descramble method.

FIG. 5 is a timing chart showing an operation of the intermediate processing device according to the present invention in a serial data output mode.

FIG. 6 is a timing chart showing an operation in the serial data input mode of the intermediate processing device according to the present invention.

FIG. 7 is a specification diagram showing an example of a data structure in FM multiplex broadcasting.

FIG. 8 is a schematic block diagram showing a configuration of a conventional FM multiplex broadcast receiving apparatus.

9A and 9B are timing charts showing data input / output in a conventional FM multiplex broadcast receiving apparatus, FIG. 9A showing an operation in a serial data output mode, and FIG. 9B showing an operation in a serial data input mode.

[Explanation of symbols] 10 Conventional FM multiplex broadcasting receiver 12 antennas 14 Tuner 16 Detection circuit 18 bandpass filter 20 LMSK demodulation circuit 22 Synchronous playback circuit 24 Error correction circuit 40 CPU 42 display device 100 Intermediate processor 102 first shift register 110 data decoding processing circuit 112 initial value determination processing circuit 114 random number generation times 116 AND circuit 118 Exclusive OR gate circuit 120 control unit 122 control circuit 124 Comparison circuit 126 second shift register

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-95296 (JP, A) Yutaka Hirasha, Outline of FM character multiplex LSI, broadcasting technology, Japan, 47, 704-708 (58) Survey Areas (Int.Cl. ⁷ , DB name) H04H 1/00-1/02

Claims (4)

(57) [Claims] 1. The frame data is composed of a plurality of packets.
The frame data is multiplexed and transmitted to the FM broadcast.
The frame transmitted in FM multiplex communication
A digital signal receiving device for receiving data, wherein each packet of the transmission data is included in the packet.
Prefix data that defines the content of the information data
And a data pattern including a data block including the information data.
And the prefix data is
The number of the data group to which the data packet belongs and the data group
Data packet of the data packet in the data group
In addition, the transmission data is encrypted.
When transmitted by the data group, the transmission data is
Packet number and / or data packet number and the plurality of data packets.
Data contained in a given data packet
Based on the initial value generated by the
Has been encoded , received the transmission data, and multiplexed the frame data.
Demodulating means 20 and 22 for demodulating data and the demodulating means 2
For the frame data demodulated by 0,22
After error correction, the data packet after error correction is
Error correction means 24 for outputting data and the error correction means 24
Is received, the encryption of each data packet is
If nothing is detected and it is encrypted, the specified data
Key data acquisition to extract master key data from packets
Output means and the corresponding data based on the initial value
Decryption processing of the information data encrypted for each packet
Of the intermediate processing means 100 for performing
Upon receipt of the output, the data from the plurality of data packets
Data blocks and reconstruct the data group
And an operation mode designation data provided to the error correction means 24.
Data operation means from the error correction means 24 according to the data
Output mode in which the data packet is output to the 40 side
And the data from the data calculation means 40
Either input mode to input to the corrector 24 side is specified
Is, the intermediate processing unit 100 includes a control unit 120, the control unit 120 detects in (i) the error correction unit 24, the output preparation of the data path <br/> packet is completed , Said mistake
The operation mode designating data designating the output mode is output to the correcting means 24 to activate the first operation control signal CS1 , and (ii) the operation mode output from the data computing means 40. When the designated data designates the output mode, the second operation control signal CS2 is activated, and (iii) the operation mode designation data output from the data operation unit 40 designates the input mode. In this case, the operation mode designating data designating the input mode is output to the error correcting means 24 , and the data computing unit is operated.
The data from the stage 40 is output to the error correction means 24 as it is, and the intermediate processing means 100 further outputs the first operation control signal C.
In response to the activation of S1, the error correction means 24 outputs the
Prefix data is input , and in accordance with activation of the second operation control signal CS2 , the packet data is serially input and serially output, and storage data is output in parallel, and a data storage unit 102 . , The prefetches received in parallel from the data storage means 102
Based on the initial value determined according to the six data
The data decoding processing means 110 for decoding the packet data sequentially input to the data storage means.
And a digital signal receiving device characterized by
Place 2. The storage capacity of the data storage means 102 is based on the bit length of one packet of the data packet.
The digital signal receiving apparatus according to claim 1 , which is also small . 3. The intermediate processing means 100 is configured to correct the error.
A first input terminal DI1 receiving an output of positive means 24, the
Second input terminal DI2 for receiving the output of the data calculation means 40
When the first output terminal DO1 to the data output to the error correction means 24, further comprising a said data to the arithmetic unit 40 to the data output <br/> second output DO2, the data storage Hand
The output of the stage 102 is connected to the second output terminal DO2 , and the data decoding processing means 110 is connected to the first input terminal D2.
After receiving the data from I1 , the data decoding processing result is
The data is output to the data storage unit 102 , the control unit 120 sequentially inputs the data from the second input terminal DI2 in series, outputs the data in series to the first output terminal DO1 , and outputs the data in parallel. A second data storage means 126 for inputting / outputting, and the second data storage means 1
26 parallel outputs, the parallel output and the input mode are received.
Input mode specification data for specifying the mode and the output mode
A comparison circuit 124 for outputting a result of comparison between the output mode specifying data for specifying the de, and a control circuit 122, the control circuit 122, (i) a trigger signal from said error correcting means 24 INTR
1 is detected that the output preparation of the data packet is completed, and the operation mode designating data designating the output mode is outputted in parallel to the second data storage means 126 to output the operation mode designating data. to 1 of the output terminal DO1 is outputted in series, receives the comparison result of the comparator circuit 124 for (ii) the operation mode designating data inputted from the second input terminal DI2 to the second data storage unit 126, When the output mode is designated, the second operation control signal
When CS2 is activated, (iii) when the input mode is designated in response to the comparison result, the operation mode designation data is serially connected to the second data storage means 124 to the first output terminal DO1 . 3. The data is output, and the data from the second input terminal DI2 is sequentially input in series and output in series.
The digital signal receiving device described. 4. The data decoding processing means 110 receives the prefix received from the data storage means 102.
Data group number and / or included in the
By the data packet number and the key data extraction means
Based on the extracted master key data, the first
Initial value determination processing means 112 for generating a period value, and a random number generator for outputting a pseudo random number sequence based on the initial value.
Stage 114 and the second operation control signal CS2 for receiving the pseudo-random number.
A logic game that outputs the corresponding data according to the activation of
116, the output of the logic gate 116 and the first input terminal DI1
The data from the
Exclusive OR operation means 1 for outputting to the data storage means 102
The digital signal receiving apparatus according to claim 3, further comprising: