JP3287310B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP3287310B2 JP3287310B2 JP19812798A JP19812798A JP3287310B2 JP 3287310 B2 JP3287310 B2 JP 3287310B2 JP 19812798 A JP19812798 A JP 19812798A JP 19812798 A JP19812798 A JP 19812798A JP 3287310 B2 JP3287310 B2 JP 3287310B2
- Authority
- JP
- Japan
- Prior art keywords
- thermal expansion
- coefficient
- film
- insulating film
- sealing film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】この発明は半導体装置及びそ
の製造方法に関する。The present invention relates to a semiconductor device and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】例えば、ＣＳＰ(Chip Size Package)と
呼ばれる半導体装置を配線基板上にフェイスダウンボン
ディング方式と呼ばれる実装技術により実装することが
ある。図８は従来のこのような半導体装置の実装構造の
一例の断面図を示したものである。半導体装置１は平面
方形状のシリコン基板２を備えている。シリコン基板２
の下面の外周部には複数の接続パッド３が形成されてい
る。接続パッド３の中央部を除くシリコン基板２の下面
全体には絶縁膜４が形成され、接続パッド３の中央部が
絶縁膜４に形成された開口部５を介して露出されてい
る。この露出された接続パッド３の下面から絶縁膜４の
下面にかけて配線（下地金属層）６が形成されている。
この場合、配線６は、接続パッド３下に形成された接続
部６ａと、絶縁膜４の下面の所定の箇所に形成された接
続パッド部６ｂと、その間に形成された引き回し線６ｃ
とからなっている。接続パッド部６ｂの下面には銅や金
等からなる柱状電極７が形成されている。柱状電極７を
除く絶縁膜４の下面にはエポキシ樹脂からなる封止膜８
が形成されている。柱状電極７の下面には半田バンプ９
が形成されている。そして、半導体装置１の半田バンプ
９がガラスエポキシ等からなる配線基板１０の上面に形
成された接続パッド１１にフェイスダウンボンディング
されていることにより、半導体装置１は配線基板１０上
に実装されている。なお、一例として、封止膜８の絶縁
膜４下における厚さは５０〜１００μｍ程度であり、半
田バンプ９のボンディング後における高さは８０μｍ程
度である。2. Description of the Related Art For example, a semiconductor device called a CSP (Chip Size Package) is sometimes mounted on a wiring board by a mounting technology called a face-down bonding method. FIG. 8 is a sectional view showing an example of a conventional mounting structure of such a semiconductor device. The semiconductor device 1 includes a planar silicon substrate 2. Silicon substrate 2
A plurality of connection pads 3 are formed on the outer peripheral portion of the lower surface of. An insulating film 4 is formed on the entire lower surface of the silicon substrate 2 except for the central portion of the connection pad 3, and the central portion of the connection pad 3 is exposed through an opening 5 formed in the insulating film 4. A wiring (base metal layer) 6 is formed from the exposed lower surface of the connection pad 3 to the lower surface of the insulating film 4.
In this case, the wiring 6 includes a connection portion 6a formed below the connection pad 3, a connection pad portion 6b formed at a predetermined location on the lower surface of the insulating film 4, and a lead line 6c formed therebetween.
It consists of A columnar electrode 7 made of copper, gold, or the like is formed on the lower surface of the connection pad portion 6b. A sealing film 8 made of epoxy resin is formed on the lower surface of the insulating film 4 except for the columnar electrodes 7.
Are formed. A solder bump 9 is provided on the lower surface of the columnar electrode 7.
Are formed. The semiconductor device 1 is mounted on the wiring board 10 because the solder bumps 9 of the semiconductor device 1 are face-down bonded to the connection pads 11 formed on the upper surface of the wiring board 10 made of glass epoxy or the like. . As an example, the thickness of the sealing film 8 under the insulating film 4 is about 50 to 100 μm, and the height of the solder bump 9 after bonding is about 80 μm.
【０００３】[0003]
【発明が解決しようとする課題】ところで、シリコン基
板２を構成するシリコンの熱膨張係数は２〜３ｐｐｍ／
℃程度であり、封止膜８を構成する封止樹脂の熱膨張係
数は１０〜１５ｐｐｍ／℃程度であり、配線基板１０を
構成する例えばガラスエポキシの熱膨張係数は１５ｐｐ
ｍ／℃程度である。このように、封止膜８の熱膨張係数
は、配線基板１０の熱膨張係数に近い値であり、シリコ
ン基板２の熱膨張係数との差が比較的大きい。この結
果、温度変化により、シリコン基板２と封止膜８との間
にその熱膨張係数差に起因する比較的大きな応力が生じ
たとき、柱状電極７と半田バンプ９との接合部分あるい
は半田バンプ９と接続パッド１１との接合部分にクラッ
クが発生し、接合不良が生じることがあるという問題が
あった。この発明の課題は、シリコン基板（半導体基
板）と封止膜との熱膨張係数差等の特性差に起因する応
力を小さくすることである。Incidentally, the silicon constituting the silicon substrate 2 has a thermal expansion coefficient of 2 to 3 ppm /
° C, the thermal expansion coefficient of the sealing resin forming the sealing film 8 is about 10 to 15 ppm / ° C, and the thermal expansion coefficient of, for example, glass epoxy forming the wiring board 10 is 15 pp.
m / ° C. As described above, the coefficient of thermal expansion of the sealing film 8 is a value close to the coefficient of thermal expansion of the wiring substrate 10, and the difference from the coefficient of thermal expansion of the silicon substrate 2 is relatively large. As a result, when a relatively large stress is generated between the silicon substrate 2 and the sealing film 8 due to a difference in thermal expansion coefficient between the silicon substrate 2 and the sealing film 8, the joining portion between the columnar electrode 7 and the solder bump 9 or the solder bump There is a problem that a crack may occur in a joint portion between the contact pad 9 and the connection pad 11 and a joint failure may occur. An object of the present invention is to reduce a stress caused by a characteristic difference such as a thermal expansion coefficient difference between a silicon substrate (semiconductor substrate) and a sealing film.
【０００４】[0004]
【課題を解決するための手段】請求項１記載の発明に係
る半導体装置は、半導体基板上に形成された絶縁膜に形
成された開口部を介して接続パッドが露出され、前記接
続パッド上から前記絶縁膜上にかけて接続パッド部を有
する配線が形成され、前記配線の接続パッド部上に電極
が形成され、前記電極を除く前記絶縁膜上に封止膜が形
成された半導体装置において、前記封止膜の特性をその
厚さ方向で異ならせ、該封止膜の前記絶縁膜側の特性を
前記半導体基板の特性に近づけたものである。請求項２
記載の発明に係る半導体装置は、請求項１記載の発明に
おいて、前記特性が熱膨張係数であることを特徴とする
ものである。請求項７記載の発明に係る半導体装置の製
造方法は、半導体基板上に形成された絶縁膜に形成され
た開口部を介して接続パッドが露出され、前記接続パッ
ド上から前記絶縁膜上にかけて接続パッド部を有する配
線が形成され、前記配線の接続パッド部上に電極が形成
され、前記電極を除く前記絶縁膜上に封止膜が形成され
た半導体装置の製造に際し、前記電極を除く前記絶縁膜
上に、少なくとも、樹脂中に熱膨張係数低下用粒子が混
入されたものからなり、熱膨張係数を前記半導体基板の
熱膨張係数に近い値とされた下側封止膜と、樹脂中に熱
膨張係数低下用粒子が混入されたものからなり、熱膨張
係数を樹脂の熱膨張係数よりも小さく且つ前記下側封止
膜の熱膨張係数よりも大きい値とされた中間封止膜と、
樹脂のみからなる上側封止膜とを形成して、これらの封
止膜により前記封止膜を形成するようにしたものであ
る。請求項８記載の発明に係る半導体装置の製造方法
は、半導体基板上に形成された絶縁膜に形成された開口
部を介して接続パッドが露出され、前記接続パッド上か
ら前記絶縁膜上にかけて接続パッド部を有する配線が形
成され、前記配線の接続パッド部上に電極が形成され、
前記電極を除く前記絶縁膜上に封止膜が形成された半導
体装置の製造に際し、前記電極を除く前記絶縁膜上に、
径の異なる複数種類の熱膨張係数低下用粒子が混入され
た単一の樹脂膜を形成し、次いでこの熱膨張係数低下用
粒子の混入された樹脂膜の熱膨張係数を表面側から前記
絶縁膜側に向かうに従って漸次小さくなるようにし、こ
れにより前記封止膜を形成するようにしたものである。
請求項９記載の発明に係る半導体装置の製造方法は、半
導体基板上に形成された絶縁膜に形成された開口部を介
して接続パッドが露出され、前記接続パッド上から前記
絶縁膜上にかけて接続パッド部を有する配線が形成さ
れ、前記配線の接続パッド部上に電極が形成され、前記
電極を除く前記絶縁膜上に封止膜が形成された半導体装
置の製造に際し、前記電極を除く前記絶縁膜上に、径の
異なる複数種類の熱膨張係数低下用粒子が混入された単
一の樹脂膜を形成し、次いでこの樹脂膜中における前記
熱膨張係数低下用粒子の体積比を表面側から前記絶縁膜
側に向かうに従って漸次大きくなるようにし、これによ
り前記封止膜を形成するようにしたものである。この発
明によれば、封止膜の熱膨張係数等の特性をその厚さ方
向で異ならせ、封止膜の絶縁膜側の熱膨張係数等の特性
を半導体基板の熱膨張係数等の特性に近づけているの
で、半導体基板と封止膜との熱膨張係数差等の特性差に
起因する応力を小さくすることができる。According to a first aspect of the present invention, in a semiconductor device, a connection pad is exposed through an opening formed in an insulating film formed on a semiconductor substrate, and the connection pad is exposed from above the connection pad. In the semiconductor device, a wiring having a connection pad portion is formed over the insulating film, an electrode is formed on the connection pad portion of the wiring, and a sealing film is formed on the insulating film excluding the electrode. The characteristics of the stop film are varied in the thickness direction, and the characteristics of the sealing film on the insulating film side are made closer to the characteristics of the semiconductor substrate. Claim 2
A semiconductor device according to the invention described in the first aspect is characterized in that the characteristic is a coefficient of thermal expansion. According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device, the connection pad is exposed through the opening formed in the insulating film formed on the semiconductor substrate, and the connection is performed from the connection pad to the insulating film. In manufacturing a semiconductor device in which a wiring having a pad portion is formed, an electrode is formed on a connection pad portion of the wiring, and a sealing film is formed on the insulating film except for the electrode, the insulation except for the electrode is removed. On the film, at least, a lower sealing film having a coefficient of thermal expansion set to a value close to the coefficient of thermal expansion of the semiconductor substrate, which is made of a resin mixed with particles for lowering the coefficient of thermal expansion in a resin, and in the resin. An intermediate sealing film made of a mixture of particles for lowering the coefficient of thermal expansion, having a coefficient of thermal expansion smaller than the coefficient of thermal expansion of the resin and a value larger than the coefficient of thermal expansion of the lower sealing film,
An upper sealing film made of only a resin is formed, and the sealing film is formed by these sealing films. In the method of manufacturing a semiconductor device according to the present invention, the connection pad is exposed through an opening formed in the insulating film formed on the semiconductor substrate, and the connection is made from the connection pad to the insulating film. A wiring having a pad portion is formed, an electrode is formed on a connection pad portion of the wiring,
In manufacturing a semiconductor device having a sealing film formed on the insulating film excluding the electrode, on the insulating film excluding the electrode,
Forming a single resin film in which a plurality of types of particles for reducing the coefficient of thermal expansion having different diameters are mixed, and then measuring the thermal expansion coefficient of the resin film in which the particles for reducing the coefficient of thermal expansion are mixed from the front side to the insulating film; The sealing film is formed so as to become gradually smaller toward the side.
According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor device, the connection pad is exposed through an opening formed in the insulating film formed on the semiconductor substrate, and the connection is made from the connection pad to the insulating film. In manufacturing a semiconductor device in which a wiring having a pad portion is formed, an electrode is formed on a connection pad portion of the wiring, and a sealing film is formed on the insulating film except for the electrode, the insulation except for the electrode is removed. On the film, to form a single resin film in which a plurality of types of particles having a different coefficient of thermal expansion coefficient having different diameters are mixed, and then, the volume ratio of the particles for lowering the thermal expansion coefficient in the resin film is determined from the surface side. The sealing film is formed so as to gradually increase toward the insulating film side. According to the present invention, the characteristics such as the coefficient of thermal expansion of the sealing film are made different in the thickness direction, and the characteristics such as the coefficient of thermal expansion of the insulating film side of the sealing film are changed to the characteristics such as the coefficient of thermal expansion of the semiconductor substrate. Since they are close to each other, it is possible to reduce a stress caused by a characteristic difference such as a thermal expansion coefficient difference between the semiconductor substrate and the sealing film.
【０００５】[0005]
【発明の実施の形態】図１はこの発明の第１実施形態に
おける半導体装置の実装構造の断面図を示したものであ
る。半導体装置２１は平面方形状のシリコン基板２２を
備えている。シリコン基板２２の下面の外周部には複数
の接続パッド２３が形成されている。接続パッド２３の
中央部を除くシリコン基板２２の下面全体には絶縁膜２
４が形成され、接続パッド２３の中央部が絶縁膜２４に
形成された開口部２５を介して露出されている。この露
出された接続パッド２３の下面から絶縁膜２４の下面に
かけて配線（下地金属層）２６が形成されている。この
場合、配線２６は、接続パッド２３下に形成された接続
部２６ａと、絶縁膜２４の下面の所定の箇所に形成され
た接続パッド部２６ｂと、その間に形成された引き回し
線２６ｃとからなっている。接続パッド部２６ｂの下面
には銅や金等からなる柱状電極２７が形成されている。FIG. 1 is a sectional view showing a mounting structure of a semiconductor device according to a first embodiment of the present invention. The semiconductor device 21 includes a planar silicon substrate 22. A plurality of connection pads 23 are formed on the outer periphery of the lower surface of the silicon substrate 22. The insulating film 2 is formed on the entire lower surface of the silicon substrate 22 except for the central portion of the connection pad 23.
4 are formed, and a central portion of the connection pad 23 is exposed through an opening 25 formed in the insulating film 24. A wiring (base metal layer) 26 is formed from the exposed lower surface of the connection pad 23 to the lower surface of the insulating film 24. In this case, the wiring 26 includes a connection portion 26a formed below the connection pad 23, a connection pad portion 26b formed at a predetermined location on the lower surface of the insulating film 24, and a leading line 26c formed therebetween. ing. A columnar electrode 27 made of copper, gold, or the like is formed on the lower surface of the connection pad portion 26b.
【０００６】柱状電極２７を除く絶縁膜２４の下面には
封止膜２８が形成されている。封止膜２８は、絶縁膜２
４側から順に、エポキシ樹脂２９ａ中にシリカ粒子２９
ｂを混入してなる下側封止膜２９、エポキシ樹脂３０ａ
中にシリカ粒子３０ｂを混入してなる中間封止膜３０、
エポキシ樹脂のみからなる上側封止膜３１の３層構造と
なっている。この場合、シリカ粒子２９ｂ、３０ｂは熱
膨張係数を低下させるためのものであり、その径は同じ
であるが、シリカ粒子２９ｂのエポキシ樹脂２９ａ中へ
の混入率がシリカ粒子３０ｂのエポキシ樹脂３０ａ中へ
の混入率よりも大きくなっている。これにより、下側封
止膜２９の熱膨張係数はシリコン基板２２の熱膨張係数
に近い値となっている。また、中間封止膜３０の熱膨張
係数は、エポキシ樹脂の熱膨張係数よりも小さく且つ下
側封止膜２９の熱膨張係数よりも大きい値となってい
る。この場合、封止膜２８が３層構造であるので、中間
封止膜３０の熱膨張係数は、下側封止膜２９の熱膨張係
数と上側封止膜３１の熱膨張係数との中間の値となって
いる。さらに、上側封止膜３１の熱膨張係数は、エポキ
シ樹脂のみからなるので、後述する配線基板３３を構成
する例えばガラスエポキシの熱膨張係数に近い値となっ
ている。A sealing film 28 is formed on the lower surface of the insulating film 24 except for the columnar electrodes 27. The sealing film 28 is made of the insulating film 2
In order from the 4th side, silica particles 29 are contained in epoxy resin 29a.
b, lower sealing film 29, epoxy resin 30a
An intermediate sealing film 30, in which silica particles 30b are mixed,
It has a three-layer structure of an upper sealing film 31 made of only epoxy resin. In this case, the silica particles 29b and 30b are for reducing the coefficient of thermal expansion and have the same diameter, but the mixing ratio of the silica particles 29b into the epoxy resin 29a is less than that of the silica particles 30b in the epoxy resin 30a. It is larger than the mixing ratio to Thereby, the thermal expansion coefficient of the lower sealing film 29 is a value close to the thermal expansion coefficient of the silicon substrate 22. The thermal expansion coefficient of the intermediate sealing film 30 is smaller than the thermal expansion coefficient of the epoxy resin and larger than the thermal expansion coefficient of the lower sealing film 29. In this case, since the sealing film 28 has a three-layer structure, the thermal expansion coefficient of the intermediate sealing film 30 is intermediate between the thermal expansion coefficient of the lower sealing film 29 and the thermal expansion coefficient of the upper sealing film 31. Value. Further, the thermal expansion coefficient of the upper sealing film 31 is a value close to the thermal expansion coefficient of, for example, glass epoxy constituting the wiring board 33 to be described later, since the thermal expansion coefficient is made only of the epoxy resin.
【０００７】柱状電極２７の下面には半田バンプ３２が
形成されている。そして、半導体装置２１の半田バンプ
３２がガラスエポキシ等からなる配線基板３３の上面に
形成された接続パッド３４にフェイスダウンボンディン
グされていることにより、半導体装置２１は配線基板３
３上に実装されている。そして、この場合も、一例とし
て、封止膜２８の絶縁膜２４下における厚さは５０〜１
００μｍ程度であり、半田バンプ３２のボンディング後
における高さは８０μｍ程度である。[0007] A solder bump 32 is formed on the lower surface of the columnar electrode 27. The semiconductor device 21 is mounted on the wiring board 3 by face-down bonding the solder bumps 32 of the semiconductor device 21 to the connection pads 34 formed on the upper surface of the wiring board 33 made of glass epoxy or the like.
3 is implemented. Also in this case, as an example, the thickness of the sealing film 28 under the insulating film 24 is 50 to 1
The height of the solder bump 32 after bonding is about 80 μm.
【０００８】このように、この半導体装置の実装構造で
は、封止膜２８を、熱膨張係数をシリコン基板２２の熱
膨張係数に近い値とされた下側封止膜２９と、熱膨張係
数を下側封止膜２９の熱膨張係数と上側封止膜３１の熱
膨張係数との中間の値とされた中間封止膜３０と、熱膨
張係数を配線基板３３の熱膨張係数に近い値とされた上
側封止膜３１との３層構造としている。この結果、温度
変化により、シリコン基板２２と封止膜２８との間にそ
の熱膨張係数差に起因する応力が生じても、封止膜２８
のうちシリコン基板２２側の下側封止膜２９とシリコン
基板２２との熱膨張係数差に起因する応力を小さくする
ことができ、ひいては柱状電極２７と半田バンプ３２と
の接合部分あるいは半田バンプ３２と接続パッド３４と
の接合部分にクラックが発生することがなく、接合の信
頼性を高めることができる。As described above, in the mounting structure of the semiconductor device, the sealing film 28 has a lower thermal expansion coefficient of a value close to the thermal expansion coefficient of the silicon substrate 22 and a lower thermal expansion coefficient of An intermediate sealing film 30 having an intermediate value between the thermal expansion coefficient of the lower sealing film 29 and the thermal expansion coefficient of the upper sealing film 31; It has a three-layer structure with the upper sealing film 31 formed. As a result, even if a stress due to a difference in thermal expansion coefficient between the silicon substrate 22 and the sealing film 28 occurs due to a temperature change, the sealing film 28
Out of the lower sealing film 29 on the silicon substrate 22 side and the stress caused by the difference in thermal expansion coefficient between the silicon substrate 22 and the joint between the columnar electrode 27 and the solder bump 32 or the solder bump 32 Cracks do not occur at the joints between the contact pads and the connection pads 34, and the joining reliability can be improved.
【０００９】次に、図１に示す半導体装置２１の製造方
法の一例について、図２〜図６を順に参照して説明す
る。まず、図２に示すように、ウエハ状態のシリコン基
板２２の上面に接続パッド２３が形成され、その上面の
接続パッド２３の中央部を除く部分に絶縁膜２４が形成
され、絶縁膜２４に形成された開口部２５を介して露出
された接続パッド２３の上面から絶縁膜２４の上面にか
けて配線２６が形成され、配線２６の接続パッド部の上
面に柱状電極２７が形成されたものを用意する。Next, an example of a method of manufacturing the semiconductor device 21 shown in FIG. 1 will be described with reference to FIGS. First, as shown in FIG. 2, a connection pad 23 is formed on an upper surface of a silicon substrate 22 in a wafer state, and an insulating film 24 is formed on a portion of the upper surface except for a central portion of the connection pad 23. The wiring 26 is formed from the upper surface of the connection pad 23 exposed through the opened opening 25 to the upper surface of the insulating film 24, and a column electrode 27 is formed on the upper surface of the connection pad portion of the wiring 26.
【００１０】次に、図３に示すように、柱状電極２７を
除く絶縁膜２４の上面に、エポキシ樹脂２９ａ中にシリ
カ粒子２９ｂを比較的多く混入してなるものをディスペ
ンサ法やスピンコート法等によって塗布して硬化させる
ことにより、下側封止膜２９を形成する。次に、図４に
示すように、柱状電極２７を除く下側封止膜２９の上面
に、エポキシ樹脂３０ａ中にシリカ粒子３０ｂを比較的
少なく混入してなるものをディスペンサ法やスピンコー
ト法等によって塗布して硬化させることにより、中間封
止膜３０を形成する。次に、図５に示すように、柱状電
極２７を除く中間封止膜３０の上面に、エポキシ樹脂を
ディスペンサ法やスピンコート法等によって塗布して硬
化させることにより、上側封止膜３１を形成する。この
状態において、柱状電極２７の上面が上側封止膜３１に
よっ覆われた場合には、表面を軽く研磨することによ
り、柱状電極２７の上面を露出させる。次に、図６に示
すように、柱状電極２７の上面に半田バンプ３２を形成
する。次に、ダイシング工程を経ると、図１に示す半導
体装置２１が得られる。Next, as shown in FIG. 3, an epoxy resin 29a containing a relatively large amount of silica particles 29b is mixed on the upper surface of the insulating film 24 excluding the columnar electrode 27 by a dispenser method, a spin coating method, or the like. The lower sealing film 29 is formed by applying and hardening the film. Next, as shown in FIG. 4, an epoxy resin 30a containing a relatively small amount of silica particles 30b mixed on the upper surface of the lower sealing film 29 except for the columnar electrodes 27 is formed by a dispenser method, a spin coating method, or the like. Then, the intermediate sealing film 30 is formed by applying and curing. Next, as shown in FIG. 5, the upper sealing film 31 is formed by applying and curing an epoxy resin on the upper surface of the intermediate sealing film 30 except for the columnar electrodes 27 by a dispenser method, a spin coating method, or the like. I do. In this state, when the upper surface of the columnar electrode 27 is covered with the upper sealing film 31, the upper surface of the columnar electrode 27 is exposed by slightly polishing the surface. Next, as shown in FIG. 6, a solder bump 32 is formed on the upper surface of the columnar electrode 27. Next, after a dicing step, the semiconductor device 21 shown in FIG. 1 is obtained.
【００１１】なお、下側封止膜２９、中間封止膜３０及
び上側封止膜３１をそれぞれ塗布してから、これらを同
時に硬化させるようにしてもよい。また、上記第１実施
形態では、シリカ粒子２９ｂ、３０ｂの径を同じとした
場合について説明したが、これに限らず、シリカ粒子２
９ｂ、３０ｂの径を異ならせてもよい。この場合、シリ
カ粒子２９ｂの径をシリカ粒子３０ｂの径よりも大きく
しても小さくしてもよい。ただし、下側封止膜２９中に
おけるシリカ粒子２９ｂの体積比を中間封止膜３０中に
おけるシリカ粒子３０ｂの体積比よりも大きくする。さ
らに、上記第１実施形態では、封止膜２８を３層構造と
した場合について説明したが、それ以上の層構造として
もよい。The lower sealing film 29, the intermediate sealing film 30, and the upper sealing film 31 may be applied and then cured at the same time. In the first embodiment, the case where the diameters of the silica particles 29b and 30b are the same is described. However, the present invention is not limited to this.
The diameters of 9b and 30b may be different. In this case, the diameter of the silica particles 29b may be larger or smaller than the diameter of the silica particles 30b. However, the volume ratio of the silica particles 29b in the lower sealing film 29 is made larger than the volume ratio of the silica particles 30b in the intermediate sealing film 30. Further, in the first embodiment, the case where the sealing film 28 has a three-layer structure has been described. However, the sealing film 28 may have a three-layer structure.
【００１２】次に、図７はこの発明の第２実施形態にお
ける半導体装置の実装構造の要部の断面図を示したもの
である。この図において、図１と同一名称部分には同一
の符合を付し、その説明を適宜省略する。この第２実施
形態における封止膜２８は、エポキシ樹脂４１中に大中
小の径の異なる３種類のシリカ粒子４２、４３、４４が
混入されたものによって形成された単一の樹脂膜からな
っている。ただし、この場合の封止膜２８は、絶縁膜２
４側から順に、エポキシ樹脂４１中に主として大径のシ
リカ粒子４２が混入されたものからなる第１の封止層４
５と、エポキシ樹脂４１中に主として中径のシリカ粒子
４３が混入されたものからなる第２の封止層４６と、エ
ポキシ樹脂４１中に主として小径のシリカ粒子２８ｂが
混入されたものからなる第３の封止層４７と、エポキシ
樹脂４１中にシリカ粒子４２、４３、４４がほとんど含
まれない第４の封止層４８との４層構造となっていると
いうこともできる。すなわち、エポキシ樹脂４１中にお
けるシリカ粒子４２、４３、４４の体積比は、表面側か
ら絶縁膜２４側に向かうに従って漸次大きくなってい
る。FIG. 7 is a sectional view showing a main part of a semiconductor device mounting structure according to a second embodiment of the present invention. In this figure, the same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. The sealing film 28 in the second embodiment is a single resin film formed by mixing three types of silica particles 42, 43, and 44 having different diameters of large, medium, and small in an epoxy resin 41. I have. However, the sealing film 28 in this case is the insulating film 2
The first sealing layer 4 is mainly made of epoxy resin 41 mixed with large-diameter silica particles 42 in order from the side 4.
5, a second sealing layer 46 made of epoxy resin 41 mainly mixed with medium-diameter silica particles 43, and a second sealing layer 46 made of epoxy resin 41 mainly mixed with small-diameter silica particles 28b. It can be said that it has a four-layer structure of the third sealing layer 47 and the fourth sealing layer 48 in which the silica particles 42, 43 and 44 are hardly contained in the epoxy resin 41. That is, the volume ratio of the silica particles 42, 43, 44 in the epoxy resin 41 gradually increases from the surface side toward the insulating film 24 side.
【００１３】次に、この第２実施形態における半導体装
置２１の製造方法の一例について説明する。まず、例え
ば図２に示すものを用意する。次に、図示していない
が、柱状電極２７を除く絶縁膜２４の上面に、エポキシ
樹脂４１中に大中小の径の異なる３種類のシリカ粒子４
２、４３、４４を混入してなるものをディスペンサ法や
スピンコート法等によって塗布し、そのまま適当な時間
放置する。すると、３種類のシリカ粒子４２、４３、４
４は自重により径が大きいものほど深く沈み、エポキシ
樹脂４１中に主として大径のシリカ粒子４２が混入され
たものからなる第１の封止層４５と、エポキシ樹脂４１
中に主として中径のシリカ粒子４３が混入されたものか
らなる第２の封止層４６と、エポキシ樹脂４１中に主と
して小径のシリカ粒子４４が混入されたものからなる第
３の封止層４７と、エポキシ樹脂４１中にシリカ粒子４
２、４３、４４がほとんど含まれない第４の封止層４８
との４層が形成される。次に、エポキシ樹脂４１を硬化
させる。次に、柱状電極２７の上面に半田バンプ３２を
形成する。次に、ダイシング工程を経ると、図７に示す
半導体装置２１が得られる。Next, an example of a method of manufacturing the semiconductor device 21 according to the second embodiment will be described. First, for example, the one shown in FIG. 2 is prepared. Next, although not shown, on the upper surface of the insulating film 24 except for the columnar electrodes 27, three types of silica particles 4 having different sizes of large, medium, and small
The mixture obtained by mixing 2, 43, and 44 is applied by a dispenser method, a spin coating method, or the like, and left as it is for an appropriate time. Then, three types of silica particles 42, 43, 4
The first sealing layer 45, which sinks deeper as its diameter becomes larger due to its own weight, is mainly formed by mixing large-diameter silica particles 42 into the epoxy resin 41,
A second sealing layer 46 mainly including medium-diameter silica particles 43 mixed therein, and a third sealing layer 47 mainly including small-diameter silica particles 44 mixed into epoxy resin 41. And silica particles 4 in epoxy resin 41
Fourth sealing layer 48 that hardly contains 2, 43, and 44
Are formed. Next, the epoxy resin 41 is cured. Next, a solder bump 32 is formed on the upper surface of the columnar electrode 27. Next, after a dicing step, the semiconductor device 21 shown in FIG. 7 is obtained.
【００１４】次に、この第２実施形態における半導体装
置２１の製造方法の他の例について説明する。まず、例
えば図２に示すものを用意する。次に、図示していない
が、柱状電極２７を除く絶縁膜２４の上面に、エポキシ
樹脂４１中に大中小の径の異なる３種類のシリカ粒子４
２、４３、４４を混入してなるものをディスペンサ法や
スピンコート法等によって塗布する。次に、遠心力を作
用させることにより、塗布したエポキシ樹脂４１の表面
側に３種類のシリカ粒子２８ｂ、２８ｃ、２８ｄを集め
る。次に、適当な時間放置する。すると、３種類のシリ
カ粒子４２、４３、４４は自重により径が大きいものほ
ど深く沈み、エポキシ樹脂４１中に主として大径のシリ
カ粒子４２が混入されたものからなる第１の封止層４５
と、エポキシ樹脂４１中に主として中径のシリカ粒子４
３が混入されたものからなる第２の封止層４６と、エポ
キシ樹脂４１中に主として小径のシリカ粒子４４が混入
されたものからなる第３の封止層４７と、エポキシ樹脂
４１中にシリカ粒子４２、４３、４４がほとんど含まれ
ない第４の封止層４８との４層が形成される。次に、エ
ポキシ樹脂４１を硬化させる。次に、柱状電極２７の上
面に半田バンプ３２を形成する。次に、ダイシング工程
を経ると、図７に示す半導体装置２１が得られる。Next, another example of the method of manufacturing the semiconductor device 21 according to the second embodiment will be described. First, for example, the one shown in FIG. 2 is prepared. Next, although not shown, on the upper surface of the insulating film 24 except for the columnar electrodes 27, three types of silica particles 4 having different sizes of large, medium, and small
A mixture of 2, 43, and 44 is applied by a dispenser method, a spin coating method, or the like. Next, by applying a centrifugal force, three types of silica particles 28b, 28c, 28d are collected on the surface side of the applied epoxy resin 41. Next, it is left for an appropriate time. Then, the three types of silica particles 42, 43, 44 sink deeper as the diameter increases due to their own weight, and the first sealing layer 45, which is mainly composed of the epoxy resin 41 and the large-diameter silica particles 42 mixed therein.
And mainly silica particles 4 of medium diameter in epoxy resin 41.
3, a third sealing layer 47 mainly formed by mixing small-diameter silica particles 44 in the epoxy resin 41, and a second sealing layer 47 formed by mixing small silica particles 44 in the epoxy resin 41. Four layers including the fourth sealing layer 48 containing almost no particles 42, 43, and 44 are formed. Next, the epoxy resin 41 is cured. Next, a solder bump 32 is formed on the upper surface of the columnar electrode 27. Next, after a dicing step, the semiconductor device 21 shown in FIG. 7 is obtained.
【００１５】なお、上記第２実施形態では、径の異なる
３種類のシリカ粒子を用い、封止膜２８を４層構造とし
た場合について説明したが、これに限らず、径の異なる
４種類以上のシリカ粒子を用い、封止膜２８を５層以上
の構造としてもよい。また、上記各実施形態では、半田
バンプ３２を半導体装置２１の柱状電極２７上に形成し
た場合について説明したが、これに限らず、配線基板３
３の接続パッド３４上に形成するようにしてもよい。さ
らに、上記各製造方法では、ウエハ状態のシリコン基板
２１上に封止膜２８を形成し、ダイシングして個々のチ
ップに分断する場合について説明したが、これに限ら
ず、チップ状態のシリコン基板２１上に封止膜２８を形
成するようにしてもよい。この場合、封止材料がチップ
状態のシリコン基板２１上から流れ落ちないようにする
ために、例えば、チップ状態のシリコン基板２１上の周
囲にエポキシ樹脂等からなる枠状のものを貼り付けるよ
うにしてもよい。In the second embodiment, the case where the sealing film 28 has a four-layer structure using three types of silica particles having different diameters has been described. However, the present invention is not limited to this. And the sealing film 28 may have a structure of five or more layers. In each of the above embodiments, the case where the solder bump 32 is formed on the columnar electrode 27 of the semiconductor device 21 has been described.
3 may be formed on the third connection pad 34. Further, in each of the above-described manufacturing methods, the case where the sealing film 28 is formed on the silicon substrate 21 in a wafer state and the wafer is diced and divided into individual chips has been described. A sealing film 28 may be formed thereon. In this case, in order to prevent the sealing material from flowing down on the silicon substrate 21 in a chip state, for example, a frame-like material made of epoxy resin or the like is attached around the silicon substrate 21 in a chip state. Is also good.
【００１６】[0016]
【発明の効果】以上説明したように、この発明によれ
ば、封止膜の熱膨張係数等の特性をその厚さ方向で異な
らせ、封止膜の絶縁膜側の熱膨張係数等の特性を半導体
基板の熱膨張係数等の特性に近づけているので、半導体
基板と封止膜との熱膨張係数差等の特性差に起因する応
力を小さくすることができ、したがって温度変化が生じ
ても、半導体基板と配線基板との接合部分にクラックが
発生することがなく、接合の信頼性を高めることができ
る。As described above, according to the present invention, the characteristics such as the coefficient of thermal expansion of the sealing film are varied in the thickness direction, and the characteristics such as the coefficient of thermal expansion of the sealing film on the insulating film side are changed. Is closer to the characteristics of the semiconductor substrate such as the coefficient of thermal expansion, so that the stress caused by the difference in the characteristics of the semiconductor substrate and the sealing film such as the difference in the coefficient of thermal expansion can be reduced. Thus, cracks do not occur at the joint between the semiconductor substrate and the wiring board, and the reliability of the joint can be improved.
【図１】この発明の第１実施形態における半導体装置の
実装構造の断面図。FIG. 1 is a sectional view of a mounting structure of a semiconductor device according to a first embodiment of the present invention.
【図２】図１に示す半導体装置の製造に際し、当初用意
したものの一部の断面図。FIG. 2 is a cross-sectional view of a part of a device initially prepared for manufacturing the semiconductor device shown in FIG. 1;
【図３】図２に続く製造工程の断面図。FIG. 3 is a sectional view of the manufacturing process following FIG. 2;
【図４】図３に続く製造工程の断面図。FIG. 4 is a sectional view of the manufacturing process following FIG. 3;
【図５】図４に続く製造工程の断面図。FIG. 5 is a sectional view of the manufacturing process following FIG. 4;
【図６】図５に続く製造工程の断面図。FIG. 6 is a sectional view of the manufacturing process following FIG. 5;
【図７】この発明の第２実施形態における半導体装置の
実装構造の要部の断面図。FIG. 7 is a sectional view of a main part of a mounting structure of a semiconductor device according to a second embodiment of the present invention.
【図８】従来の半導体装置の実装構造の一例の断面図。FIG. 8 is a cross-sectional view of an example of a conventional semiconductor device mounting structure.
２１ 半導体装置 ２２ シリコン基板 ２３ 接続パッド ２４ 絶縁膜 ２５ 開口部 ２６ 配線 ２７ 柱状電極 ２８ 封止膜 ２９ 下側封止膜 ２９ａ エポキシ樹脂 ２９ｂ シリカ粒子 ３０ 中間封止膜 ３０ａ エポキシ樹脂 ３０ｂ シリカ粒子 ３１ 上側封止膜 ３２ 半田バンプ ３３ 配線基板 ３４ 接続パッド DESCRIPTION OF SYMBOLS 21 Semiconductor device 22 Silicon substrate 23 Connection pad 24 Insulating film 25 Opening 26 Wiring 27 Columnar electrode 28 Sealing film 29 Lower sealing film 29a Epoxy resin 29b Silica particles 30 Intermediate sealing film 30a Epoxy resin 30b Silica particles 31 Upper sealing Stop film 32 Solder bump 33 Wiring board 34 Connection pad
フロントページの続き (56)参考文献 特開 平３−224245（ＪＰ，Ａ) 特開 平10−340978（ＪＰ，Ａ) 特開 平11−87424（ＪＰ，Ａ) 特開 平11−121538（ＪＰ，Ａ) 特開 平３−296250（ＪＰ，Ａ) 特開 昭64−37075（ＪＰ，Ａ) 実開 昭64−13730（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/28 - 23/31 H01L 21/60 311 H01L 23/12 501 Continuation of front page (56) References JP-A-3-224245 (JP, A) JP-A-10-340978 (JP, A) JP-A-11-87424 (JP, A) JP-A-11-121538 (JP, A) , A) JP-A-3-296250 (JP, A) JP-A-64-37075 (JP, A) JP-A-64-13730 (JP, U) (58) Fields investigated (Int. Cl. 7 , DB Name) H01L 23/28-23/31 H01L 21/60 311 H01L 23/12 501
Claims (10)
された開口部を介して接続パッドが露出され、前記接続
パッド上から前記絶縁膜上にかけて接続パッド部を有す
る配線が形成され、前記配線の接続パッド部上に電極が
形成され、前記電極を除く前記絶縁膜上に封止膜が形成
された半導体装置において、前記封止膜の特性がその厚
さ方向で異なり、該封止膜の前記絶縁膜側の特性が前記
半導体基板の特性に近くなっていることを特徴とする半
導体装置。A connection pad is exposed through an opening formed in an insulating film formed on a semiconductor substrate, and a wiring having a connection pad portion is formed from above the connection pad to above the insulating film; In a semiconductor device in which an electrode is formed on a connection pad portion of a wiring and a sealing film is formed on the insulating film excluding the electrode, the characteristics of the sealing film differ in the thickness direction, and the sealing film Wherein the characteristic on the insulating film side is close to the characteristic of the semiconductor substrate.
は熱膨張係数であることを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein said characteristic is a coefficient of thermal expansion.
膜は、少なくとも、樹脂中に熱膨張係数低下用粒子が混
入されたものからなり、熱膨張係数を前記半導体基板の
熱膨張係数に近い値とされた下側封止膜と、樹脂中に熱
膨張係数低下用粒子が混入されたものからなり、熱膨張
係数を樹脂の熱膨張係数よりも小さく且つ前記下側封止
膜の熱膨張係数よりも大きい値とされた中間封止膜と、
樹脂のみからなる上側封止膜とを有することを特徴とす
る半導体装置。3. The invention according to claim 2, wherein the sealing film is made of at least a resin in which particles for lowering the coefficient of thermal expansion are mixed in a resin. The lower sealing film having a value close to that of the lower sealing film is made of resin in which particles for lowering the coefficient of thermal expansion are mixed into the resin. An intermediate sealing film having a value larger than the expansion coefficient,
A semiconductor device having an upper sealing film made of only a resin.
膜は、径の異なる複数種類の熱膨張係数低下用粒子が混
入された単一の樹脂膜からなっているとともに、その熱
膨張係数が表面側から前記絶縁膜側に向かうに従って漸
次小さくなっていることを特徴とする半導体装置。4. The invention according to claim 2, wherein the sealing film is formed of a single resin film into which a plurality of types of particles having different diameters for lowering the coefficient of thermal expansion are mixed, and the coefficient of thermal expansion of the resin film is increased. Is gradually reduced from the surface side toward the insulating film side.
膜は、径の異なる複数種類の熱膨張係数低下用粒子が混
入された単一の樹脂膜からなっているとともに、この樹
脂膜中における前記熱膨張係数低下用粒子の体積比が表
面側から前記絶縁膜側に向かうに従って漸次大きくなっ
ていることを特徴とする半導体装置。5. The invention according to claim 2, wherein the sealing film is made of a single resin film mixed with plural kinds of particles having different diameters for lowering a thermal expansion coefficient, and the sealing film is formed of a single resin film. Wherein the volume ratio of the particles for lowering the coefficient of thermal expansion in (1) gradually increases from the surface side toward the insulating film side.
おいて、前記熱膨張係数低下用粒子はシリカ粒子である
ことを特徴とする半導体装置。6. The semiconductor device according to claim 3, wherein the particles for lowering the coefficient of thermal expansion are silica particles.
された開口部を介して接続パッドが露出され、前記接続
パッド上から前記絶縁膜上にかけて接続パッド部を有す
る配線が形成され、前記配線の接続パッド部上に電極が
形成され、前記電極を除く前記絶縁膜上に封止膜が形成
された半導体装置の製造に際し、前記電極を除く前記絶
縁膜上に、少なくとも、樹脂中に熱膨張係数低下用粒子
が混入されたものからなり、熱膨張係数を前記半導体基
板の熱膨張係数に近い値とされた下側封止膜と、樹脂中
に熱膨張係数低下用粒子が混入されたものからなり、熱
膨張係数を樹脂の熱膨張係数よりも小さく且つ前記下側
封止膜の熱膨張係数よりも大きい値とされた中間封止膜
と、樹脂のみからなる上側封止膜とを形成して、これら
の封止膜により前記封止膜を形成することを特徴とする
半導体装置の製造方法。7. A connection pad is exposed through an opening formed in an insulating film formed on a semiconductor substrate, and a wiring having a connection pad portion is formed from above the connection pad to above the insulating film; In manufacturing a semiconductor device in which an electrode is formed on a connection pad portion of a wiring and a sealing film is formed on the insulating film except for the electrode, at least heat is applied to the resin on the insulating film except for the electrode. The lower sealing film having a coefficient of thermal expansion set to a value close to the coefficient of thermal expansion of the semiconductor substrate, and the particles for lowering the coefficient of thermal expansion were mixed in the resin. An intermediate sealing film having a coefficient of thermal expansion smaller than the coefficient of thermal expansion of the resin and larger than the coefficient of thermal expansion of the lower sealing film, and an upper sealing film made of only the resin. And forming these sealing films A method for manufacturing a semiconductor device, comprising forming a sealing film.
された開口部を介して接続パッドが露出され、前記接続
パッド上から前記絶縁膜上にかけて接続パッド部を有す
る配線が形成され、前記配線の接続パッド部上に電極が
形成され、前記電極を除く前記絶縁膜上に封止膜が形成
された半導体装置の製造に際し、前記電極を除く前記絶
縁膜上に、径の異なる複数種類の熱膨張係数低下用粒子
が混入された単一の樹脂膜を形成し、次いでこの熱膨張
係数低下用粒子の混入された樹脂膜の熱膨張係数を表面
側から前記絶縁膜側に向かうに従って漸次小さくなるよ
うにし、これにより前記封止膜を形成することを特徴と
する半導体装置の製造方法。8. A connection pad is exposed through an opening formed in an insulating film formed on a semiconductor substrate, and a wiring having a connection pad portion is formed from above the connection pad to above the insulating film. In manufacturing a semiconductor device in which an electrode is formed on a connection pad portion of a wiring and a sealing film is formed on the insulating film except for the electrode, a plurality of types having different diameters are formed on the insulating film except for the electrode. Form a single resin film in which the particles for lowering the thermal expansion coefficient are mixed, and then gradually decrease the thermal expansion coefficient of the resin film in which the particles for lowering the thermal expansion coefficient are mixed from the surface side toward the insulating film side. A method for manufacturing a semiconductor device, wherein the sealing film is formed.
された開口部を介して接続パッドが露出され、前記接続
パッド上から前記絶縁膜上にかけて接続パッド部を有す
る配線が形成され、前記配線の接続パッド部上に電極が
形成され、前記電極を除く前記絶縁膜上に封止膜が形成
された半導体装置の製造に際し、前記電極を除く前記絶
縁膜上に、径の異なる複数種類の熱膨張係数低下用粒子
が混入された単一の樹脂膜を形成し、次いでこの樹脂膜
中における前記熱膨張係数低下用粒子の体積比を表面側
から前記絶縁膜側に向かうに従って漸次大きくなるよう
にし、これにより前記封止膜を形成することを特徴とす
る半導体装置の製造方法。9. A connection pad is exposed through an opening formed in an insulating film formed on a semiconductor substrate, and a wiring having a connection pad portion is formed from above the connection pad to above the insulating film. In manufacturing a semiconductor device in which an electrode is formed on a connection pad portion of a wiring and a sealing film is formed on the insulating film except for the electrode, a plurality of types having different diameters are formed on the insulating film except for the electrode. A single resin film mixed with the particles for lowering the coefficient of thermal expansion is formed, and the volume ratio of the particles for lowering the coefficient of thermal expansion in the resin film gradually increases from the surface toward the insulating film. And forming the sealing film by using the method.
において、前記熱膨張係数低下用粒子はシリカ粒子であ
ることを特徴とする半導体装置の製造方法。10. The method of manufacturing a semiconductor device according to claim 7, wherein the particles for lowering the coefficient of thermal expansion are silica particles.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19812798A JP3287310B2 (en) | 1998-06-30 | 1998-06-30 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19812798A JP3287310B2 (en) | 1998-06-30 | 1998-06-30 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000022052A JP2000022052A (en) | 2000-01-21 |
| JP3287310B2 true JP3287310B2 (en) | 2002-06-04 |
Family
ID=16385908
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19812798A Expired - Fee Related JP3287310B2 (en) | 1998-06-30 | 1998-06-30 | Semiconductor device and manufacturing method thereof |
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| Country | Link |
|---|---|
| JP (1) | JP3287310B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10014609B2 (en) | 2016-11-28 | 2018-07-03 | Molex, Llc | Connector |
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|---|---|---|---|---|
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| JP2008091530A (en) * | 2006-09-29 | 2008-04-17 | Oki Electric Ind Co Ltd | Semiconductor device |
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| JP5003741B2 (en) * | 2009-10-05 | 2012-08-15 | イビデン株式会社 | Semiconductor chip |
| JP5585133B2 (en) * | 2010-03-15 | 2014-09-10 | 富士電機株式会社 | Semiconductor device and method for manufacturing semiconductor device |
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| JP6788344B2 (en) * | 2015-12-21 | 2020-11-25 | 京セラ株式会社 | Electronic components and manufacturing methods for electronic components |
| JP2017157767A (en) * | 2016-03-04 | 2017-09-07 | パナソニックＩｐマネジメント株式会社 | Chip resistor |
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1998
- 1998-06-30 JP JP19812798A patent/JP3287310B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10014609B2 (en) | 2016-11-28 | 2018-07-03 | Molex, Llc | Connector |
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|---|---|
| JP2000022052A (en) | 2000-01-21 |
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