JP2000164617A - Chip-sized package and its manufacture - Google Patents
Chip-sized package and its manufactureInfo
- Publication number
- JP2000164617A JP2000164617A JP10334175A JP33417598A JP2000164617A JP 2000164617 A JP2000164617 A JP 2000164617A JP 10334175 A JP10334175 A JP 10334175A JP 33417598 A JP33417598 A JP 33417598A JP 2000164617 A JP2000164617 A JP 2000164617A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- layer
- forming
- opening
- metal post
- Prior art date
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05557—Shape in side view comprising protrusions or indentations
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、チップサイズパッ
ケージとその製造方法に関する。チップサイズパッケー
ジ（Chip Size Package）は、ＣＳＰとも呼ばれ、チッ
プサイズと同等か、わずかに大きいパッケージの総称で
あり、高密度実装を目的としたパッケージである。本発
明は、ＣＳＰに採用されるメタルポストと半田バンプと
の密着性を高めて、チップサイズパッケージの信頼性を
向上させる技術に関する。The present invention relates to a chip size package and a method for manufacturing the same. The chip size package (Chip Size Package) is also referred to as a CSP, and is a general term for packages having a size equal to or slightly larger than the chip size, and is a package for high-density mounting. The present invention relates to a technique for improving the adhesion between a metal post and a solder bump used in a CSP to improve the reliability of a chip size package.
【０００２】[0002]
【従来の技術】従来、この分野では、一般にＢＧＡ（Ba
ll Grid Array）と呼ばれ、面状に配列された複数のハ
ンダボールを持つ構造、ファインピッチＢＧＡと呼ば
れ、ＢＧＡのボールピッチをさらに狭ピッチにして外形
がチップサイズに近くなった構造等が知られている。2. Description of the Related Art Conventionally, in this field, BGA (Ba
ll Grid Array), a structure with a plurality of solder balls arranged in a plane, a fine pitch BGA, a structure in which the ball pitch of the BGA is further narrowed and the outer shape is close to the chip size, etc. Are known.
【０００３】また、最近では、「日経マイクロデバイ
ス」１９９８年８月号，第４４頁〜第７１頁に記載され
たウエハーＣＳＰがある。このウエハーＣＳＰは、基本
的には、チップのダイシング前に配線やアレイ状のパッ
ドをウエハープロセス（前工程）で作り込むＣＳＰであ
る。この技術によって、ウエハープロセスとパッケージ
・プロセス（後工程）が一体化され、パッケージ・コス
トが大幅に低減できるようになることが期待されてい
る。Further, recently, there is a wafer CSP described in “Nikkei Microdevice”, August 1998, pp. 44-71. This wafer CSP is basically a CSP in which wiring or array-like pads are formed by a wafer process (pre-process) before dicing a chip. It is expected that this technology will integrate the wafer process and the package process (post-process), thereby greatly reducing the package cost.
【０００４】ウエハーＣＳＰの種類には、封止樹脂型と
再配線型がある。封止樹脂型は、従来のパッケージと同
様に表面を封止樹脂で覆った構造であり、チップ表面の
配線層上にメタルポストを形成し、その周囲を封止樹脂
で固める構造である。There are two types of wafer CSP: a sealing resin type and a rewiring type. The sealing resin mold has a structure in which the surface is covered with a sealing resin, similarly to a conventional package, and has a structure in which metal posts are formed on a wiring layer on the chip surface and the periphery thereof is solidified with the sealing resin.
【０００５】一般にパッケージをプリント基板に搭載す
ると、プリント基板との熱膨張差によって発生した応力
がメタルポストに集中すると言われているが、樹脂封止
型では、メタルポストが長くなるため、応力が分散され
ると考えられている。It is generally said that when a package is mounted on a printed circuit board, stress generated due to a difference in thermal expansion between the printed circuit board and the printed circuit board is concentrated on the metal posts. It is believed to be decentralized.
【０００６】一方、再配線型は、図５に示すように、封
止樹脂を使わず、再配線を形成した構造である。つまり
チップ５１の表面にＡｌ電極５２、配線層５３、絶縁層
５４が積層され、配線層５３上にはメタルポスト５５が
形成され、その上に半田バンプ５６が形成されている。
配線層５３は、半田バンプ５６をチップ上に所定のアレ
イ状に配置するための再配線として用いられる。On the other hand, the rewiring type has a structure in which a rewiring is formed without using a sealing resin as shown in FIG. That is, an Al electrode 52, a wiring layer 53, and an insulating layer 54 are stacked on the surface of the chip 51, a metal post 55 is formed on the wiring layer 53, and a solder bump 56 is formed thereon.
The wiring layer 53 is used as rewiring for arranging the solder bumps 56 on the chip in a predetermined array.
【０００７】封止樹脂型は、メタルポストを１００μｍ
程度と長くし、これを封止樹脂で補強することにより、
高い信頼性が得られる。しかしながら、１００μｍ程度
のメタルポストを形成するにはホトレジスト層の露光限
界が２０〜３０μｍ程度であるため、複数回の露光作業
が必要となり生産性が悪く、また、封止樹脂を形成する
プロセスは、後工程において金型を用いて実施する必要
があり、プロセスが複雑になる。[0007] The sealing resin mold has a metal post of 100 μm.
By lengthening it and reinforcing it with sealing resin,
High reliability is obtained. However, since the exposure limit of the photoresist layer is about 20 to 30 μm in order to form a metal post of about 100 μm, a plurality of exposure operations are required and productivity is poor, and the process of forming a sealing resin is It is necessary to carry out using a mold in a post-process, and the process becomes complicated.
【０００８】一方、再配線型では、プロセスは比較的単
純であり、しかも殆どの工程をウエハープロセスで実施
できる利点がある。しかし、なんらかの方法で実装基板
からの応力を緩和し信頼性を高めることが必要とされて
いる。On the other hand, the rewiring type has an advantage that the process is relatively simple and most of the steps can be performed by a wafer process. However, it is necessary to relieve the stress from the mounting board by some method to increase the reliability.
【０００９】[0009]
【発明が解決しようとする課題】しかし、半田バンプ５
６は、溶融時の表面張力により球体に成り、ネック（メ
タルポストとの半田融着部が細くなる部分）が形成され
るため、図６に示すように実装基板６１の被着面６２と
の実装時に、ここに応力が加わり半田クラックが発生す
る問題があった。However, the solder bumps 5
6 is formed into a sphere due to the surface tension at the time of melting, and a neck (a portion where the solder fusion portion with the metal post is narrowed) is formed. Therefore, as shown in FIG. At the time of mounting, there is a problem that a stress is applied here and a solder crack occurs.
【００１０】また、メタルポスト径が微細化されるに従
って、メタルポストと半田バンプとの密着強度が低下し
て信頼性が低下することになる。[0010] Further, as the diameter of the metal post is reduced, the adhesion strength between the metal post and the solder bump is reduced, and the reliability is reduced.
【００１１】[0011]
【課題を解決するための手段】本発明のチップサイズパ
ッケージとその製造方法は上記の課題に鑑みてなされ、
メタルポスト７の上面部に凸部９が形成されていること
で、半田バンプとの密着表面積が増大し、信頼性が向上
する。SUMMARY OF THE INVENTION A chip size package and a method of manufacturing the same according to the present invention have been made in view of the above problems, and
The formation of the protrusions 9 on the upper surface of the metal post 7 increases the surface area in contact with the solder bumps, thereby improving reliability.
【００１２】そして、そのようなメタルポスト７の形成
は、先ず、通常のメタルポストの形成工程と同様にし
て、Ａｌ電極１あるいはＡｌ電極１に接続された配線層
１０を被覆するように開口部４を有するパッシベーショ
ン膜３あるいはポリイミド層１２を形成した後、この開
口部４内にメタルポスト用の第１の金属層７Ａを形成す
る。そして、前記第１の金属層７Ａ上に少なくともその
上面部よりも小さい開口部１２Ｂを有するポリイミド層
１２Ａを形成し、この開口部１２Ｂ内にメタルポスト用
の第２の金属層７Ｂを形成した後に、前記ポリイミド層
１２Ａを除去して前記第１の金属層７Ａと第２の金属層
７Ｂから成るメタルポスト７を形成するものである。The formation of such a metal post 7 is performed in the same manner as in a normal metal post formation process, so that an opening is formed so as to cover the Al electrode 1 or the wiring layer 10 connected to the Al electrode 1. After forming the passivation film 3 or the polyimide layer 12 having the metal layer 4, a first metal layer 7A for a metal post is formed in the opening 4. Then, a polyimide layer 12A having an opening 12B smaller than at least the upper surface thereof is formed on the first metal layer 7A, and a second metal layer 7B for a metal post is formed in the opening 12B. And removing the polyimide layer 12A to form a metal post 7 including the first metal layer 7A and the second metal layer 7B.
【００１３】[0013]
【発明の実施の形態】以下、本発明の実施形態について
説明する。図１は、ＩＣチップの表面に形成されたＡｌ
電極の真上に半田バンプを形成したものであり、図２
は、配線層を延在させ、この上に形成したものである。Embodiments of the present invention will be described below. FIG. 1 shows an example of Al formed on the surface of an IC chip.
FIG. 2 is a view in which solder bumps are formed just above the electrodes.
In this example, a wiring layer is extended and formed thereon.
【００１４】先ず、前者の第１の実施形態について説明
する。First, the former first embodiment will be described.
【００１５】半導体ＩＣは、素子数の増加に伴い、１層
メタル、２層メタル、３層メタル…等が採用され、最上
層のメタルの上には、Ｓｉ窒化膜やＰＩＸ等のパッシベ
ーション膜が被覆されている。As the number of elements of the semiconductor IC increases, a one-layer metal, a two-layer metal, a three-layer metal, etc. are adopted, and a passivation film such as a Si nitride film or PIX is formed on the uppermost metal. Coated.
【００１６】図１では、前記最上層のメタル（金属電極
パッド、以下Ａｌ電極と呼ぶ。）を図番１で示し、この
Ａｌ電極１のコンタクトホールが形成される層間絶縁膜
を図番２で示す。更には、パッシベーション膜を図番３
で示す。ここでパッシベーション膜３は、Ｓｉ窒化膜、
エポキシ樹脂またはＰＩＸ等である。In FIG. 1, the metal of the uppermost layer (metal electrode pad, hereinafter referred to as Al electrode) is shown in FIG. 1, and the interlayer insulating film in which the contact hole of this Al electrode 1 is formed is shown in FIG. Show. Furthermore, the passivation film is
Indicated by Here, the passivation film 3 is a Si nitride film,
Epoxy resin or PIX.
【００１７】続いて、このパッシベーション膜３には、
Ａｌ電極１を露出する開口部４が形成され、ここには、
バリアメタルとして、下からＴｉ，ＴｉＮやＣｒ等から
成る後述するＣｕ層用のバリア層５、Ｃｕ層６が形成さ
れている。このバリアメタル５、６は、開口部の中およ
びその周辺に延在されるようにパターニングされてい
る。Subsequently, the passivation film 3 has
An opening 4 exposing the Al electrode 1 is formed.
As a barrier metal, a barrier layer 5 and a Cu layer 6 for a Cu layer, which will be described later, made of Ti, TiN, Cr or the like are formed from below. The barrier metals 5 and 6 are patterned so as to extend into and around the opening.
【００１８】更には、このバリアメタルの上には、メタ
ルポスト７が形成されている。このメタルポスト７は、
例えば半田バンプ８と親和性の良いＣｕやＡｕ等から成
り、下地のＣｕに例えば電解メッキにより形成される。
しかし、蒸着、スパッタリング等で形成されても良い。Further, a metal post 7 is formed on the barrier metal. This metal post 7
For example, it is made of Cu, Au, or the like that has a good affinity for the solder bump 8, and is formed on the underlying Cu by, for example, electrolytic plating.
However, it may be formed by vapor deposition, sputtering or the like.
【００１９】そして半田バンプ８が形成されている。こ
こで半田バンプ８は、下地のＣｕに電解メッキにより形
成される。尚、前記半田バンプ８の形成は、電解メッキ
法に限らず、印刷法でもボンダー等を用いた形成法であ
っても良い。Then, solder bumps 8 are formed. Here, the solder bumps 8 are formed on the underlying Cu by electrolytic plating. The formation of the solder bumps 8 is not limited to the electrolytic plating method, but may be a printing method or a forming method using a bonder or the like.
【００２０】本発明の特徴は、前記メタルポスト７の形
状にある。すなわち、図１に示すようにメタルポスト７
の上面部に凸部９が形成されていることで、半田バンプ
８との密着表面積が増大することになり、密着強度が増
大し、信頼性が向上するものである。The feature of the present invention lies in the shape of the metal post 7. That is, as shown in FIG.
By forming the projections 9 on the upper surface of the solder bumps 8, the surface area of the contact with the solder bumps 8 is increased, the adhesion strength is increased, and the reliability is improved.
【００２１】続いて、第２の実施形態について図２を参
照しながら説明する。本実施形態は、図５のような配線
層５３を採用したものである。Next, a second embodiment will be described with reference to FIG. This embodiment employs a wiring layer 53 as shown in FIG.
【００２２】図２に於いても、最上層のメタル（Ａｌ電
極）を図番１で示し、このＡｌ電極１のコンタクトホー
ルが形成される層間絶縁膜を図番２で示す。更には、パ
ッシベーション膜を図番３で示す。ここでパッシベーシ
ョン膜３は、Ｓｉ窒化膜、エポキシ樹脂またはＰＩＸ等
である。Also in FIG. 2, the metal (Al electrode) in the uppermost layer is shown in FIG. 1, and the interlayer insulating film in which the contact hole of this Al electrode 1 is formed is shown in FIG. Further, the passivation film is shown in FIG. Here, the passivation film 3 is a Si nitride film, an epoxy resin, PIX, or the like.
【００２３】続いて、このパッシベーション膜３は、Ａ
ｌ電極１を露出する開口部１３が形成され、ここには、
バリアメタルとして、Ｃｒ、Ｔｉ、ＴｉＮ等から選択さ
れて形成される。このバリアメタル１１は、開口部１３
の中およびその周辺だけに形成されても良い。そして、
この上には、配線層１０が形成される。ここでは、バリ
アメタル１１をメッキ電極として活用し、Ｃｕが形成さ
れている。Subsequently, the passivation film 3
An opening 13 exposing the electrode 1 is formed.
The barrier metal is formed by being selected from Cr, Ti, TiN and the like. The barrier metal 11 has an opening 13
May be formed only in and around. And
On this, the wiring layer 10 is formed. Here, Cu is formed using the barrier metal 11 as a plating electrode.
【００２４】続いて、絶縁樹脂から成る樹脂層（例え
ば、ポリイミド層１２）等が形成され、配線層１０の端
部に開口部４が形成され、この開口部４に、下からＴ
ｉ，ＴｉＮやＣｒ等から成る後述するＣｕ層用のバリア
層５、Ｃｕ層６が形成されている。このバリアメタル
５、６は、開口部の中およびその周辺に延在されるよう
にパターニングされている。Subsequently, a resin layer (for example, a polyimide layer 12) made of an insulating resin and the like are formed, an opening 4 is formed at an end of the wiring layer 10, and a T
A barrier layer 5 and a Cu layer 6 for a Cu layer, which will be described later, are formed of i, TiN, Cr, or the like. The barrier metals 5 and 6 are patterned so as to extend into and around the opening.
【００２５】また、このバリアメタル５、６の上には、
メタルポスト７が形成されている。このメタルポスト７
は、例えば半田バンプ８と親和性の良いＣｕ等から成
り、例えば電解メッキで形成される。しかし蒸着、スパ
ッタリング等で形成されても良い。On the barrier metals 5 and 6,
Metal posts 7 are formed. This metal post 7
Is made of, for example, Cu having a good affinity for the solder bump 8, and is formed by, for example, electrolytic plating. However, it may be formed by vapor deposition, sputtering or the like.
【００２６】そして半田バンプ８が形成される。ここで
半田バンプ８は、下地のＣｕに電解メッキにより形成さ
れる。尚、印刷法でもボンダーを用いた形成法であって
も良い。Then, solder bumps 8 are formed. Here, the solder bumps 8 are formed on the underlying Cu by electrolytic plating. Note that a printing method or a forming method using a bonder may be used.
【００２７】本発明の特徴は、前記メタルポスト７の形
状にある。すなわち、図２に示すようにメタルポスト７
の上面部に凸部９が形成されていることで、半田バンプ
８との密着表面積が増大することになり、密着強度が増
大し、信頼性が向上するものである。A feature of the present invention lies in the shape of the metal post 7. That is, as shown in FIG.
By forming the projections 9 on the upper surface of the solder bumps 8, the surface area of the contact with the solder bumps 8 is increased, the adhesion strength is increased, and the reliability is improved.
【００２８】図３は本発明のＣＳＰと実装基板との実装
状態を示した図（本発明の効果が顕著に表れるように、
両者の実装位置がずれて、実装条件が厳しい状態を示し
てある。）であり、半田バンプ８と実装基板６１の被着
面６２との実装時に、従来のように実装ストレスにより
応力が加わり半田クラックが発生しそうになった（ある
いは発生した）としても、前記凸部９の存在により、こ
の凸部９で半田クラックが止まることになる。FIG. 3 is a view showing a mounting state of the CSP of the present invention and a mounting board (to make the effect of the present invention remarkable,
The two mounting positions are shifted from each other, and the mounting conditions are severe. When the solder bumps 8 are mounted on the adhered surface 62 of the mounting board 61, soldering cracks are likely to occur due to mounting stress as in the related art (or, if the solder bumps 8 are likely to occur). Due to the presence of 9, the solder crack stops at the convex portion 9.
【００２９】尚、メタルポスト７と半田バンプ８との密
着表面積を増大させるという目的をかなえるのであれ
ば、第１，第２の実施形態で説明した凸部９に代えて、
メタルポストの上面部に凹部を設ける方法もあるが、こ
の場合には、前述した図３に示したような実装状態にお
いて、凸部９ほど密着強度が高くならず、半田バンプ８
がそっくり抜けてしまうおそれがある。もし、凹部でも
って、密着強度を高めたいとした場合には、その凹部の
断面形状を矩形状にするよりも、開口部の上面に向かう
に従って開口径が狭くなった形状にするほど密着強度の
高いものが得られる。If the purpose of increasing the contact surface area between the metal post 7 and the solder bump 8 can be achieved, instead of the protrusion 9 described in the first and second embodiments,
Although there is a method of providing a concave portion on the upper surface of the metal post, in this case, in the mounting state as shown in FIG.
May be completely removed. If it is desired to increase the adhesive strength with the concave portion, rather than making the cross-sectional shape of the concave portion rectangular, the adhesive strength of the concave portion becomes smaller as the opening diameter decreases toward the upper surface of the opening. Higher ones are obtained.
【００３０】更に言えば、密着強度の高まる凸部９の形
状は、種々の形状のものが考えられるが、例えば、凸部
９を上から観た状態で説明すれば、第１，第２の実施形
態のようにはメタルポスト７の中央部に形成される構成
であっても良く、上面部の複数箇所に形成されていても
良く、その凸部９の上面部の形状が円形でも良く、ま
た、三角形や四角形や十字形…等の角部があった方が半
田バンプ８との密着性が良くなると考えられる。尚、凸
部９と凹部とを併せ持った構造のメタルポストを採用し
ても良い。More specifically, various shapes can be considered for the shape of the convex portion 9 where the adhesion strength is increased. For example, if the convex portion 9 is viewed from above, the first and second convex portions 9 will be described. As in the embodiment, the metal post 7 may be formed at the center portion, the metal post 7 may be formed at a plurality of positions on the upper surface portion, and the shape of the upper surface portion of the convex portion 9 may be circular. Further, it is considered that the corners such as a triangle, a quadrangle, a cross, and the like have better adhesion to the solder bumps 8. Incidentally, a metal post having a structure having both the convex portion 9 and the concave portion may be adopted.
【００３１】また、今後、メタルポスト径が微細化され
るに従って、メタルポストと半田バンプとの密着強度の
低下が予想されるが、本発明を採用することで密着強度
の低下を抑えられる。In the future, as the diameter of the metal posts becomes finer, it is expected that the adhesion strength between the metal posts and the solder bumps will decrease. However, by employing the present invention, the decrease in the adhesion strength can be suppressed.
【００３２】続いて、本発明のＣＳＰ構造の一般的な製
造方法について簡単に説明する。尚、前述した第１，第
２の実施形態の構造は、実質的にＡｌ電極１上にメタル
ポスト７を形成するか、Ａｌ電極１上に接続された配線
層１０を介してメタルポスト７を形成するかの違いであ
るため、図２に示す第２の実施形態のＣＳＰ構造におけ
るその製造方法についてのみ説明するが、前記メタルポ
スト７の形成は、本発明の特徴を為す工程であるため、
図４を参照しながら説明する。Next, a general method of manufacturing the CSP structure according to the present invention will be briefly described. In the structure of the first and second embodiments described above, the metal post 7 is substantially formed on the Al electrode 1 or the metal post 7 is formed via the wiring layer 10 connected on the Al electrode 1. Only the method of manufacturing the CSP structure according to the second embodiment shown in FIG. 2 will be described because of the difference in the formation of the metal post 7. However, since the formation of the metal post 7 is a process that is a feature of the present invention,
This will be described with reference to FIG.
【００３３】先ず、Ａｌ電極１を有するＬＳＩが形成さ
れた半導体基板（ウエハー）を準備し、半導体基板の表
面をＳｉＮ膜、ＰＩＸなどのパッシベーション膜３で被
覆する。First, a semiconductor substrate (wafer) on which an LSI having an Al electrode 1 is formed is prepared, and the surface of the semiconductor substrate is covered with a passivation film 3 such as a SiN film or PIX.
【００３４】Ａｌ電極１はＬＳＩの外部接続用のパッド
である。その表面のパッシベーション膜３をエッチング
によって取り除き、全面にバリアメタル１１を形成す
る。バリアメタル１１は、後に形成する配線層１０とＡ
ｌ電極１との間に介在してＡｌ電極１を保護するバリア
であり、Ｃｒ、Ｔｉ、ＴｉＮなどをスパッタして形成す
る。The Al electrode 1 is a pad for external connection of the LSI. The passivation film 3 on the surface is removed by etching, and a barrier metal 11 is formed on the entire surface. The barrier metal 11 is formed between the wiring layer 10 to be formed later and A
A barrier interposed between the electrode 1 and the Al electrode 1 to protect the Al electrode 1, and is formed by sputtering Cr, Ti, TiN, or the like.
【００３５】次に、Ａｌ電極１に接続する配線層１０を
形成する。この配線層１０は機械的強度を確保するため
に５μｍ程度に厚く形成する必要があり、メッキ法を用
いて形成するのが適当である。しかし蒸着やスパッタリ
ング等で形成しても良い。バリアメタル１１上であって
配線層１０を形成する領域を除く領域にホトレジスト層
を形成し、バリアメタル１１をメッキの電極として利用
し、ホトレジスト層で覆われていないバリアメタル１１
上にＣｕのメッキ層からなる配線層１０を形成する。こ
の後、ホトレジスト層を除去し、さらに、配線層１０を
マスクとして用いてエッチングを行い、バリアメタル１
１の不要部分を除去する。Next, a wiring layer 10 connected to the Al electrode 1 is formed. This wiring layer 10 needs to be formed to be as thick as about 5 μm in order to secure mechanical strength, and it is appropriate to form it using a plating method. However, it may be formed by vapor deposition or sputtering. A photoresist layer is formed on the barrier metal 11 in a region other than the region where the wiring layer 10 is formed, and the barrier metal 11 is used as a plating electrode, and is not covered with the photoresist layer.
A wiring layer 10 made of a Cu plating layer is formed thereon. Thereafter, the photoresist layer is removed, and etching is performed using the wiring layer 10 as a mask, thereby forming the barrier metal 1.
1. Remove unnecessary portions.
【００３６】次に、ポリイミド層１２を全面に塗布し、
露光・現像により、配線層１０上のポリイミド層１２に
開口部４を形成する。膜厚は、最大で２０μｍ〜２５μ
ｍである。また開口部４の開口径は、５０μｍ程度が良
い。尚、現像後は２００℃程度の温度下でポリイミド層
１２をベーキングすると良い。Next, a polyimide layer 12 is applied to the entire surface,
The opening 4 is formed in the polyimide layer 12 on the wiring layer 10 by exposure and development. The film thickness is up to 20μm ~ 25μ
m. The diameter of the opening 4 is preferably about 50 μm. After the development, the polyimide layer 12 is preferably baked at a temperature of about 200 ° C.
【００３７】次いで、メッキのためのシード層としてＣ
ｒ５、Ｃｕ６を形成し、この上に電解メッキによりＣｕ
から成るメタルポスト７を形成する。ここで、メタルポ
スト７の形成は、以下のようにして行われる。Next, C is used as a seed layer for plating.
r5 and Cu6 are formed, and Cu is formed thereon by electrolytic plating.
Is formed. Here, the formation of the metal post 7 is performed as follows.
【００３８】先ず、図４（ａ）において、ポリイミド層
１２を全面に塗布し、露光・現像により、配線層１０上
のポリイミド層１２に開口部４を形成した後に、メッキ
のためのシード層としてＣｒ５、Ｃｕ６を形成し、この
上にポリイミド層２０を介して電解メッキによりＣｕか
ら成る第１の金属層７Ａを形成する。First, in FIG. 4A, a polyimide layer 12 is coated on the entire surface, and an opening 4 is formed in the polyimide layer 12 on the wiring layer 10 by exposure and development, and then a seed layer for plating is formed. Cr5 and Cu6 are formed, and a first metal layer 7A made of Cu is formed thereon by electrolytic plating via a polyimide layer 20.
【００３９】続いて、図４（ｂ）に示すように、前記第
１の金属層７Ａを被覆するようにポリイミド層２１を全
面に塗布し、露光・現像により、このポリイミド層２１
に第１の金属層７Ａの上面部より少なくとも小さいサイ
ズの開口部２２を形成した後に、電解メッキによりＣｕ
から成る第２の金属層７Ｂを形成する。Subsequently, as shown in FIG. 4B, a polyimide layer 21 is applied to the entire surface so as to cover the first metal layer 7A, and the polyimide layer 21 is exposed and developed.
After an opening 22 having a size at least smaller than the upper surface of the first metal layer 7A is formed, Cu is formed by electrolytic plating.
The second metal layer 7B made of is formed.
【００４０】更に、図４（ｃ）に示すように、前記ポリ
イミド層２１を除去することで、前記第１の金属層７Ａ
と第２の金属層７Ｂから成るメタルポスト７を形成す
る。Further, as shown in FIG. 4C, by removing the polyimide layer 21, the first metal layer 7A is removed.
And a metal post 7 composed of a second metal layer 7B.
【００４１】そして、このメタルポスト７が露出するよ
うに不図示のホトレジスト層を形成し、半田バンプ８を
形成する。Then, a photoresist layer (not shown) is formed so that the metal posts 7 are exposed, and solder bumps 8 are formed.
【００４２】最後に、ホトレジスト層を除去し、半田バ
ンプ８をマスクとして、シード層の不要部分をエッチン
グにより除去する。そして、半導体基板をダイシング工
程により、スクライブラインに沿ってチップに分割し、
チップサイズ・パッケージとして完成する。Finally, the photoresist layer is removed, and unnecessary portions of the seed layer are removed by etching using the solder bumps 8 as a mask. Then, the semiconductor substrate is divided into chips along scribe lines by a dicing process,
Completed as chip size package.
【００４３】以上、本発明は、再配線型で説明してきた
が、樹脂封止型でも実施できることは言うまでもない。Although the present invention has been described with reference to the rewiring type, it goes without saying that the present invention can also be implemented with a resin-sealed type.
【００４４】[0044]
【発明の効果】本発明によれば、メタルポストの上面部
に凸部が形成されていることで、半田バンプとの密着表
面積が増大することになり、密着強度が増大し、信頼性
が向上する。特に、チップサイズパッケージと実装基板
との実装時に、従来のように実装ストレスにより応力が
加わっても凸部の存在により、この凸部で半田クラック
が止まり、半田バンプの密着強度を向上させることがで
きる。According to the present invention, since the convex portion is formed on the upper surface of the metal post, the contact surface area with the solder bump is increased, the adhesive strength is increased, and the reliability is improved. I do. In particular, when mounting the chip size package and the mounting board, even if a stress is applied due to mounting stress as in the conventional case, the presence of the convex portion stops the solder crack at this convex portion and improves the adhesion strength of the solder bump. it can.
【００４５】更に、メタルポスト径が微細化されるに従
って、メタルポストと半田バンプとの密着強度の低下が
予想されるが、本発明を採用することで密着強度の低下
を抑えることができる。Further, as the diameter of the metal post is reduced, the adhesion strength between the metal post and the solder bump is expected to decrease. However, by employing the present invention, the decrease in the adhesion strength can be suppressed.
【図１】本発明の実施形態に係るチップサイズパッケー
ジに用いられるメタルポストを説明する断面図である。FIG. 1 is a cross-sectional view illustrating a metal post used in a chip size package according to an embodiment of the present invention.
【図２】本発明の実施形態に係るチップサイズパッケー
ジに用いられるメタルポストを説明する断面図である。FIG. 2 is a cross-sectional view illustrating a metal post used in a chip size package according to an embodiment of the present invention.
【図３】本発明の実施形態に係るチップサイズパッケー
ジと実装基板との実装状態を説明する断面図である。FIG. 3 is a cross-sectional view illustrating a mounting state of a chip size package and a mounting board according to the embodiment of the present invention.
【図４】本発明の実施形態に係るチップサイズパッケー
ジに用いられるメタルポストの製造方法を説明する断面
図である。FIG. 4 is a cross-sectional view illustrating a method of manufacturing a metal post used in a chip size package according to an embodiment of the present invention.
【図５】従来のチップサイズパッケージに用いられるメ
タルポストを説明する断面図である。FIG. 5 is a cross-sectional view illustrating a metal post used in a conventional chip size package.
【図６】従来のチップサイズパッケージと実装基板との
実装状態を説明する断面図である。FIG. 6 is a cross-sectional view illustrating a mounting state of a conventional chip size package and a mounting board.
Claims (4)
する絶縁層と、前記金属電極パッド上の絶縁層に形成さ
れた開口部と、この開口部に形成されたメタルポスト
と、このメタルポストに固着された半田バンプとを具備
するチップサイズパッケージに於いて、 前記メタルポストの上面部には、前記半田バンプとの密
着性を高めるための凸部が形成されていることを特徴と
するチップサイズパッケージ。An insulating layer covering a surface of a chip including a metal electrode pad; an opening formed in the insulating layer on the metal electrode pad; a metal post formed in the opening; In a chip size package having a solder bump fixed thereto, a convex portion for improving adhesion to the solder bump is formed on an upper surface of the metal post. package.
に延在する配線層と、この配線層を含むチップ表面を被
覆する絶縁層と、前記配線層上の絶縁層に形成された開
口部と、この開口部に形成されたメタルポストと、この
メタルポストに固着された半田バンプとを具備するチッ
プサイズパッケージに於いて、 前記メタルポストの上面部には、前記半田バンプとの密
着性を高めるための凸部が形成されていることを特徴と
するチップサイズパッケージ。2. A wiring layer connected to the metal electrode pad and extending on the chip surface, an insulating layer covering the chip surface including the wiring layer, and an opening formed in the insulating layer on the wiring layer. In a chip size package having a metal post formed in the opening and a solder bump fixed to the metal post, the upper surface of the metal post has an improved adhesion with the solder bump. Chip size package characterized by having a convex portion for forming the same.
の絶縁層で被覆する工程と、 前記金属電極パッド上の第１の絶縁層に開口部を形成し
た後、この開口部内に第１の金属層を形成する工程と、 前記第１の金属層上に少なくともその上面部よりも小さ
い開口部を有する第２の絶縁層を形成する工程と、 前記開口部内に第２の金属層を形成した後に、前記第２
の絶縁層を除去して前記第１の金属層と第２の金属層か
ら成るメタルポストを形成する工程と、 前記メタルポスト上に半田バンプを形成する工程とを具
備したことを特徴とするチップサイズパッケージの製造
方法。3. A chip surface including a metal electrode pad is firstly
Forming an opening in the first insulating layer on the metal electrode pad, and then forming a first metal layer in the opening; and forming a first metal layer in the opening. Forming a second insulating layer having an opening smaller than at least the upper surface thereof; forming a second metal layer in the opening;
Forming a metal post composed of the first metal layer and the second metal layer by removing the insulating layer, and forming a solder bump on the metal post. Manufacturing method of size package.
に延在する配線層を形成する工程と、 前記配線層を含むチップ表面を第１の絶縁層で被覆する
工程と、 前記配線層上の第１の絶縁層に開口部を形成した後、こ
の開口部内に第１の金属層を形成する工程と、 前記第１の金属層上に少なくともその上面部よりも小さ
い開口部を有する第２の絶縁層を形成する工程と、 前記開口部内に第２の金属層を形成した後に、前記第２
の絶縁層を除去して前記第１の金属層と第２の金属層か
ら成るメタルポストを形成する工程と、 前記メタルポスト上に半田バンプを形成する工程とを具
備したことを特徴とするチップサイズパッケージの製造
方法。4. A step of forming a wiring layer connected to the metal electrode pad and extending on the chip surface; a step of covering the chip surface including the wiring layer with a first insulating layer; Forming an opening in the first insulating layer, forming a first metal layer in the opening, and forming a second metal layer on the first metal layer having at least an opening smaller than an upper surface of the first metal layer. Forming an insulating layer; forming a second metal layer in the opening;
Forming a metal post composed of the first metal layer and the second metal layer by removing the insulating layer, and forming a solder bump on the metal post. Manufacturing method of size package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10334175A JP2000164617A (en) | 1998-11-25 | 1998-11-25 | Chip-sized package and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10334175A JP2000164617A (en) | 1998-11-25 | 1998-11-25 | Chip-sized package and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000164617A true JP2000164617A (en) | 2000-06-16 |
Family
ID=18274385
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10334175A Pending JP2000164617A (en) | 1998-11-25 | 1998-11-25 | Chip-sized package and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000164617A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10309502A1 (en) * | 2003-01-10 | 2004-07-22 | Samsung Electronics Co., Ltd., Suwon | Solder bump structure and method of making the same |
| WO2008078655A1 (en) * | 2006-12-25 | 2008-07-03 | Rohm Co., Ltd. | Semiconductor device |
| JP2009524927A (en) * | 2006-02-20 | 2009-07-02 | ネペス コーポレーション | Semiconductor chip on which solder bump is formed and method for manufacturing solder bump |
| KR101037832B1 (en) * | 2008-05-09 | 2011-05-31 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor Device And Fabricating Method Thereof |
| KR101073485B1 (en) * | 2009-03-18 | 2011-10-17 | 성균관대학교산학협력단 | Preparation method of lead free solder bump having improved mechanical reliability |
| US9343416B2 (en) | 2006-12-25 | 2016-05-17 | Rohm Co., Ltd. | Semiconductor device employing wafer level chip size package technology |
| JP2019087693A (en) * | 2017-11-09 | 2019-06-06 | 株式会社デンソー | Semiconductor device |
| EP4071792A1 (en) * | 2021-04-07 | 2022-10-12 | MediaTek Inc. | Three-dimensional pad structure and interconnection structure for electronic devices |
-
1998
- 1998-11-25 JP JP10334175A patent/JP2000164617A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6959856B2 (en) | 2003-01-10 | 2005-11-01 | Samsung Electronics Co., Ltd. | Solder bump structure and method for forming a solder bump |
| DE10309502A1 (en) * | 2003-01-10 | 2004-07-22 | Samsung Electronics Co., Ltd., Suwon | Solder bump structure and method of making the same |
| DE10309502B4 (en) * | 2003-01-10 | 2009-01-02 | Samsung Electronics Co., Ltd., Suwon | Method for producing a solder bump structure and solder bump structure |
| JP2009524927A (en) * | 2006-02-20 | 2009-07-02 | ネペス コーポレーション | Semiconductor chip on which solder bump is formed and method for manufacturing solder bump |
| US9018762B2 (en) | 2006-12-25 | 2015-04-28 | Rohm Co., Ltd. | Semiconductor device bonding with stress relief connection pads |
| EP2099065A1 (en) * | 2006-12-25 | 2009-09-09 | Rohm Co., Ltd. | Semiconductor device |
| EP2099065A4 (en) * | 2006-12-25 | 2011-02-23 | Rohm Co Ltd | Semiconductor device |
| CN101542704B (en) * | 2006-12-25 | 2011-04-20 | 罗姆股份有限公司 | Semiconductor device |
| US8446008B2 (en) | 2006-12-25 | 2013-05-21 | Rohm Co., Ltd. | Semiconductor device bonding with stress relief connection pads |
| JP5570727B2 (en) * | 2006-12-25 | 2014-08-13 | ローム株式会社 | Semiconductor device |
| WO2008078655A1 (en) * | 2006-12-25 | 2008-07-03 | Rohm Co., Ltd. | Semiconductor device |
| US9343416B2 (en) | 2006-12-25 | 2016-05-17 | Rohm Co., Ltd. | Semiconductor device employing wafer level chip size package technology |
| KR101037832B1 (en) * | 2008-05-09 | 2011-05-31 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor Device And Fabricating Method Thereof |
| KR101073485B1 (en) * | 2009-03-18 | 2011-10-17 | 성균관대학교산학협력단 | Preparation method of lead free solder bump having improved mechanical reliability |
| JP2019087693A (en) * | 2017-11-09 | 2019-06-06 | 株式会社デンソー | Semiconductor device |
| EP4071792A1 (en) * | 2021-04-07 | 2022-10-12 | MediaTek Inc. | Three-dimensional pad structure and interconnection structure for electronic devices |
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