JPS615561A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS615561A
JPS615561A JP59125185A JP12518584A JPS615561A JP S615561 A JPS615561 A JP S615561A JP 59125185 A JP59125185 A JP 59125185A JP 12518584 A JP12518584 A JP 12518584A JP S615561 A JPS615561 A JP S615561A
Authority
JP
Japan
Prior art keywords
electrode pad
film
aluminum
insulating film
metal film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59125185A
Other languages
Japanese (ja)
Inventor
Masami Kiyono
清野　政美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59125185A priority Critical patent/JPS615561A/en
Publication of JPS615561A publication Critical patent/JPS615561A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
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    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To improve the reliability of a semiconductor chip by a method wherein an electrode pad is formed into a multilayer structure for the electrode pad to be mechanically strong enough to withstand pressure imposed during a wire- bonding process so that such pressure may not cause deformation of the electrode pad or cracks in insulating films. CONSTITUTION:On a gate electrode 14 constituting a MOSFETQM in a semiconductor chip 1, an insulating film 15 is formed of SiO2, PSG, or the like. An electrode pad 10 is formed on the insulating film 15 in a region surrounding the semiconductor chip 1. The electrode pad 10 is formed simultaneously with an aluminum wiring 16 to be connected to a diffused layer 12 of the MOSFETQM. Between the insulating film 15 and the electrode pad 10, there is a metal film 17 made of tungsten, molybdenum, titanium, or the like, which is superior to aluminum in strength or hardness, with the film 15, pad 10, and film 17 combining into a single lamination. In a semiconductor device designed as such, the electrode pad 10 will not experience deformation even under the pressure imposed upon the electrode pad 10 during a process wherein a wire 6 is connected to the electrode pad 10.

Description

【発明の詳細な説明】 （技術分野〕 本発明は半導体装置に関し、特に外部導出リード接続用
の電極パッドにおける信頼性の向上を図った半導体装置
に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a semiconductor device, and more particularly to a semiconductor device with improved reliability in electrode pads for connecting external leads.

〔背景技術〕[Background technology]

一般にＩＣ，ＬＳＩ等の半導体装置は、所要の回路素子
を形成した半導体チップをセラミックやレジン（プラス
チック）等のパッケージ内に内装しているが、このパッ
ケージに設けられた外部導出リードと半導体チップとを
電気的に接続するた　　′めＫ、外部導出リードのイン
ナ部と半導体チップの電極パッドとにわたって極細のワ
イヤが接続される。ところで、このワイヤの接続には超
音波ボンブイノブ法、熱圧着法等が利用されている（工
業調査会発行電子材料１９８１年別冊、昭和５６年１１
月１０日発行、１５６頁〜１６２頁）。しかしながら、
いずれの方法もワイヤを被接続面（電極パッド等の表面
）Ｋ所定の圧力で押圧する必要がある。このため、アル
ミニウム等で形成された電極パッドはこの押圧力により
若干変形されて下側の絶縁膜に応力を生じさせ、この応
力によってガラス質である二酸化シリコン膜やＰＳＧ等
の絶縁膜忙クラックを生じさせるといり事故が生じ易い
。特に近年の半導体チップは集積度の向上に伴なって電
極パッドのアルミニウム膜が１．２μｍから０．８μｍ
と薄型化され、これと共に下側絶縁膜も薄くなる傾向に
あるために、この種の事故は生じ易い。そして、このよ
うな事故が生じると絶縁膜のクラックを通して電極パッ
ドと半導体基板との間に電流リークパスが発生し、電極
パッドないし半導体チップ全体の信頼性が低下されるこ
とＫなる。In general, semiconductor devices such as ICs and LSIs have a semiconductor chip with required circuit elements formed inside a package made of ceramic or resin (plastic), and the external leads provided in this package and the semiconductor chip are connected to each other. In order to electrically connect the semiconductor chip, an extremely thin wire is connected between the inner part of the external lead and the electrode pad of the semiconductor chip. By the way, the ultrasonic bomb-in-knob method, thermocompression bonding method, etc. are used to connect these wires (Electronic Materials 1981 separate volume published by Kogyo Kenkyukai, November 1981).
Published on March 10th, pp. 156-162). however,
In either method, it is necessary to press the wire onto the surface to be connected (the surface of the electrode pad, etc.) with a predetermined pressure. For this reason, the electrode pad made of aluminum or the like is slightly deformed by this pressing force, creating stress in the underlying insulating film, and this stress can cause cracks in the insulating film of glassy silicon dioxide films, PSG, etc. Accidents are likely to occur. In particular, with the improvement in the degree of integration of semiconductor chips in recent years, the aluminum film of the electrode pad has become thinner from 1.2 μm to 0.8 μm.
This kind of accident is likely to occur because the lower insulating film tends to become thinner as well. If such an accident occurs, a current leak path will occur between the electrode pad and the semiconductor substrate through cracks in the insulating film, reducing the reliability of the electrode pad or the semiconductor chip as a whole.

〔発明の目的〕[Purpose of the invention]

本発明の目的はワイヤボンディングに対する電極パッド
および下地絶縁膜の機械的強度を向上して電極パッドな
いし半導体チップ忙おける信頼性の向上を達成すること
めできる半導体装置を提供することＫある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can improve the mechanical strength of an electrode pad and a base insulating film for wire bonding, thereby improving the reliability of the electrode pad or semiconductor chip.

本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.

すなわち、アルミニウム等で形成した電極パッドと下地
絶縁膜との間に電極パッドよりも高強度の金属膜を形成
して電極パッドを多層構造とすることＫより、ワイヤボ
ンディング時の押圧力に対する電極パッドの実質的な機
械強度を向上し、とれｋより押圧力による電極パッドの
変形やこれに伴なう絶縁膜のクラック等を防止し、電流
リークバスによる特性、信頼性の低下を防止するもので
ある。In other words, by forming a metal film with higher strength than the electrode pad between the electrode pad made of aluminum or the like and the base insulating film to form the electrode pad into a multilayer structure, the electrode pad can withstand the pressing force during wire bonding. This improves the actual mechanical strength of the electrode pad, prevents deformation of the electrode pad due to pressing force and cracks in the insulating film caused by this, and prevents deterioration of characteristics and reliability due to current leakage. .

〔実施例１〕 第１図は本発明をＭＯ３型トランジスタを回路素子とす
る半導体装置に適用した実施例を示し、その要部を第２
図に拡大して示す。第１図において、半導体チップ１は
セラミック等のベース２内底面上忙載置され、Ａｕ　　
Ｓｉ共晶３等によりベースに固着される。また、ベース
２の周囲忙は低融点ガラス４を用いて外部導出リード５
を配設し、　　　　　　　ｌこれら外部導出リード５と
、半導体チップｌの上面に形成した電極パッド１ｏとを
極細のアルミニウム製ワイヤ６にて接続して両者間の電
気的接続を図っている。ベース２上にはキャップ７を固
着し、内部を気密に保ってパ、ツ・クー・ジ、を完成し
ている。[Embodiment 1] FIG. 1 shows an embodiment in which the present invention is applied to a semiconductor device using an MO3 type transistor as a circuit element.
It is shown enlarged in the figure. In FIG. 1, a semiconductor chip 1 is placed on the inner bottom surface of a base 2 made of ceramic or the like, and an Au
It is fixed to the base by Si eutectic 3 or the like. In addition, the surrounding area of the base 2 is made of low melting point glass 4, and external lead 5 is used.
These external leads 5 and electrode pads 1o formed on the upper surface of the semiconductor chip 1 are connected by ultra-thin aluminum wires 6 to establish an electrical connection between them. A cap 7 is fixed on the base 2 to keep the inside airtight and complete the package.

前記半導体チップ１は、第２図のように−の導電型の半
導体基板１１上に逆導電型の拡散層１２゜１２を形成し
、半導体基板１１の主面上にゲート絶縁膜１３を形成し
た上でその上にゲート電極１４を形成することによりＭ
Ｏ８型電界効果トランジスタ（ＭＯＳＦＥＴ）ＱＭを構
成している。一方、ゲート電極１４上にはＳ　ｉＯ，や
ＰＳＧ（りんガラス）等の絶縁膜１５を形成し、前記半
導体チップ、１の周辺位置のこの絶縁膜１５上に電極（
ボンディング）パッド１０を形成している。この電極パ
ッド１０は前記ＭＯ８ＦＥＴＱＭの拡散層１２゜１２へ
接続されるアルミニウム配線１６．１６と同時にアルミ
ニウムにて形成し、その下側、つまり電極パッド１０と
下地絶縁膜１５との間にはアルミニウムよりも強度（硬
度）の高いタングステン、モリブデン、チタン等の金属
膜１７を一体に形成している。この金属膜１７は、例え
ばアルミニウム配線１６の形成前、つまり絶縁膜１５の
形成直後に前記金属のいずれかを全面に蒸着し、電極パ
ッド相当部位のみを残して他の部位をエツチング除去す
ることにより形成する。また、タングステン等の金属膜
１７の形成にあたりては、ゲート電極材料としてのタン
グステン等を使用し、ゲート電極形成プロセスを使用し
てボンディングバット部に設けるものであってもよい。As shown in FIG. 2, the semiconductor chip 1 has a diffusion layer 12 of an opposite conductivity type formed on a semiconductor substrate 11 of a negative conductivity type, and a gate insulating film 13 formed on the main surface of the semiconductor substrate 11. M by forming the gate electrode 14 thereon.
It constitutes an O8 type field effect transistor (MOSFET) QM. On the other hand, an insulating film 15 made of SiO, PSG (phosphorous glass), etc. is formed on the gate electrode 14, and an electrode (
A bonding) pad 10 is formed. This electrode pad 10 is formed of aluminum at the same time as the aluminum wiring 16.16 connected to the diffusion layer 12. A metal film 17 made of tungsten, molybdenum, titanium, or the like having high strength (hardness) is also integrally formed. This metal film 17 can be formed, for example, by depositing one of the metals on the entire surface before forming the aluminum wiring 16, that is, immediately after forming the insulating film 15, and etching away the other parts, leaving only the part corresponding to the electrode pad. Form. Furthermore, in forming the metal film 17 of tungsten or the like, tungsten or the like may be used as the gate electrode material and may be provided on the bonding butt portion using a gate electrode forming process.

そして、前記アルミニウム配線１６．１６および電極パ
ッド１０の形成後にシラン等のパッシベーション膜１８
を形成し、電極パッド１０部位を開口して電極パッド１
ｏのアルミニウム面を露呈すれば、アルミニウムワイヤ
６の接続が可能とされる。After forming the aluminum wiring 16, 16 and the electrode pad 10, a passivation film 18 of silane or the like is formed.
, and open the electrode pad 10 portion to form the electrode pad 1.
By exposing the aluminum surface of the aluminum wire 6, the aluminum wire 6 can be connected.

したがって、この構成によればワイヤ６を電極パッド１
０に接続するに際し電極パッド１ｏ面に押圧力が加えら
れても、電極パッド１ｏは下側に形成した金属膜１７の
高強度特性忙よって全体の強度が高められているので、
容易に変形されることはなく、したがって変形に伴なう
応力を絶縁膜１５に発生させることはない。これにより
、絶縁膜１５ないし更に下側の絶縁膜のクラックは防止
でき、り２ツクを通しての電流す二りパスを未然に防止
して半導体チップないし半導体装置全体の信頼性を向上
できる。Therefore, according to this configuration, the wire 6 is connected to the electrode pad 1.
Even if a pressing force is applied to the surface of the electrode pad 1o when connecting to the electrode pad 1o, the overall strength of the electrode pad 1o is increased due to the high strength properties of the metal film 17 formed on the lower side.
It is not easily deformed, and therefore stress associated with deformation is not generated in the insulating film 15. As a result, cracks in the insulating film 15 or the lower insulating film can be prevented, and a double current path through the gate can be prevented, thereby improving the reliability of the semiconductor chip or the semiconductor device as a whole.

〔実施例２〕 第３図は本発明の他の実施例の要部断面図を示しており
、図中第２図と同一部分には同一符号を付して詳細な説
明は省略する。本例にあっては、ＭＯ８ＦＥＴＱＭの拡
散層１２．１２に接続する　゛配線１６Ａ、１６Ａを多
層構造に形成すると共に、電極（ボンディング）パッド
部をこれと同一の配線で、つまり配線の一部として構成
している。前記配線１６Ａ、１６Ａは、所謂マイグレー
ションを防止する目的により上、下のアルミニウム膜１
９゜２０とその中間の金属膜２１とで構成しており、金
属膜２１の材料にはタングステン、モリブデン。[Embodiment 2] FIG. 3 shows a sectional view of a main part of another embodiment of the present invention, and the same parts as in FIG. 2 are given the same reference numerals and detailed explanations are omitted. In this example, the wirings 16A and 16A connected to the diffusion layers 12 and 12 of the MO8FETQM are formed in a multilayer structure, and the electrode (bonding) pad portion is formed with the same wiring, that is, as part of the wiring. It consists of The wirings 16A, 16A are coated with the upper and lower aluminum films 1 for the purpose of preventing so-called migration.
It is composed of 9° 20 and a metal film 21 in between, and the material of the metal film 21 is tungsten or molybdenum.

チタン等のアルミニウムよりも硬度の高い金属材料を利
用している。したがって、この配線１６Ａ。It uses metal materials such as titanium that are harder than aluminum. Therefore, this wiring 16A.

１６Ａの一部を電極パッド部として構成すれば、上層の
アルミニウム膜１９を電極パッドＩＯＡとして構成し、
中間の金属膜２１を高硬度の下側金属膜１７Ａとして構
成でき、更に下側にアルミニウム膜２０が存在するもの
の前例と同様に多層構造の電極パッド構造を構成できる
。If a part of 16A is configured as an electrode pad part, the upper aluminum film 19 is configured as an electrode pad IOA,
The middle metal film 21 can be configured as a highly hard lower metal film 17A, and a multilayered electrode pad structure can be configured as in the previous example, although the aluminum film 20 is further provided on the lower side.

この構成によれば、上側のアルミニウム膜からなる電極
パッドＩＯＡは、下側の中間金属膜からなる金属膜１７
Ａの高硬度特性によって全体強度が向上され、ワイヤ６
接続時の押圧力によっても容易には変形されることはな
く、絶縁膜１５のクラックやこれに伴なう電流リークパ
ス等を防止して信頼性の向上を達成できる。また、本例
では配線１６Ａ、１６Ａの一部として電極パッド部を構
成しているので、プロセスの増加は全くなく、プロセス
上でも有利である。According to this configuration, the electrode pad IOA made of the upper aluminum film is connected to the metal film 17 made of the lower intermediate metal film.
The high hardness property of A improves the overall strength, making wire 6
It is not easily deformed by the pressing force applied during connection, and it is possible to prevent cracks in the insulating film 15 and the resulting current leak path, thereby improving reliability. Further, in this example, since the electrode pad portion is formed as a part of the wirings 16A, 16A, there is no increase in the number of processes, which is advantageous in terms of the process.

〔効果〕〔effect〕

（１）アルミニウム等で構成した電極パッドの下側　　
　　　　　、ＩＫアルミニウムよりも高強度の金属膜を
形成して多層構造としているので、電極パッド全体の強
度を増大してワイヤ接続時における電極パッドの変形を
防止し、これＫより下地絶縁膜における応力の発生およ
びこれに伴なうクラックの発生を防止し、電流リークパ
ス等による信頼性の低下を防止できる。(1) Lower side of electrode pad made of aluminum etc.
, a multilayer structure is formed by forming a metal film with higher strength than IK aluminum, which increases the strength of the entire electrode pad and prevents deformation of the electrode pad during wire connection. It is possible to prevent the generation of cracks and cracks that accompany this, and to prevent a decrease in reliability due to current leakage paths and the like.

（２）下側の金属膜は絶縁膜の形成後で電極パッドおよ
びアルミニウム配線の形成前に形成しているので、従来
の製造プロセス間に１工程を挿入するだけでよく、容易
に本発明構造を構成できる。(2) Since the lower metal film is formed after the formation of the insulating film and before the formation of the electrode pads and aluminum wiring, it is only necessary to insert one step between the conventional manufacturing processes, and the structure of the present invention can be easily constructed. can be configured.

（３）電極パッドと下側の金属膜を多層構造のアルミニ
ウム配線の上側アルミニウム膜と中間の金属膜とで構成
しているので、アルミニウム配線の形成と同時に電極パ
ッドを構成でき、製造プロセスを更に有利なものにでき
る。(3) Since the electrode pad and the lower metal film are composed of the upper aluminum film and the middle metal film of the multilayer aluminum wiring, the electrode pad can be constructed at the same time as the aluminum wiring is formed, further simplifying the manufacturing process. It can be made advantageous.

（４）ポンディングパッドの下側の金属膜をＭ−Ｉ　Ｓ
半導体装置のゲート電極の形成プロセスを使用して設け
ることができるので、簡便な製造プロセスをもって前記
金属膜を形成することができる。(4) M-I S the metal film under the bonding pad.
Since the metal film can be provided using a process for forming a gate electrode of a semiconductor device, the metal film can be formed using a simple manufacturing process.

以上本発明者によってなされた発明を実施例忙もとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。たとえば、金属膜は前
述以外にも、銅、あるいは種々の合金を使用することも
できる。Although the invention made by the present inventor has been specifically explained using examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, in addition to the metal film described above, copper or various alloys can also be used.

〔利用分野〕[Application field]

以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるセラミックハラケー
ジ型半導体装置でかつ超音波ポンディング方式のワイヤ
ボンディング技術を使用する半導体装置に適用した場合
について説明したが、それに限定されるものではなく、
レジンモールド型のパッケージを用いる半導体装置や、
熱圧着法（ネイルヘッドボンディング）を用いる半導体
装置にも適用することができる。The above explanation mainly describes the case where the invention made by the present inventor is applied to the field of application which is the background of the invention, which is a ceramic Hara cage type semiconductor device and a semiconductor device that uses ultrasonic bonding wire bonding technology. However, it is not limited to
Semiconductor devices using resin molded packages,
It can also be applied to semiconductor devices using thermocompression bonding (nail head bonding).

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例の全体断面図、第２図は要部
の拡大断面図、 第３図は他の実施例の拡大断面図である。 １・・・半導体チップ、６・・・ワイヤ、１０．ＩＯＡ
・・・電極パッド（アルミニウム）、１１・・・半導体
基板、１２・・・拡散層、１４・・・ゲート電極、１５
・・・絶縁膜、１６，１６Ａ・・・配線、１７．１７Ａ
・・・金属膜、１８・・・パッジベニジョン膜、１９．
２１・９・上。 下アルミニウム膜、２０・・・中間金属膜。 代理人　弁理士　　高　橋　明　失 策　　１　　図FIG. 1 is an overall sectional view of one embodiment of the present invention, FIG. 2 is an enlarged sectional view of essential parts, and FIG. 3 is an enlarged sectional view of another embodiment. 1... Semiconductor chip, 6... Wire, 10. IOA
... Electrode pad (aluminum), 11 ... Semiconductor substrate, 12 ... Diffusion layer, 14 ... Gate electrode, 15
...Insulating film, 16,16A...Wiring, 17.17A
. . . Metal film, 18 . . . Pudge venition film, 19.
21.9.1. Lower aluminum film, 20... intermediate metal film. Agent Patent Attorney Akira Takahashi Mistake 1 Diagram

Claims (1)

【特許請求の範囲】 １、半導体チップの絶縁膜上にワイヤボンディング用の
電極パッドを設けてなる半導体装置において、前記電極
パッドと下地、絶縁膜との間に電極パッドよりも高強度
の金属膜を形成して電極パッドを多層構造としたことを
特徴とする半導体装置。 ２、電極パッドをアルミニウム膜で形成し、その下側に
タングステン、モリブデン、チタン等の金属膜を形成し
てなる特許請求の範囲第１項記載の半導体装置。 ３、電極パッドと金属膜とを多層アルミニウム配線の一
部として形成し、電極パッドを上層アルミニウムで構成
し、金属膜を中間異種金属で形成してなる特許請求の範
囲第１項記載の半導体装置。[Claims] 1. In a semiconductor device in which an electrode pad for wire bonding is provided on an insulating film of a semiconductor chip, a metal film having higher strength than the electrode pad is provided between the electrode pad and the base and insulating film. A semiconductor device characterized in that an electrode pad has a multilayer structure by forming. 2. The semiconductor device according to claim 1, wherein the electrode pad is formed of an aluminum film, and a metal film of tungsten, molybdenum, titanium, etc. is formed below the electrode pad. 3. The semiconductor device according to claim 1, wherein the electrode pad and the metal film are formed as part of a multilayer aluminum wiring, the electrode pad is made of upper layer aluminum, and the metal film is made of an intermediate dissimilar metal. .
JP59125185A 1984-06-20 1984-06-20 Semiconductor device Pending JPS615561A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59125185A JPS615561A (en) 1984-06-20 1984-06-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59125185A JPS615561A (en) 1984-06-20 1984-06-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS615561A true JPS615561A (en) 1986-01-11

Family

ID=14904007

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59125185A Pending JPS615561A (en) 1984-06-20 1984-06-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS615561A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01220850A (en) * 1988-02-29 1989-09-04 Sharp Corp Electrode structure of semiconductor device
US5365112A (en) * 1991-10-14 1994-11-15 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device having an improved bonding pad structure
US5394013A (en) * 1990-11-28 1995-02-28 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with an elevated bonding pad
JP2005294872A (en) * 2005-07-05 2005-10-20 Mitsubishi Electric Corp Semiconductor device and its manufacturing method
JP2007507080A (en) * 2003-08-22 2007-03-22 アーベーベー・シュバイツ・アーゲー Pressure contact spring for contact structure in power semiconductor module

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01220850A (en) * 1988-02-29 1989-09-04 Sharp Corp Electrode structure of semiconductor device
US5394013A (en) * 1990-11-28 1995-02-28 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with an elevated bonding pad
US5365112A (en) * 1991-10-14 1994-11-15 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device having an improved bonding pad structure
JP2007507080A (en) * 2003-08-22 2007-03-22 アーベーベー・シュバイツ・アーゲー Pressure contact spring for contact structure in power semiconductor module
JP4800764B2 (en) * 2003-08-22 2011-10-26 アーベーベー・シュバイツ・アーゲー Pressure contact spring for contact structure in power semiconductor module
JP2005294872A (en) * 2005-07-05 2005-10-20 Mitsubishi Electric Corp Semiconductor device and its manufacturing method

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