JP3241935B2 - Flat display device - Google Patents

Flat display device

Info

Publication number
JP3241935B2
JP3241935B2 JP15579694A JP15579694A JP3241935B2 JP 3241935 B2 JP3241935 B2 JP 3241935B2 JP 15579694 A JP15579694 A JP 15579694A JP 15579694 A JP15579694 A JP 15579694A JP 3241935 B2 JP3241935 B2 JP 3241935B2
Authority
JP
Japan
Prior art keywords
display device
getter
panel
screen display
fed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP15579694A
Other languages
Japanese (ja)
Other versions
JPH0822785A (en
Inventor
治 豊田
圭一 別井
智之 石井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15579694A priority Critical patent/JP3241935B2/en
Publication of JPH0822785A publication Critical patent/JPH0822785A/en
Application granted granted Critical
Publication of JP3241935B2 publication Critical patent/JP3241935B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Manufacture Of Electron Tubes, Discharge Lamp Vessels, Lead-In Wires, And The Like (AREA)
  • Electrodes For Cathode-Ray Tubes (AREA)
  • Vessels, Lead-In Wires, Accessory Apparatuses For Cathode-Ray Tubes (AREA)
  • Cathode-Ray Tubes And Fluorescent Screens For Display (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、蛍光面の励起手段とし
て電界放出型陰極からなる多数の電子源(電子銃)を備
えたフラット形表示装置、及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat display device provided with a large number of electron sources (electron guns) comprising field emission cathodes as means for exciting a phosphor screen, and a method of manufacturing the same.

【0002】電界放出(冷陰極放出ともいう)を利用し
た表示装置(FED:FieldEmitter De
splay)は、高精細で高輝度の表示が可能であり、
次世代の表示デバイスとして注目されている。
A display device using field emission (also referred to as cold cathode emission) (FED: FieldEmitter De)
spray) is capable of displaying high definition and high brightness,
It is drawing attention as a next-generation display device.

【0003】[0003]

【従来の技術】FEDは、微小間隙を介して一対のパネ
ルを対向配置し、それらパネルの周囲を封着した厚さ数
mm程度の偏平状の表示管である。前面側パネルの内面
に蛍光膜が設けられ、背面側パネル上に個々の画素毎に
ミクロンサイズの電界放出型陰極が配列されている。電
界放出型陰極の配列領域が画面表示領域である。
2. Description of the Related Art An FED is a flat display tube having a thickness of about several millimeters in which a pair of panels are arranged to face each other with a small gap therebetween and the periphery of the panels is sealed. A fluorescent film is provided on the inner surface of the front panel, and a micron-sized field emission cathode is arranged for each pixel on the rear panel. The arrangement region of the field emission cathode is a screen display region.

【0004】FEDの製造に際しては、パネルの周囲の
封着と同時に、予め一方のパネルの周縁部の排気口に仮
止めしておいたチップオフ管を接着し、その後にチップ
オフ管を介して内部の排気を行う。そして、チップオフ
管を溶断して排気口を塞ぎ、内部の真空間隙を密閉す
る。
In manufacturing the FED, a chip-off tube temporarily fixed in advance to an exhaust port at a peripheral portion of one of the panels is bonded at the same time as sealing around the panel, and thereafter, the chip-off tube is connected through the chip-off tube. Exhaust the inside. Then, the tip-off tube is blown to close the exhaust port, and the internal vacuum gap is sealed.

【0005】このようなFEDにおいて、電界放出型陰
極(以下では「エミッタ」という)が確実に機能するに
は、エミッタと蛍光面との間隙を少なくとも10-7〜1
-8Torrのいわゆる超高真空に保つ必要がある。こ
のため、通常は、チップオフ管内に非蒸発型ゲッタ(バ
ルクゲッタ)が固定されている。
In such an FED, in order for a field emission cathode (hereinafter referred to as an “emitter”) to function reliably, the gap between the emitter and the phosphor screen must be at least 10 −7 to 1 −7.
It is necessary to maintain a so-called ultra-high vacuum of 0 -8 Torr. For this reason, a non-evaporable getter (bulk getter) is usually fixed in the chip-off tube.

【0006】また、従来において、前面側パネルの内面
に蛍光面(表示面)の全体を囲む溝を設け、その溝の中
にバルクゲッタを埋め込むことにより、バルクゲッタの
大容積化を図る手法が提案されている(特開平5−12
1015号)。
Conventionally, there has been proposed a method of increasing the volume of a bulk getter by providing a groove surrounding the entire phosphor screen (display surface) on the inner surface of the front panel and embedding a bulk getter in the groove. (Japanese Patent Laid-Open No. 5-12)
No. 1015).

【0007】[0007]

【発明が解決しようとする課題】従来のようにバルクゲ
ッタを用いる場合には、その配置位置が限定されてしま
う。つまり、最も薄いバルクゲッタでも厚さが150μ
m程度であり、100μm程度の内部間隙にバルクゲッ
タを収めることはできない。
When a bulk getter is used as in the prior art, the position of the bulk getter is limited. In other words, even the thinnest bulk getter has a thickness of 150μ.
m, and the bulk getter cannot be accommodated in the internal gap of about 100 μm.

【0008】したがって、使用中にガス放出の生じ易い
画面表示領域とゲッタ配置位置とが離れることになり、
画面表示領域の内壁から湧き出たガスが直ちに吸着され
ずに周囲に拡散し、蛍光面やエミッタの汚染、アーク放
電によるエミッタの破損が生じ易いという問題があっ
た。また、間隙が狭くガス流動のコンダクタンスが小さ
いので、画面表示領域内の真空度が局所的に損なわれ、
表示が不安定になるという問題もあった。
[0008] Therefore, the screen display area where gas emission is likely to occur during use is separated from the getter arrangement position,
There is a problem that the gas spouted from the inner wall of the screen display area is not immediately adsorbed but diffuses to the surroundings, and the phosphor and the emitter are easily contaminated and the emitter is easily damaged by arc discharge. In addition, since the gap is small and the conductance of gas flow is small, the degree of vacuum in the screen display area is locally impaired,
There was also a problem that the display became unstable.

【0009】本発明は、このような問題に鑑みてなされ
たもので、画面表示領域内でのガス拡散を可及的に抑え
て高真空状態を維持し、表示を安定化することを目的と
している。
The present invention has been made in view of the above problems, and has as its object to stabilize display by maintaining a high vacuum state by minimizing gas diffusion in a screen display area. I have.

【0010】[0010]

【課題を解決するための手段】請求項1の発明に係る装
置は、蛍光膜を有した前面側のパネルと、前記蛍光膜を
選択的に励起する画面表示のための多数の電界放出型陰
極を有した背面側のパネルとが、真空間隙を介して対向
する構造のフラット形表示装置であって、前記電界放出
型陰極が配置された領域である画面表示領域内に、前記
真空間隙の寸法を局所的に増大させる窪みを有し、前記
窪みの底部に蒸発型ゲッタ材料を蒸発させて被着させた
ゲッタが設けられてなる。
Apparatus according to the invention of claim 1 SUMMARY OF THE INVENTION comprises a front side of the panel having a fluorescent film, a large number of field emission for the screen display to selectively excite the fluorescent film A panel on the back side having a cathode is a flat display device having a structure opposed to each other via a vacuum gap, and a screen display area in which the field emission cathode is arranged ,
Having a depression locally increasing the size of the vacuum gap,
A getter is provided at the bottom of the recess, where the evaporable getter material is evaporated and applied .

【0011】請求項2の発明に係るフラット形表示装置
においては、画面表示領域内に前記真空間隙を区画する
隔壁を備え、前記隔壁の側面に蒸発型ゲッタ材料を蒸発
させて被着させたゲッタが設けられてなる。
The flat display device according to the second aspect of the present invention.
, The vacuum gap is defined in a screen display area
Evaporating getter material on the side surface of the partition wall
A getter is provided.

【0012】[0012]

【0013】[0013]

【0014】[0014]

【0015】[0015]

【作用】画面表示領域の内壁から湧き出た不純ガスは、
近辺の蒸発型ゲッタによって速やかに吸着される。
[Function] The impure gas flowing from the inner wall of the screen display area is
Adsorbed quickly by nearby evaporable getters.

【0016】[0016]

【0017】蒸発型ゲッタを底部に有した窪みの近辺
で、ガス放出によるアーク放電が生じた場合には、窪み
の中が周囲と比べて高真空になるため、その真空度勾配
によりガスが窪みへ流れ込み(拡散し)、アーク放電の
拡がりが抑えられる。
If an arc discharge due to gas discharge occurs near the pit having the evaporable getter at the bottom, the inside of the pit becomes higher in vacuum than the surrounding area, and the gas gradient is reduced due to the degree of vacuum gradient. , And the spread of the arc discharge is suppressed.

【0018】[0018]

【実施例】図1は第1実施例のFED1の構成を示す断
面図、図2はFED1の内部構造を示す部分斜視図、図
3は電子源22の構造の一例を示す図である。
1 is a sectional view showing the structure of an FED 1 according to a first embodiment, FIG. 2 is a partial perspective view showing the internal structure of the FED 1, and FIG. 3 is a view showing an example of the structure of an electron source 22.

【0019】FED1は、ガラス板11を基体とする前
面側パネル10と、ガラス板(又はシリコン板)21を
基体とする背面側パネル20とから構成されており、フ
ルカラーのマトリクス表示が可能なフラット形表示装置
である。両パネル10,20は、約100μmの間隙を
設けて対向配置され、対向領域の周縁部が低融点ガラス
層35によって封着されている。内部の間隙30は10
-7〜10-8Torrの真空であり、間隙寸法は図示しな
いビーズスペーサの点在配置によって均一化されてい
る。
The FED 1 is composed of a front panel 10 having a glass plate 11 as a base and a rear panel 20 having a glass plate (or a silicon plate) 21 as a base. It is a shape display device. The two panels 10 and 20 are opposed to each other with a gap of about 100 μm, and the peripheral edge of the opposed region is sealed with a low melting point glass layer 35. The internal gap 30 is 10
The vacuum is -7 to 10 -8 Torr, and the gap size is made uniform by dotted arrangement of bead spacers (not shown).

【0020】マトリクス表示のスクリーンとなる画面表
示領域IAにおいて、前面側パネル10の内面に蛍光膜
12が設けられ、背面側パネル20の内面に蛍光膜12
を励起するためのエミッタ25が配置されている。
In a screen display area IA serving as a matrix display screen, a fluorescent film 12 is provided on the inner surface of the front panel 10, and the fluorescent film 12 is provided on an inner surface of the rear panel 20.
Is arranged.

【0021】図2のように、蛍光膜12の配置パターン
は、フルカラー表示のための3原色(R,G,B)が一
方向について交互に入れ替わるストライプパターンとさ
れ、帯状の各蛍光膜12とガラス板11との間には、透
明導電膜からなる図示しないアノード電極が設けられて
いる。
As shown in FIG. 2, the arrangement pattern of the fluorescent films 12 is a stripe pattern in which three primary colors (R, G, B) for full color display are alternately switched in one direction. Between the glass plate 11, an anode electrode (not shown) made of a transparent conductive film is provided.

【0022】背面側パネル20においては、ガラス板2
1上に配列されたカソード電極23と、蛍光膜12と同
一方向に延びるゲート電極26とによって電極マトリク
スが構成されている。カソード電極23及びゲート電極
26は、絶縁層24を介して交差し、その各交差部にマ
トリクス表示の単位発光領域を画定する電子源22が形
成されている。単位発光領域の大きさは、例えば100
μm角程度である。
In the rear panel 20, the glass plate 2
An electrode matrix is composed of the cathode electrodes 23 arranged on the first electrode 1 and the gate electrode 26 extending in the same direction as the fluorescent film 12. The cathode electrode 23 and the gate electrode 26 intersect with an insulating layer 24 interposed therebetween, and an electron source 22 for defining a unit light emitting region of a matrix display is formed at each intersection. The size of the unit light emitting area is, for example, 100
It is about μm square.

【0023】電子源22は、図3のように、カソード電
極23と電気的に一体化された円錐状のエミッタ(エミ
ッタティップともいう)25、エミッタ25を露出させ
る開口26aを有したゲート電極26、及びエミッタ2
5の周囲に空隙を形成し且つゲート電極26との絶縁を
保つための絶縁層24から構成されており、実際には数
百以上のエミッタ25を有する。電子源22の形成方法
は公知であるので、ここではその説明を省略する。
As shown in FIG. 3, the electron source 22 includes a conical emitter (also referred to as an emitter tip) 25 electrically integrated with the cathode electrode 23, and a gate electrode 26 having an opening 26a for exposing the emitter 25. , And emitter 2
5 is formed of an insulating layer 24 for forming a void around the gate electrode 5 and maintaining insulation from the gate electrode 26, and actually has several hundred or more emitters 25. Since a method for forming the electron source 22 is known, the description thereof is omitted here.

【0024】エミッタ25とゲート電極26との間に所
定の電圧を印加すると、エミッタ25の先端部で電界放
出が生じる。したがって、例えばライン順次形式でカソ
ード電極23とゲート電極26とを選択し、特定の電子
源22から電子ビームを射出させることにより、電子源
22と対向する蛍光膜12を選択的に発光させることが
できる。FED1では、マトリクス表示の1画素は、カ
ソード電極23の延長方向に並ぶ3色の単位発光領域か
らなり、画素の表示色に応じて発光時間制御などによる
各色の階調表示が行われる。
When a predetermined voltage is applied between the emitter 25 and the gate electrode 26, field emission occurs at the tip of the emitter 25. Therefore, for example, by selecting the cathode electrode 23 and the gate electrode 26 in a line-sequential manner and emitting an electron beam from a specific electron source 22, it is possible to selectively cause the fluorescent film 12 facing the electron source 22 to emit light. it can. In the FED 1, one pixel of the matrix display is composed of unit light emission areas of three colors arranged in the extension direction of the cathode electrode 23, and gradation display of each color is performed by light emission time control or the like according to the display color of the pixel.

【0025】なお、カソード電極23、ゲート電極2
6、及びアノード電極は画面表示領域IAからパネル端
部まで導出され、これら電極を外部の回路と接続するた
めに、一方のパネルの電極導出部が他方のパネルに対し
て張り出すように、前面側及び背面側のパネルサイズと
重ね合わせ位置とが選定されている。
The cathode electrode 23 and the gate electrode 2
6, and the anode electrodes are led out from the screen display area IA to the edge of the panel, and in order to connect these electrodes to an external circuit, the electrode lead-out portions of one panel are extended so as to protrude from the other panel. The side and back side panel sizes and the overlapping position are selected.

【0026】さて、図1及び図2のように、FED1に
おいては、前面側パネル10の各蛍光膜12の間に、画
面表示領域IAの全域にわたって均等に、帯状の蒸発型
ゲッタ(フラッシュゲッタ)19が設けられている。
As shown in FIGS. 1 and 2, in the FED 1, a strip-shaped evaporable getter (flash getter) is uniformly provided between the fluorescent films 12 of the front panel 10 over the entire screen display area IA. 19 are provided.

【0027】蒸発型ゲッタ19は、例えばBaAl4
末を原料とし、被着面を部分的に覆うマスク蒸着法によ
って形成したバリウム薄膜であり、厚さは真空間隙寸法
と比べて十分に小さい1000Å程度である。
The evaporable getter 19 is, for example, a barium thin film formed by a mask vapor deposition method using BaAl 4 powder as a raw material and partially covering the adherend surface, and has a thickness of about 1000 ° which is sufficiently smaller than the vacuum gap dimension. It is.

【0028】蒸発型ゲッタ19によって、画面表示領域
IA内でのガス放出に対する迅速なゲッタリングが行わ
れる。その結果、FED1では、ガス拡散が局所化され
て内部の高真空状態が維持され、特にアーク放電を招く
大量のガス放出があってもアークが拡がらず、エミッタ
25の破損が最小限に抑えられる。
By the evaporable getter 19, quick gettering for gas release in the screen display area IA is performed. As a result, in the FED 1, the gas diffusion is localized, and a high vacuum state inside is maintained. In particular, even if a large amount of gas is discharged, which causes an arc discharge, the arc does not spread, and damage to the emitter 25 is minimized. Can be

【0029】以上の構成のFED1の製造に際しては、
ガラス板11上に、蛍光体12、封着用の低融点ガラ
ス、及びビーズスペーサをスクリーン印刷などによって
適当な順序で設けた後、真空中で表面浄化処理を施す。
表面浄化処理としては、ベーキング、電子照射、イオン
照射、紫外線照射、プラズマ処理などがある。また、水
素雰囲気中でのベーキングを加えてもよい。
In manufacturing the FED 1 having the above structure,
After a phosphor 12, a low-melting glass for sealing, and bead spacers are provided in a suitable order on a glass plate 11 by screen printing or the like, a surface cleaning treatment is performed in a vacuum.
Examples of the surface cleaning treatment include baking, electron irradiation, ion irradiation, ultraviolet irradiation, and plasma treatment. Further, baking in a hydrogen atmosphere may be performed.

【0030】表面浄化処理に続いて、真空を保持した状
態又は水素雰囲気から大気に暴露することなく処理環境
を真空にした状態で、蒸発型ゲッタ19を蒸着する。そ
して、蒸着後も真空状態を保持する。
Following the surface cleaning treatment, the evaporable getter 19 is deposited in a state where the vacuum is maintained or the processing environment is evacuated without exposing the atmosphere from a hydrogen atmosphere to the atmosphere. Then, the vacuum state is maintained after the vapor deposition.

【0031】一方、背面側パネル20についても、ガラ
ス21上に電子源22を含む電極マトリクスを設けた
後、前面側パネル10と同様に表面浄化処理を施す。た
だし、上述の各処理に加えて、真空中で電子源22を作
動させるエージングを行う。そして、エージング後も真
空状態を保持する。
On the other hand, also on the rear panel 20, after the electrode matrix including the electron source 22 is provided on the glass 21, the surface cleaning treatment is performed similarly to the front panel 10. However, in addition to the above-described processes, aging for operating the electron source 22 in a vacuum is performed. Then, the vacuum state is maintained even after aging.

【0032】その後、真空状態に保たれた両側のパネル
10,20を、使用時の内部間隙の真空度である10-7
〜10-8Torrの真空環境下に配置し、ホットプレー
ト加熱などにより周囲を封着して対向間隙を密閉する。
これにより、FED1が完成する。
Thereafter, the panels 10 and 20 on both sides kept in a vacuum state are replaced with 10 -7, which is the degree of vacuum of the internal gap during use.
It is placed in a vacuum environment of 10 to 10 -8 Torr, and the periphery is sealed by heating with a hot plate or the like to seal the facing gap.
Thus, the FED 1 is completed.

【0033】このように、表面浄化処理からゲッタ蒸着
を経て封着に至る一連の処理を実質的に真空中で連続的
に行うことにより、蒸発型ゲッタ19が長期にわたって
有効に機能する清浄な真空間隙30を形成することがで
きる。
As described above, a series of processes from the surface cleaning process to the sealing through the getter vapor deposition are performed substantially continuously in a vacuum, so that the evaporable getter 19 can function effectively for a long time in a clean vacuum. The gap 30 can be formed.

【0034】なお、FED1の製造には、各段階の処理
に適した複数の真空室とマニピュレータを含む搬送手段
とを備え、各真空室がロードロック機構で仕切られた製
造設備が好適である。
For manufacturing the FED 1, it is preferable to use a manufacturing facility having a plurality of vacuum chambers suitable for each stage of processing and transport means including a manipulator, and each vacuum chamber is partitioned by a load lock mechanism.

【0035】図4は第2実施例のFED2の構成を模式
的に示す平面図である。図4において、図1〜図3に対
応する構成要素には同一の符号を付してある。以下の図
においても同様である。
FIG. 4 is a plan view schematically showing the structure of the FED 2 of the second embodiment. In FIG. 4, the components corresponding to FIGS. 1 to 3 are denoted by the same reference numerals. The same applies to the following figures.

【0036】FED2の基本構成は、上述のFED1と
同一である。ただし、FED2では、画面表示領域IA
内の前面側及び背面側の両方に蒸発型ゲッタ19,19
Bが設けられている。
The basic structure of the FED 2 is the same as that of the FED 1 described above. However, in the FED2, the screen display area IA
The evaporable getters 19, 19 are provided on both the front side and the back side of the inside.
B is provided.

【0037】すなわち、図4(A)のように、前面側パ
ネル10には、各蛍光膜12の間に帯状の蒸発型ゲッタ
19が設けられており、背面側パネル20には、隣接す
る2×2個の電子源22の中心に四角形状の蒸発型ゲッ
タ19Bが設けられている。
That is, as shown in FIG. 4A, a strip-shaped evaporable getter 19 is provided between the phosphor films 12 on the front panel 10, and the adjacent two getters are provided on the rear panel 20. At the center of the two electron sources 22, a rectangular evaporable getter 19B is provided.

【0038】図5は第3実施例のFED3の要部の構造
を示す斜視図である。FED3は、上述のFED2と同
様に背面側パネル20に、各電子源22を四隅から囲む
ように、四角形状の蒸発型ゲッタ19Cが設けられてい
る。ただし、FED3では、絶縁層24の表層部に10
μm程度の深さの四角形状の窪み24aが形成され、そ
の窪み24aの底部に蒸発型ゲッタ19Cが設けられて
いる。
FIG. 5 is a perspective view showing the structure of the main part of the FED 3 of the third embodiment. The FED 3 is provided with a rectangular evaporable getter 19C on the back panel 20 so as to surround each electron source 22 from four corners, similarly to the FED 2 described above. However, in the case of FED3, 10
A square depression 24a having a depth of about μm is formed, and an evaporable getter 19C is provided at the bottom of the depression 24a.

【0039】これにより、窪み24aの近辺の電子源2
2でガス放出によるアーク放電が生じた場合には、窪み
24aの中が周囲と比べて高真空になるため、その真空
度勾配によりガスが窪み24aへ流れ込み、他の電子源
22へのアーク放電の拡がりが抑えられる。
Thus, the electron source 2 near the depression 24a
When the arc discharge occurs due to the gas discharge in step 2, the inside of the depression 24a is higher in vacuum than the surroundings, so that the gas flows into the depression 24a due to the degree of vacuum gradient, and the arc discharge to the other electron source 22 occurs. Is prevented from spreading.

【0040】図6は第4実施例のFED4の内部構造を
示す斜視図である。FED4は、前面側パネル10の各
蛍光膜12の間に平面視形状が直線状の隔壁51を有
し、背面側パネル20に各電子源22を囲む平面視形状
が格子状の隔壁52を有している。これら隔壁51,5
2によって、真空間隙30が単位発光領域毎に等間隔に
区画され、クロストークのない(発光にじみのない)高
精細な表示が可能となる。
FIG. 6 is a perspective view showing the internal structure of the FED 4 of the fourth embodiment. The FED 4 has a partition wall 51 having a linear shape in plan view between the phosphor films 12 of the front panel 10, and a partition wall 52 having a lattice shape in plan view surrounding each electron source 22 on the rear panel 20. are doing. These partition walls 51 and 5
2, the vacuum gap 30 is partitioned at equal intervals for each unit light emitting region, and high-definition display without crosstalk (without light emission bleeding) becomes possible.

【0041】そして、FED4では、隔壁51の側面を
被覆するように蒸発型ゲッタ19Dが設けられ、隔壁5
2の側面を被覆するように蒸発型ゲッタ19Eが設けら
れている。これら蒸発型ゲッタ19D,19Eは、蒸着
に際して蒸発源に対してパネル10,20とマスクとを
斜め方向の位置に配置することにより容易に形成するこ
とができる。
In the FED 4, the evaporable getter 19D is provided so as to cover the side surface of the partition 51, and the partition 5
An evaporable getter 19E is provided so as to cover the side surface of the second evaporator. These evaporable getters 19D and 19E can be easily formed by arranging the panels 10, 20 and the mask at oblique positions with respect to the evaporation source during vapor deposition.

【0042】上述の実施例によれば、厚さ寸法に係る配
置スペースの制約がなく、吸着面積を大幅に増大するこ
とができる。このため、従来のように画面表示領域IA
を囲む深い溝を設けてバルクゲッタを埋め込む必要がな
くなり、画面表示領域IAからパネル端部への電極の引
出しが容易になる。
According to the above-described embodiment, there is no restriction on the arrangement space related to the thickness dimension, and the suction area can be greatly increased. For this reason, the screen display area IA is
It is not necessary to embed a bulk getter by providing a deep groove surrounding the panel, and it is easy to draw out the electrode from the screen display area IA to the end of the panel.

【0043】上述の実施例において、前面側パネル10
についても、ガラス板11のエッチングなどにより帯状
の窪み(溝)を設け、その中に蒸発型ゲッタ19を設け
てもよい。また、蒸発型ゲッタ19,19B〜Eの形
状、配置位置は図示の例に限定されない。例えば、前面
側パネル10において、蛍光膜12を単位発光領域毎に
分割配置し、蛍光膜12を除いて内面を覆うように蒸発
型ゲッタ19を設けてもよい。
In the above embodiment, the front panel 10
Also, a strip-shaped depression (groove) may be provided by etching the glass plate 11 or the like, and the evaporable getter 19 may be provided therein. Further, the shapes and arrangement positions of the evaporable getters 19 and 19B to E are not limited to the illustrated example. For example, in the front panel 10, the fluorescent film 12 may be divided and arranged for each unit light emitting region, and the evaporable getter 19 may be provided so as to cover the inner surface except for the fluorescent film 12.

【0044】上述の実施例において、パネル封着を低融
点ガラスによらず、メタルシールや陽極接合などの他の
方法によって行うこともできる。各部の材質、形状、大
きさ、配置関係などは用途に応じて適宜選定すればよ
い。背面側パネル20の基体としてシリコン板を用いる
場合には、不純物拡散によってカソード電極23となる
導電層を形成し、その後にシリコンのパターンエッチン
グにより円錐状のエミッタ25を形成することができ
る。
In the above-described embodiment, the panel sealing can be performed by another method such as metal sealing or anodic bonding, instead of using the low melting point glass. The material, shape, size, arrangement relationship, and the like of each part may be appropriately selected according to the application. When a silicon plate is used as the base of the rear panel 20, a conductive layer serving as the cathode electrode 23 is formed by impurity diffusion, and then the conical emitter 25 can be formed by pattern etching of silicon.

【0045】上述の実施例において、エミッタ25の電
子放出面に蒸発型ゲッタを設ければ、ガスの離脱がなく
なって吸着のみとなることから、ガスの着脱に起因する
電界放出のノイズが低減され、アーク放電の誘発要因
(トリガ)も少なくなり、デバイス性能の向上を図るこ
とができる。
In the above-described embodiment, if an evaporative getter is provided on the electron emission surface of the emitter 25, gas is not released and only adsorption is performed, so that field emission noise due to gas attachment / detachment is reduced. In addition, the number of triggers (triggers) of arc discharge is reduced, and the device performance can be improved.

【0046】[0046]

【発明の効果】請求項1又は請求項の発明によれば、
使用中にガス放出の起こり易い画面表示領域の中にゲッ
タが配置されるので、ガス拡散が可及的に抑えられて高
真空状態が維持され、表示を安定化することができる。
According to the first or second aspect of the present invention,
Since the getter is arranged in the screen display area where gas emission is likely to occur during use, gas diffusion is suppressed as much as possible, a high vacuum state is maintained, and the display can be stabilized.

【0047】[0047]

【図面の簡単な説明】[Brief description of the drawings]

【図1】第1実施例のFEDの構成を示す断面図であ
る。
FIG. 1 is a cross-sectional view illustrating a configuration of an FED according to a first embodiment.

【図2】FEDの内部構造を示す部分斜視図である。FIG. 2 is a partial perspective view showing the internal structure of the FED.

【図3】電子源の構造の一例を示す図である。FIG. 3 is a diagram showing an example of the structure of an electron source.

【図4】第2実施例のFEDの構成を模式的に示す平面
図である。
FIG. 4 is a plan view schematically showing a configuration of an FED according to a second embodiment.

【図5】第3実施例のFEDの要部の構造を示す斜視図
である。
FIG. 5 is a perspective view illustrating a structure of a main part of an FED according to a third embodiment.

【図6】第4実施例のFEDの内部構造を示す斜視図で
ある。
FIG. 6 is a perspective view showing the internal structure of an FED according to a fourth embodiment.

【符号の説明】[Explanation of symbols]

1,2,3,4 FED(フラット形表示装置) 12 蛍光膜 10 前面側パネル 20 背面側パネル 25 エミッタ(電界放出型陰極) 30 間隙(真空間隙) IA 画面表示領域 19 19B〜E 蒸発型ゲッタ 24a 窪み 51,52 隔壁 1, 2, 3, 4 FED (flat display device) 12 phosphor film 10 front panel 20 rear panel 25 emitter (field emission cathode) 30 gap (vacuum gap) IA screen display area 19 19B-E evaporation type getter 24a depression 51, 52 partition

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平2−100242(JP,A) 特開 平4−289640(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01J 31/12 H01J 29/94 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-100242 (JP, A) JP-A-4-289640 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01J 31/12 H01J 29/94

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】蛍光膜を有した前面側のパネルと、前記蛍
光膜を選択的に励起する画面表示のための多数の電界放
出型陰極を有した背面側のパネルとが、真空間隙を介し
て対向する構造のフラット形表示装置であって、 前記電界放出型陰極が配置された領域である画面表示領
域内に、前記真空間隙の寸法を局所的に増大させる窪み
を有し、前記窪みの底部に蒸発型ゲッタ材料を蒸発させ
て被着させたゲッタが設けられてなることを特徴とする
フラット形表示装置。
1. A front panel having a fluorescent film and a rear panel having a plurality of field emission cathodes for screen display for selectively exciting the fluorescent film are interposed through a vacuum gap. A flat display device having a structure in which the size of the vacuum gap is locally increased in a screen display area in which the field emission cathode is arranged.
Having an evaporable getter material at the bottom of the depression.
A flat display device, comprising a getter attached to the display device.
【請求項2】蛍光膜を有した前面側のパネルと、前記蛍
光膜を選択的に励起する画面表示のための多数の電界放
出型陰極を有した背面側のパネルとが、真空間隙を介し
て対向する構造のフラット形表示装置であって、 前記画面表示領域内に前記真空間隙を区画する隔壁を備
え、前記隔壁の側面に蒸発型ゲッタ材料を蒸発させて被
着させたゲッタが設けられてなることを特徴とするフラ
ット形表示装置。
2. A front panel having a fluorescent film and said fluorescent panel.
Multiple field emission for screen display to selectively excite optical film
The panel on the back side with the output cathode is connected via a vacuum gap.
A flat display device having a structure opposing to the first display device, wherein a partition partitioning the vacuum gap is provided in the screen display area.
Then, the evaporation type getter material is evaporated on the side surface of the partition wall to be covered.
Characterized by being provided with a getter
Bit-shaped display device.
JP15579694A 1994-07-07 1994-07-07 Flat display device Expired - Fee Related JP3241935B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15579694A JP3241935B2 (en) 1994-07-07 1994-07-07 Flat display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15579694A JP3241935B2 (en) 1994-07-07 1994-07-07 Flat display device

Publications (2)

Publication Number Publication Date
JPH0822785A JPH0822785A (en) 1996-01-23
JP3241935B2 true JP3241935B2 (en) 2001-12-25

Family

ID=15613632

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15579694A Expired - Fee Related JP3241935B2 (en) 1994-07-07 1994-07-07 Flat display device

Country Status (1)

Country Link
JP (1) JP3241935B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5894193A (en) * 1997-03-05 1999-04-13 Motorola Inc. Field emission display with getter frame and spacer-frame assembly
US6149483A (en) * 1998-07-30 2000-11-21 Candescent Technologies Corporation Cleaning of components of flat panel display
JP2000057940A (en) 1998-08-10 2000-02-25 Yamaha Corp Electric-field-emission-type element and its manufacture
WO2000052728A1 (en) * 1999-03-04 2000-09-08 Canon Kabushiki Kaisha Air-tight device, electron beam device, and image forming device
WO2000060634A1 (en) * 1999-03-31 2000-10-12 Kabushiki Kaisha Toshiba Method for manufacturing flat image display and flat image display
JP2000315458A (en) * 1999-04-28 2000-11-14 Toshiba Corp Method and equipment for manufacturing flat-type image display device
JP3754859B2 (en) 2000-02-16 2006-03-15 キヤノン株式会社 Manufacturing method of image display device
KR100752863B1 (en) * 2001-01-03 2007-08-29 엘지전자 주식회사 FED and manufacturing method thereof
JP3634805B2 (en) 2001-02-27 2005-03-30 キヤノン株式会社 Manufacturing method of image forming apparatus
JP4574081B2 (en) * 2001-08-09 2010-11-04 キヤノン株式会社 Manufacturing method of image display device
KR100446623B1 (en) * 2002-01-30 2004-09-04 삼성에스디아이 주식회사 Field emission display and manufacturing method thereof
JP2008034226A (en) * 2006-07-28 2008-02-14 Futaba Corp Self-luminous display device
JP2009093951A (en) * 2007-10-10 2009-04-30 Ulvac Japan Ltd Manufacturing method for sealed panel and manufacturing method for plasma display panel using the same

Also Published As

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