JP3178459B2 - Operation clock frequency switching circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for generating a low-frequency operating clock frequency by dividing a basic clock signal as necessary in a microcomputer.

[0002]

2. Description of the Related Art In recent years, portable devices incorporating a microcomputer have become widespread. Since these devices generally use a battery as a power source, it is necessary to replace or charge the battery after a certain period of operation. For this reason, in order to extend the operation time of the device, a technique for reducing the power consumption of the microcomputer is being developed.

The power consumption of a microcomputer is proportional to the operating clock frequency of the microcomputer. Therefore, power consumption can be reduced by dynamically switching and lowering the operating clock frequency when the processing performance of the microcomputer is not required.

[0004] An example of the prior art in which such an operation clock frequency is switched to lower is disclosed in Japanese Patent Application Laid-Open No. 3-257515. According to the technology disclosed in this publication, a divide-by-2 clock signal and a divide-by-4 clock signal are generated from a fundamental clock signal of a fundamental frequency, and any one of the basic clock signal and the divided clock signal is selected. A signal is selected and output as an operation clock signal.

[0005]

The prior art described above is
Switching the operating clock frequency as needed to reduce
It was excellent in that power consumption could be reduced. However, in the conventional example, even when the basic clock signal is required as the operation clock signal, the divide-by-2 clock signal and the divide-by-4 clock signal are generated. That is, since a clock signal having an unnecessary cycle is always generated, there is room for technical improvement.

In general, when the operation clock frequency is switched, an unintended signal having a short pulse waveform may be generated. That is, unnecessary clock disturbance may be caused. When such a signal is generated, for example, the delay between the latches inside the circuit of the microcomputer may not be in time for the clock cycle, and the microcomputer may malfunction.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and generates a low-frequency operation clock frequency of a microcomputer as necessary while avoiding the occurrence of a malfunction of the microcomputer. It is an object of the present invention to provide a technology capable of reducing the number of times.

[0008]

In order to achieve the above object, according to the operation clock frequency switching circuit according to the first aspect of the present invention, the frequency dividing number is switched according to the designated frequency dividing number of the selection signal. An operation clock frequency switching circuit for generating an operation clock signal obtained by dividing the basic clock signal, comprising a plurality of output delay flip-flops (hereinafter referred to as “output delay flip-flops”) synchronized with the basic clock signal and connected in series with each other. DF
F ". ) And a decoding device that generates a plurality of decode signals in which only one signal corresponding to the designated frequency division number is activated and a signal corresponding to the other frequency division number is inactive, A latch circuit that latches in synchronization with an output signal of one of the output DFFs to generate a latch output signal, and one of the output DFFs based on an active signal among the latch output signals. A selection circuit for selecting and outputting the output of the DFF, and an inversion circuit for generating an inverted signal of the output of the selection circuit and inputting the inverted signal to the first-stage output DFF, and the output signal of the final-stage output DFF Is taken out as an operation clock signal.

As described above, according to the operation clock frequency switching circuit of the present invention, the latch circuit constantly latches the signal for selecting the frequency division number in synchronization with the signal having the longest cycle. For this reason, the frequency division number of the operation clock signal can be switched without causing unnecessary disturbance of the waveform of the operation clock signal. For this reason, it is possible to suppress occurrence of a malfunction of the circuit due to unnecessary transition of the operation clock waveform.

Further, according to the present invention, since only the specified frequency division number specified by the selection signal is selected by the selection circuit, it is possible to generate only the operation clock signal of the selected frequency division number.
Therefore, an operation clock signal having an unnecessary frequency division number is not always generated. Then, the frequency of division is dynamically switched to the required frequency of division by the selection signal and is generated only when necessary, so that the power consumption of the circuit can be reduced.

Thus, according to the present invention, it is possible to reduce the power consumption by generating a low-frequency operating clock frequency of the microcomputer as necessary while avoiding the occurrence of a malfunction of the microcomputer. .

According to the second aspect of the present invention, the latch circuit is constituted by a plurality of latch delay flip-flops synchronized with the operation clock signal and individually corresponding to each frequency division number. With such a configuration, it is possible to individually latch the decode signals generated by the decoding device and corresponding to each frequency division number.

Further, according to the third aspect of the present invention, the selection circuit is the output delay of the number of stages equal to the logarithm base 2 of the frequency division number corresponding to the active signal among the outputs of the latch circuit. The configuration is such that the output of the flip-flop is selected.

With this configuration, when the frequency division number is N, the output DF of the number of stages given by log ₂ N
The output of F can be selected. That is, the dividing number N
In the case of = 2, the output of the output DFF of the log ₂ 2 = first stage is selected. When the frequency division number N = 4, lo
selects the output of g ₂ 4 = 2-stage output DFF. Furthermore, in the case of division number N = 8 selects the output of the output DFF of log ₂ 8 = 3 stage.

According to the fourth aspect of the present invention, the selection circuit includes a plurality of A inputs to which one latch output signal and one output of one latch delay flip-flop are input.
An ND circuit and an OR to which the outputs of these AND circuits are input
And a circuit. With such a configuration,
In the selection circuit, an active signal (signal value is “1”) corresponding to the designated frequency division number is easily selected from the latch output signals corresponding to each frequency division number. be able to.

According to a fifth aspect of the present invention, there is provided a configuration including an operation clock selection unit for selecting an output of any one of the output delay flip-flops and inputting the output to the latch circuit. Thus, if the operation clock selection unit is provided,
From among the outputs of the output DFFs, the output of the output DFF corresponding to the designated frequency division number can be easily selected and taken out as an operation clock signal.

By the way, the designated frequency division number is sequentially (for example,
In the case of changing discretely without changing (like 2 → 4 → 8 or 8 → 4 → 2) (for example, changing like 2 → 8 or 8 → 2), Depending on the designated frequency division number before and after the change, the waveform of the operation clock signal may be disturbed.

Therefore, according to the invention described in claim 6, the decoding device includes a decoder, a comparator, a shifter, and a register. The decoder receives a selection signal, outputs a decoding signal, and outputs the decoding signal. The signal is compared with the output of the shifter, and when the value of the decode signal is greater than the output of the shifter, the decode signal is activated. When the decode signal is active, the shifter sequentially outputs the decode signal. And the register latches the shifted decoded signal in synchronization with the basic clock signal.

As described above, the comparator compares the decode signal with the output of the shifter, and when the decode signal is active (when the value of the signal is "1"), the decode signal is converted by the shifter. Shift sequentially. In this way, even if the new designated frequency division number is larger than the current designated frequency division number, the decoded signal is sequentially shifted one bit at a time, and finally the designated frequency division number. Can be matched with Therefore, even when the designated frequency division number is changed step by step, the designated frequency division number can be sequentially changed in the switching circuit. As a result, it is possible to suppress the occurrence of disturbance in the waveform of the operation clock signal.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] First, a first embodiment of an operation clock frequency switching circuit of the present invention will be described with reference to FIG.

FIG. 1 is a block circuit diagram for explaining a configuration of an operation clock frequency switching circuit (also referred to as a “switching circuit”) of the first embodiment. In this embodiment,
An example in which the frequency division number is switched according to the frequency division number specified by the selection signal S to generate the operation clock signal CO obtained by dividing the basic clock signal CL will be described. As shown in FIG. 1, this switching circuit includes a three-stage output delay DFF1.
0, 12, and 14, a decoding device 16, a latch circuit 18, a selection circuit 20, and an inversion circuit 22.

The decoding device 16 is supplied with a 3-bit selection signal S. The decoding device 16 sets only one signal corresponding to one of the designated frequency division numbers of “2”, “4” or “8” designated by the selection signal S to be active (signal value is “1”), Three decode signals a1 to a3 are generated in which signals corresponding to other frequency division numbers are inactive (signal value is “0”). These decode signals a1 to a3
Are input to the latch circuit 18, respectively.

The latch circuit 18 outputs the decode signals a1 to a1.
a3 is latched in synchronization with the operation clock signal d3 (CO) output from the output DFF 14 at the final stage to generate a latch output signal. For this purpose, as shown in FIG. 2, the latch circuit 18 of the present embodiment includes three latch delay flip-flops (hereinafter, referred to as “latch DFFs”) synchronized with the operation clock signal and individually corresponding to each frequency division number. 181 to 183.

That is, the first latch DFF 181 receives the operation clock signal d from the final stage output DFF 14.
3 and the decode signal a1 from the decoding device 16. And this latch DFF
181 latches the decode signal a1 in synchronization with the operation clock signal d3 and outputs the first latch output signal b1 to the selection circuit 20.

The second latch DFF 182 also has
Similarly to the first latch DFF 181, the operation clock signal d3 is input from the output DFF 14 of the last stage, and the decode signal a2 is input from the decoding device 16. Then, the latch DFF 182 latches the decode signal a2 in synchronization with the operation clock signal d3, and outputs the second latch output signal b2 to the selection circuit 20.

The third latch DFF 183 also has
Similarly to the first and second latch DFFs 181 and 182, the operation clock signal d
3 as well as a decode signal a3 from the decoding device 16. And this latch DFF
183 latches the decode signal a3 in synchronization with the operation clock signal d3 and outputs the third latch output signal b3 to the selection circuit 20.

As described above, in the latch circuit 18,
The decoded signal is constantly latched in synchronization with the output d3 of the output DFF 14 at the last stage, which is the signal having the longest cycle. For this reason, the frequency division number of the operation clock signal can be switched without causing unnecessary disturbance of the waveform of the operation clock signal.

The selection circuit 20 outputs the latch output signal b
The output of one of the output DFFs is selected and output based on the active signal among 1 to b3. For this purpose, the selection circuit 20 of the present embodiment is
As shown in the figure, the circuit is composed of three AND circuits 201 to 203 and one OR circuit 204. Each of the AND circuits 203 to 201 has a corresponding one of the latch DFFs 18.
Outputs b1 to b3 from 1 to 183 are input, and outputs d1 to d from the output DFF are input.

That is, the AND circuit 201 has the output of the latch DFF 183 and the output DFF of the third stage.
Fourteen outputs are input. Similarly, the output of the second-stage output DFF 12 is input to the AND circuit 202 together with the output of the latch DFF 182. Furthermore, AN
Similarly, the output of the first-stage output DFF 10 is input to the D circuit 201 together with the output of the latch DFF 181. The output of each of the AND circuits 201 to 203 is O
Input to the R circuit 204.

With such a configuration, in the selection circuit 20, the output delay flip-flop of the number of stages equal to the logarithmic value with the base 2 of the frequency division number corresponding to the active signal among the outputs b1 to b3 of the latch circuit is provided. Output can be selected. That is, when the frequency division number is N, log
The output of stages th output DFF given by ₂ N can be selected. For example, when the dividing number N = 2, l
The output of og ₂ 2 = 1 stage output DFF10 is selected. In the case of frequency division number N = 4, the output of the log ₂ 4 = 2-stage output DFF12 is selected. Furthermore, in the case of division number N = 8 is, log ₂ 8 = 3-stage output D
The output of the FF 14 is selected.

As a result, in the selection circuit 10, from among the latch output signals b1 to b3 corresponding to each frequency division number, an active signal corresponding to the specified frequency division number (the signal value is "1"). The signal can be easily selected. Therefore, the selection circuit 20 can select only the specified frequency division number specified by the selection signal S. Therefore, it is possible to generate only the operation clock signal of the selected division number. As a result, an operation clock signal having an unnecessary frequency division number is not always generated. Then, the frequency of division is dynamically switched to the required frequency of division by the selection signal and is generated only when necessary, so that the power consumption of the circuit can be reduced.

Further, the output C1 of the OR circuit 204 is input to an inverting circuit (NOT circuit) 22. The inverted output C2 output from the inverting circuit 22 is the output DFF1 of the first stage.
Input to 0. The output DFFs 10, 12, and 14 are
Each is synchronized with the basic clock signal CL and connected in series with each other. Then, the output of the output DFF 14 at the final stage is extracted as the operation clock signal CO.

Next, an example of the operation of the operation clock frequency switching circuit of the first embodiment will be described with reference to FIG.
FIG. 3 is a timing chart for explaining an operation example of the first embodiment. In this operation example, a case will be described in which the number of divisions designated by the selection signal S is switched from “2” to “4”.

The 3-bit selection signal S is initially (for example,
At the time T1), the frequency division number is “2” by the binary data “001”. In each of the decoded signals decoded by the decoding device 16, the value of the decoded signal a1 corresponding to the first bit from the lower bit of the bit string of the binary data is “1”, which is active. The values of the decode signals a2 and a3 corresponding to the second and third bits from the lower order are respectively "0".

At the time T1, the operation clock signal CO has a period obtained by dividing the clock signal by two, and the output signal C1 of the selection circuit 20 and its inverted signal C1 are output.
The cycle of 2 is also halved. Therefore, each output D
The outputs d1 to d3 of the FFs 10, 12, and 14 are also divided by two. At this time, the value of the signal b1 latching the decode signal a1 is also "1", and the signal b2 latching the decode signals a2 and a3, respectively.
And the value of b3 is “0”.

When the binary data of the selection signal S is switched to "010" indicating the frequency division number "4", the value of each decode signal also changes. That is, the value of the decode signal a1 changes from “1” to “0”, while the value of the decode signal a2 changes from “0” to “1”. Further, the value of the decode signal a3 remains “0”.

Subsequently, at time T3 immediately after the binary data of the selection signal S is changed, the decoded signals a1 to a3 after the change are latched by the latch circuit 18 in synchronization with the rise of the operation clock signal CO. You. And at time T3
, Latch output signals b1 to b3 are output. Note that the cycle of the operation clock signal CO at the time T3 remains at 二.

When the changed latch output signals b1 to b3 are output, the selection circuit 20 outputs a second-stage output DF corresponding to the activated latch output signal b2.
The output d2 of F12 is selected and output as the output c1. The output d2 of the second-stage output DFF 12 is delayed by one cycle of the operation clock signal CO from the output d1 of the first-stage output DFF1. At time T3,
The operation clock signal CO has a cycle obtained by dividing the basic clock signal CL by two.

When the output d2 is selected at time T4, the output signal C1 of the selection circuit 20 and its inverted signal C1 are output.
2 also switches. Then, when the inverted signal C2 after the change is input to the first-stage output DFF 10, the cycle of the output d1 is switched to the cycle of the quarter of the basic clock signal CL. Then, the outputs d2 and d3 of the second and third output DFFs 12 and 14 are sequentially switched. as a result,
The cycle of the operation clock signal CO, which is the output of the output DFF 14 of the third stage, which is the last stage, is also switched to 四.

[Second Embodiment] Next, referring to FIG.
A second embodiment of the operation clock frequency switching circuit of the present invention will be described. FIG. 4 is a circuit diagram for explaining the configuration of the operation clock frequency switching circuit of the second embodiment.
As shown in FIG. 4, in the second embodiment, the configuration other than the decoding device 16a and the newly provided operation clock selection unit 24 is the same as that of the above-described first embodiment. Therefore, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

The output of any one of the output delay DFFs 10, 12, or 14 is selected by the operation clock selector 24,
Input to the latch circuit 18. As described above, if the operation clock selection unit 24 is provided, the output of the output DFF corresponding to the designated frequency division number can be easily selected from the outputs of the output DFFs and taken out as the operation clock signal. it can.

Here, a decoding device 16a according to the second embodiment will be described with reference to FIG. FIG. 5 is a block circuit diagram for explaining the configuration of the decoding device 16a according to the second embodiment. As shown in FIG. 5, the decoding device 16a includes a decoder 241, a comparator 242, and a shifter 24.
3 and a register 245.

The decoder 241 receives the selection signal S and outputs a decode signal f. The comparator 242 outputs the decoded signal f and the output of the shifter 243 to a
And b terminal. Then, the comparator 242 compares these signals. As a result of the comparison, when the value of the decode signal f is larger than the output of the shifter 242, the value of the decode signal f is set to “1” and activated.

Further, shifter 242 provides decode signal g
Are active, the decode signal g is sequentially shifted. The register 245 latches the shifted decode signal n in synchronization with the basic clock signal CL, and outputs the decode signals a1 to a3.

In this way, even when the new designated frequency indicated by the selection signal S is larger than the current designated frequency, the decoded signal is sequentially shifted one bit at a time. Finally, it can be made to coincide with the designated frequency division number. Therefore, even when the designated frequency division number is changed step by step, the designated frequency division number can be sequentially changed in the switching circuit. As a result, it is possible to suppress the occurrence of disturbance in the waveform of the operation clock signal.

In the embodiment described above, an example in which the present invention is configured under specific conditions has been described. However, the present invention can be variously modified. For example, in the above-described embodiment, an example has been described in which three types of frequency division numbers that can be selected are "2", "4", and "8". It is not limited to this. The type of frequency division number that can be selected can be a desired number depending on the number of stages of each of the latch delay flip-flop and the output delay flip-flop.

[0047]

As described in detail above, according to the operation clock frequency switching circuit of the present invention, in the latch circuit, the signal for selecting the frequency division number is constantly synchronized with the signal having the longest period. Latch. For this reason, the frequency division number of the operation clock signal can be switched without causing unnecessary disturbance of the waveform of the operation clock signal. For this reason, occurrence of a malfunction of the circuit can be suppressed.

Further, in the present invention, since only the specified frequency division number specified by the selection signal is selected by the selection circuit, only the operation clock signal of the selected frequency division number can be generated.
Therefore, an operation clock signal having an unnecessary frequency division number is not always generated. Then, according to the selection signal, the frequency division number is
Since the frequency is dynamically switched to the required frequency division number and generated only when necessary, the power consumption of the circuit can be reduced.

Therefore, according to the present invention, it is possible to reduce the power consumption by generating a low-frequency operation clock frequency of the microcomputer as required while avoiding the occurrence of a malfunction of the microcomputer.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically illustrating a configuration of an operation clock frequency switching circuit according to a first embodiment.

FIG. 2 is a block diagram illustrating a configuration of an operation clock frequency switching circuit according to the first embodiment.

FIG. 3 is a time chart illustrating an operation of the operation clock frequency switching circuit according to the first embodiment.

FIG. 4 is a block diagram illustrating a configuration of an operation clock frequency switching circuit according to a second embodiment.

FIG. 5 is a block diagram illustrating a configuration of a decoding device according to a second embodiment.

[Explanation of symbols]

 10, 12, 14 Output delay flip-flops 16, 16a Decoding device 18 Latch circuit 20 Selection circuit 24 Operation clock selection unit 181, 182, 183 Latch flip-flops 201, 202, 203 AND circuit 204 OR circuit 241 Decoder 242 Comparator 243 shifter 245 register

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 1/08 G06F 1/04

Claims (6)

(57) [Claims] 1. An operation clock frequency switching circuit for generating an operation clock signal obtained by dividing a basic clock signal by switching a frequency division number according to a designated frequency division number of a selection signal, wherein the operation clock frequency switching circuit synchronizes with the basic clock signal. And a plurality of output delay flip-flops connected in series with each other, and a plurality of delay flip-flops in which only one signal corresponding to the designated frequency division number is activated and signals corresponding to the other frequency division numbers are inactive. A decoding device that generates a decode signal; a latch circuit that latches each of the decode signals in synchronization with an output signal of one of the output delay flip-flops to generate a latch output signal; Select and output the output of one of the output delay flip-flops based on the active signal of A selection circuit, and an inversion circuit for generating an inverted signal of the output of the selection circuit and inputting the inverted signal to the first-stage output delay flip-flop. The output signal of the final-stage output delay flip-flop is An operation clock frequency switching circuit for extracting an operation clock signal as an operation clock signal. 2. The operation clock according to claim 1, wherein the latch circuit is constituted by a plurality of latch delay flip-flops synchronized with the operation clock signal and individually corresponding to the respective frequency division numbers. Frequency switching circuit. 3. The selection circuit selects the output of the output delay flip-flop of the number of stages equal to a logarithmic value with a base of 2 of a frequency division number corresponding to an active signal among outputs of the latch circuit. 3. The method according to claim 1, wherein
An operation clock frequency switching circuit as described in the above. 4. The selection circuit includes a plurality of AND circuits to which one of the latch output signals and an output of one of the latch delay flip-flops are input, and an OR to which the outputs of the AND circuits are input. 4. The operation clock frequency switching circuit according to claim 1, wherein the operation clock frequency switching circuit comprises a circuit. 5. An operation clock selector for selecting an output signal of any one of the output delay flip-flops and inputting the selected signal to the latch circuit.
5. The operation clock frequency switching circuit according to 2, 3, or 4. 6. The decoding device includes a decoder, a comparator, a shifter, and a register, wherein the decoder receives the selection signal and outputs the decode signal, and the comparator outputs the decode signal and the register. When the value of the decode signal is larger than the output of the register, the decode signal is activated. When the decode signal is active, the shifter sequentially outputs the decode signal. 6. The operating clock frequency switching circuit according to claim 5, wherein the register latches the shifted decode signal in synchronization with the basic clock signal.