JP2008109563A - Counter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a counter in which a delay time from a clock to a change in bits of a count value is reduced even when there are a number of bits of the count value, and power consumption is reduced. <P>SOLUTION: A clock gating control circuit 3 is interposed between a low-order digit counter 1 and a high-order digit counter 2. The low-order digit counter 1 is a ripple counter and performs up-counting of a clock CLK. When the count value of the low-order digit counter 1 becomes "7" and digits should be carried, the clock gating control circuit 3 passes the next clock CLK and supplies it to the high-order digit counter 2 as a clock CLKa. The high-order digit counter 2 is a synchronous counter and performs up-counting of the clock CLKa supplied in this way. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a counter used for pulse counting, timing, timing control, and the like.

As a form of the counter, there are a synchronous counter and a ripple counter. As is well known, the synchronization counter includes a plurality of flip-flops that store a plurality of bits representing the count value, and is configured so that each bit stored in each flip-flop is updated in synchronization with the same clock. Counter. On the other hand, in the ripple counter, only the least significant bit stored in the flip-flop at the first stage is directly updated by the clock, and each bit stored in each flip-flop at the second stage and thereafter is stored in each flip-flop at the previous stage. The counter is configured to be updated using the selected bit as a clock.
Special table 2003-519951 gazette

  The synchronous counter described above has a short delay time from the clock to the change timing of each bit, and there is little variation in the delay time between bits. Therefore, it is possible to increase the maximum clock frequency of the entire digital circuit using the synchronous counter, and it is advantageous in that the timing design of the digital circuit becomes easy. On the other hand, since the clock is supplied to all the flip-flops in the counter, there is a problem that the number of transistors that perform switching operation at the same frequency as the clock is large and the power consumption increases. On the other hand, the ripple counter is configured such that a clock (inversion of lower bits) is given to each flip-flop storing each bit only when each bit should be inverted, so that power consumption is low. Has the advantage. However, in the ripple counter, since all of the preceding flip-flops are interposed in the clock supply path to each flip-flop, the delay time from the change in the clock becomes longer as the higher-order bit is increased. For this reason, when the number of bits representing the count value is large, it is difficult to increase the maximum clock frequency of the entire digital circuit using the ripple counter, and the timing design of the digital circuit is also difficult. There is a problem of becoming.

  The present invention has been made in view of the circumstances described above, and even when the number of bits expressing the count value is large, the delay time from the clock to the change of each bit indicating the count value is small, and An object of the present invention is to provide a counter with reduced power consumption.

The present invention has a plurality of counters including a first-stage counter that counts clocks and a second-stage and subsequent counters that count the clock in response to the occurrence of carry or carry-down in a previous-stage counter, Provided is a counter characterized by connecting a clock gating control circuit that allows a clock to pass through the counter when a carry or a carry-down occurs in the counter in the preceding stage of the counter to the counter in the second stage or later of the counter To do.
According to this invention, the counters in the second and subsequent stages have carry or carry down in the previous stage, and the clock is supplied only when each count value needs to be updated, thus reducing power consumption. Is done. In addition, only the clock gating control circuit is interposed in the clock supply path to each counter in the second and subsequent stages, and no other counter is interposed, so the delay from the clock to the change timing of the output signal of each counter Time can be shortened.

Embodiments of the present invention will be described below with reference to the drawings.
<First Embodiment>
FIG. 1 is a circuit diagram showing a configuration of a counter according to a first embodiment of the present invention. In the illustrated example, the counter according to the present embodiment is a 6-bit up counter that is mounted on a certain semiconductor integrated circuit and performs up-counting of the count value expressed in 6 bits. This 6-bit up counter includes a lower digit counter 1 that counts up the lower 3 bits of the 6 bits indicating the count value, an upper digit counter 2 that counts up the upper 3 bits, a lower digit counter 1 and an upper digit. The clock gating control circuit 3 is interposed between the counters 2.

  In the present embodiment, the lower-order counter 1 that is the first-stage counter is a ripple counter that counts the clock CLK, and includes flip-flops 11 to 13 that store the lower 3 bits of the count value, inverters 14 to 16, and a selector 17. And 18 and an AND gate 19.

  Here, in the flip-flops 11 to 13, the output signals of the respective low active data output terminals are inverted by the inverters 14 to 16 and supplied to the respective low active data input terminals. Each time the clock applied to the terminal rises, a toggle operation is performed to invert the level of each output signal. The output signals of the inverters 14 to 16 are supplied to a circuit (not shown) using the count value as output signals Q0 to Q2 indicating the lower 3 bits of the 6-bit expression count value.

  The clock CLK is directly applied to the clock input terminal of the flip-flop 11 of the lower digit counter 1 from a clock generation source (not shown). On the other hand, the output terminals of the selectors 17 and 18 are connected to the clock input terminals of the flip-flops 12 and 13, and the signals selected by the selectors 17 and 18 are supplied.

  The selectors 17 and 18 are supplied with a test signal TEST as a selection signal. The test signal TEST is a signal whose level is switched in order to easily perform function confirmation during the function confirmation test or failure test of the semiconductor integrated circuit on which the counter according to the present embodiment is mounted. Sometimes it is fixed at L level. Selectors 17 and 18 select the output signals of the low active data output terminals of flip-flops 11 and 12 when test signal TEST is at the L level, and output signals of AND gate 19 when test signal TEST is at the H level. Select. The AND gate 19 outputs a logical product of the test signal TEST and the clock CLK. The AND gate 19 prevents the clock CLK from being transmitted to the selectors 17 and 18 when the test signal TEST is at the L level (other than the function confirmation test or the failure test) to reduce power consumption. It is provided.

  The high-order digit counter 2 that is the second-stage counter is a synchronous counter that counts the clock CLK in response to the occurrence of a carry in the low-order digit counter 1 that is the preceding-stage counter, and stores the high-order 3 bits of the count value. A 3-bit register 21 and a 3-bit full adder 22 that adds “+1” (001B) to the 3-bit data output from the 3-bit register 21 and supplies the 3-bit register 21 to the 3-bit register 21. Here, the clock CLKa is given to the 3-bit register 21 from the clock gating control circuit 3 when a carry occurs in the lower digit counter 1. In the upper digit counter 2, the output data of the 3-bit full adder 22 at that time (that is, data obtained by adding “+1” to the output data of the 3-bit register 21) to the 3-bit register 21 at the rising edge of the clock CLKa. It is written and the count value is incremented. Then, the 3-bit output signal in the 3-bit register 21 is supplied to a circuit (not shown) that uses the count value as the upper 3-bit output signals Q3 to Q5 of the 6-bit counter according to the present embodiment.

The clock gating control circuit 3 is a circuit that passes the clock CLK and supplies it to the 3-bit register 21 of the upper digit counter 2 only when a carry occurs in the lower digit counter 1 as the clock CLKa. The clock gating control circuit 3 includes a low active AND gate 31, a latch 32, and an AND gate 33. Here, in the low active AND gate 31, all the output signals of the low active data output terminals of the flip-flops 11 to 13 are at the L level, the count value of the lower digit counter 1 is “7”, and the next clock CLK When a carry from the lower digit counter 1 to the upper digit counter 2 is to be performed at the rising edge, the enable signal EN1 is set to H level. The latch 32 passes the enable signal EN1 as the enable signal EN2 when the clock CLK is at L level (through state), and holds the enable signal EN2 immediately before the clock CLK becomes H level (holding state). The AND gate 33 passes the clock CLK as the clock CLKa only when the enable signal EN2 is at the H level, and outputs an L level signal when the enable signal EN2 is at the L level.
The above is the details of the configuration of the counter according to the present embodiment.

  Next, the operation of this embodiment will be described. FIG. 2 is a time chart showing waveforms of respective parts of the counter when the test signal TEST is at the L level in the present embodiment. When test signal TEST is at L level, the output signal of AND gate 19 is at L level. The selector 17 selects the output signal of the low active data output terminal of the flip-flop 11 and supplies it to the clock input terminal of the flip-flop 12. The selector 18 selects the output signal of the low active data output terminal of the flip-flop 12. To the clock input terminal of the flip-flop 13. For this reason, when the flip-flop 11 toggles at the rising edge of the clock CLK, the flip-flop 12 toggles according to the rise of the output signal of the low active data output terminal of the flip-flop 11. Then, the flip-flop 13 performs a toggle operation in response to the output signal of the low active data output terminal of the flip-flop 12 rising. Thus, when the test signal TEST is at the L level, the flip-flops 11 to 13 operate as a ripple counter. Therefore, the count values indicated by the output signals Q0 to Q2 of the lower digit counter 1 are “0”, “1”, “2”,..., “7”, “0”,. The count value in the range of “0” to “7” is repeated.

  In the low active AND gate 31 in the clock gating control circuit 3, the count value of the lower digit counter 1 is “7”, that is, all the output signals of the low active data output terminals of the flip-flops 11 to 13 are at the L level. During the period, the enable signal EN1 is set to the H level, and the enable signal EN1 is set to the L level during the other periods.

  When the count value of the lower digit counter 1 is “7” and the enable signal EN1 is changed from the L level to the H level, and the clock CLK is subsequently changed to the L level, the latch 32 receives the H level enable signal EN1. The signal is passed and provided to the AND gate 33 as an enable signal EN2. Thereafter, when the clock CLK rises and the count value of the lower digit counter 1 changes from “7” to “0”, the latch 32 outputs the H level enable signal EN2 during the period from the rise of the clock CLK to the fall thereafter. Hold. For this reason, the clock CLK whose count value of the lower digit counter 1 is changed from “7” to “0” passes through the AND gate 33 and is supplied to the 3-bit register 21 of the upper digit counter 2 as the clock CLKa. The count value of the digit counter 2 (the count value indicated by the output signals Q3 to Q5) is counted up.

  FIG. 3 is a time chart showing waveforms of respective parts of the counter when the test signal TEST is at the H level (in the case of a function check test or a failure test) in this embodiment. In this case, the AND gate 19 passes the clock CLK. The selectors 17 and 18 select the clock CLK passing through the AND gate 19 and supply it to the clock input terminals of the flip-flops 12 and 13, respectively. Therefore, the flip-flops 11 to 13 toggle each time the clock CLK rises, and the level inversion of the output signals Q0 to Q2 occurs, and the count value of the lower digit counter 1 alternately repeats “0” and “7”. . Similarly to the case where the test signal TEST is at the L level, when the count value of the lower digit counter 1 changes from “7” to “0”, the clock in which the count value is changed from “7” to “0”. CLK is supplied to the 3-bit register 21 of the upper digit counter 2 as the clock CLKa through the clock gating control circuit 3, and the count value of the upper digit counter 2 (the count value indicated by the output signals Q3 to Q5) is incremented. Done. As a result, the output destination circuits of the output signals Q0 to Q5 operate and their functions can be confirmed.

  As described above, in this embodiment, only when the count value of the lower digit counter 1 is “7” and the carry from the lower digit counter 1 to the upper digit counter 2 is to be performed, the clock gating control circuit 3 The clock CLKa is supplied to the upper digit counter 2 via. Therefore, it is possible to keep power consumption low without performing unnecessary switching operation on the upper digit counter 2. In this embodiment, since the lower digit counter 1 to which a high frequency clock is applied is a ripple counter, the power consumption of the lower digit counter 1 is reduced, thereby reducing the power consumption of the entire 6-bit up counter. it can. In the present embodiment, only the clock gating control circuit 3 is interposed in the supply path of the clock CLK to the upper digit counter 2, and the lower digit counter 1 is not interposed. Therefore, the delay time from the clock CLK to the change timing of each output signal of the upper digit counter 2 can be shortened. In addition, according to the present embodiment, since the high-order digit counter 2 to which a low-frequency clock is applied is a synchronous counter, each output signal Q3 from the rising edge of the clock CLK while reducing the power consumption of the entire 6-bit up counter as much as possible. It is possible to reduce the variation of each delay time until the change timing of .about.Q5 and to keep the maximum value of the delay times low.

<Second Embodiment>
FIG. 4 is a circuit diagram showing a configuration of a counter according to the second embodiment of the present invention. In the first embodiment, the present invention is applied to an up counter. However, in the present embodiment, the present invention is applied to a down counter.

  In the lower digit counter 1 in the first embodiment, the output signals of the low active data output terminals of the flip-flops 11 and 12 are supplied to the selectors 17 and 18, but in the lower digit counter 1A in the present embodiment, the flip-flop The output signals at the high active data output terminals 11 and 12 are supplied to the selectors 17 and 18, and the lower digit counter 1A operates as a 3-bit down counter.

  In the upper digit counter 2 in the first embodiment, the 3-bit full adder 22 adds “+1” to the output data of the 3-bit register 21, but in the upper digit counter 2A in the present embodiment, the 3-bit full adder 22 The adder 22 adds “−1” to the output data of the 3-bit register 21, and the upper digit counter 2A operates as a 3-bit down counter.

In the clock gating control circuit 3 according to the present embodiment, the low active AND gate 31 has a count value of “0” when the output signals of the high active data output terminals of the flip-flops 11 to 13 are all at the L level. The enable signal EN1 is set to H level when a digit reduction is to be performed at the next rising edge of the clock CLK. Then, the clock gating control circuit 3 in the present embodiment passes the clock CLK when the carry-down occurs, and supplies the clock CLK to the upper digit counter 2A as the clock CLKa.
Also in this embodiment, the same effect as the first embodiment can be obtained.

<Third Embodiment>
FIG. 5 is a circuit diagram showing a configuration of a counter according to the third embodiment of the present invention. In the first and second embodiments, one counter is composed of two counters, a lower digit counter and an upper digit counter. In the present embodiment, one counter is composed of three counters.

  As shown in FIG. 5, the counter according to the present embodiment is inserted between the 3-bit counters 101 to 103, the clock gating control circuit 111 interposed between the counters 101 and 102, and the counters 102 and 103. And a clock gating control circuit 112.

  The counters 101 to 103 may all be up counters or all may be down counters. Each of the counters 101 to 103 may be a ripple counter or a synchronous counter.

  The clock CLK is directly given to the first-stage counter 101. The counter 101 repeats up-counting or down-counting in the range of “0” to “7” according to the clock CLK.

  The clock gating control circuit 111 sets the count value of the counter 101 to “7” in the case of up-counting and should carry, and in the case of down-counting, the count value of the counter 101 becomes “0”. When the digit is to be reduced, the clock CLK rising immediately after that is passed and supplied to the counter 102 as the clock CLKa. As a result, the counter 102 performs up-counting (carrying up) or down-counting (carrying down).

  The clock gating control circuit 112 counts down when the count value of the counter 101 is “7” in the case of up-counting and the count value of the counter 102 is “7” to carry. In this case, when the count value of the counter 101 becomes “0” and the count value of the counter 102 becomes “0” and the digit should be reduced, the clock CLK rising immediately after that is passed, and the counter is used as the clock CLKb. 103. As a result, the counter 103 performs up-counting (carrying up) or down-counting (carrying down).

  As described above, according to the present embodiment, the clocks are supplied to the counters 102 and 103 that count the upper digits only when the count value needs to be updated, and unnecessary clocks are not supplied otherwise. . Therefore, power consumption can be reduced. In the present embodiment, only the clock gating control circuit 111 is interposed in the supply path of the clock CLK to the counter 102, and the clock gating control circuit is provided in the supply path of the clock CLK to the counter 103. 112 is only interposed, and the lower digit counter is not interposed. Therefore, even when the number of bits representing the count value (9 bits in the example of FIG. 5) is large, the delay time from the clock CLK of each output signal of the counters 102 and 103 that count the upper digits is set. Can be shortened.

<Other embodiments>
The first to third embodiments of the present invention have been described above. However, the present invention may have other embodiments.

(1) For example, in the first and second embodiments described above, a 6-bit counter is divided into two 3-bit counters, and a clock gating control circuit is inserted between the 3-bit counters. The number of counters to be divided or the number of bits to be divided may be determined according to the allowable power consumption, the occupation area allowed for the counter in the semiconductor integrated circuit, and the like.

(2) In order to reduce power consumption, it is desirable that the first stage counter to which the clock with the highest frequency is given among the counters obtained by dividing one counter is a ripple counter. However, if the first stage counter is a ripple counter, the delay time from the clock of the output signal of the first stage counter (particularly, the most significant bit of the count value of the first stage counter) becomes longer. However, according to the present invention, the clock gating control circuit works to lower the frequency of the clock supplied to the second and subsequent counters and to reduce the power consumption of the second and subsequent counters. It is done. Therefore, when only the effect of reducing the power consumption of the counters after the second stage is sufficient, the first stage counter may be a synchronous counter, and the delay time of each bit of the first stage counter may be shortened. Further, all the counters obtained by dividing one counter may be used as the synchronous counter.

(3) In each of the above embodiments, a single counter is configured using a plurality of binary counters. However, a plurality of BCDs (Binary Coded Decimal; binary) that repeat count values in the range of “0” to “9” are used. A (decimal) counter may be used, and a clock gating control circuit may be inserted between each BCD counter.

It is a block diagram which shows the structure of the counter which is 1st Embodiment of this invention. 4 is a time chart showing waveforms of respective parts of the counter when the test signal TEST is at the L level in the embodiment. 6 is a time chart showing waveforms of respective parts of the counter when the test signal TEST is at the H level in the embodiment. It is a circuit diagram which shows the structure of the counter which is 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the counter which is 3rd Embodiment of this invention.

Explanation of symbols

1, 1A: Lower digit counter, 2, 2A: Upper digit counter, 3, 111, 112 ... Clock gating control circuit, 101-103 ... Counter, 11-13 ... Flip-flop, 14-16 ... Inverter, 17, 18 ... Selector, 19, 33 ... AND gate, 31 ... Low active AND gate, 32 ... Latch, 21 ... 3-bit register, 22 ... 3-bit full adder.

Claims (4)

A plurality of counters including a first-stage counter that counts the clock and a second-stage counter that counts the clock according to the occurrence of carry or carry-down in the previous-stage counter;
A clock gating control circuit that allows a clock to pass to the counter when a carry or a carry in the counter in the preceding stage of the counter is generated is connected to the second and subsequent counters in the plurality of counters. counter.   2. The counter according to claim 1, wherein a first-stage counter of the plurality of counters is a ripple counter.   3. The counter according to claim 1, wherein a counter other than a first-stage counter of the plurality of counters includes a synchronization counter. The counter according to claim 1, wherein all of the plurality of counters are synchronous counters.

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