JP3163808B2 - PLL circuit with double loop structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage-controlled oscillator (hereinafter, referred to as VCO) having a high frequency band and a wide band and high sensitivity.
The present invention relates to a PLL circuit for improving an N ratio, and more particularly to a PLL circuit used for a synthesizer device requiring a good spectrum.

[0002]

2. Description of the Related Art Conventionally, this kind of PLL circuit uses a digital phase comparator, amplifies and filters the phase detection voltage by a charge pump circuit, and uses it as a VCO tuning voltage. . FIG.
FIG. 1 is a block diagram showing a configuration of a conventional digital PLL circuit. In FIG. 5, reference numeral 1 denotes a digital phase comparator that compares the phases of two input digital signals and outputs a phase difference signal. Reference numeral 2 denotes an active low-pass filter that smoothes the phase difference signal. It is a charge pump that converts a waveform into a voltage waveform. The output of the charge pump 2 is supplied to a VCO as a tuning voltage. Reference numeral 3 denotes a VCO whose output frequency changes in response to a tuning voltage which is a DC voltage. Reference numeral 4 denotes a prescaler that divides an output oscillation signal obtained from the VCO 3 as a feedback signal, and reference numeral 5 denotes a reference signal generator that generates a reference signal.

In the configuration shown in FIG. 5, a digital phase comparator 1 detects a phase error between a reference signal and a divided feedback signal, and inputs a DC tuning voltage corresponding to the phase error to a VCO. By obtaining an output signal of a predetermined frequency, a digital PLL circuit is formed.

FIG. 6 is a block diagram showing a configuration of a conventional analog PLL circuit. In FIG. 6, reference numeral 11 denotes a multiplier (mixer) that multiplies two analog signals having different phases and outputs a phase error signal of the two signals.
Reference numeral 12 denotes a passive low-pass filter for removing high-frequency components. Reference numeral 13 denotes a VCO that oscillates according to the input tuning voltage. Reference numeral 14 denotes a prescaler that receives a tuning voltage and divides a feedback signal generated by a VCO, and 15 denotes a reference signal generator that generates a reference signal.

In the configuration of FIG. 6, the mixer 11
An analog reference signal from the reference signal generator 15 is multiplied by an analog feedback signal divided by the prescaler 14 to obtain a phase error signal corresponding to the phase difference and an input signal 2.
And a phase sum signal having a double frequency. These mixers 1
1 is supplied to the low-pass filter 12, where the carrier component of the phase error signal and the phase sum signal are removed.
A DC tuning voltage corresponding to the phase error is output. The tuning voltage is supplied to the VCO 13 to form an analog PLL circuit.

[0006]

However, both the digital phase comparison type and the analog phase comparison type have advantages and disadvantages from the viewpoint of controlling the synthesizer of the wide-band high-sensitivity VCO, and have a good C / N improvement. I was not able to satisfy both the ratio and the broadband lock. That is, in a digital PLL circuit, a sufficient C / N
On the other hand, a suppression ratio cannot be obtained. On the other hand, in an analog PLL circuit, since the output voltage of a mixer as a phase comparator is small, there is a problem that a wide-band pull-in state (lock) is difficult.

The present invention solves such a conventional problem, and has both advantages of analog phase control capable of improving C / N and digital phase control capable of locking in a wide band. It is an object of the present invention to provide a PLL circuit.

[0008]

In order to achieve the above object, the present invention provides a VCO whose output frequency changes according to an input DC voltage, a prescaler for dividing a feedback signal obtained from the VCO, A first distributor for distributing the divided feedback signal and transmitting first and second digital feedback signals, a reference signal generator for outputting a reference signal of a reference frequency, and distributing the reference signal A second distributor for transmitting a digital reference signal and an analog reference signal, a digital phase error detecting means for comparing the digital reference signal with the first digital feedback signal and transmitting a digital phase error signal; Synthesizing means for adding the digital phase error signal to an analog phase error signal obtained by comparing a reference signal and the digital feedback signal and transmitting a synthesized phase error signal; By removing high-frequency components of the synthesized phase error signal and a low pass filter delivering a DC voltage to be input to the VCO.

[0009]

The present invention has the following functions by the above-mentioned structure. That is, in the first stage of the PLL control, the VCO pull-in operation is started by the digital phase error signal having a large detection signal voltage, and after the pull-in operation is completed, the C / N ratio is increased by the analog phase error signal having high error detection accuracy. Starts the suppression operation.

Therefore, extremely accurate phase control is performed by the analog phase detection loop, and at the same time, C /
It has the effect of improving the N ratio.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention. In FIG. 1, reference numeral 21 denotes a reference signal generator for generating a reference signal, and reference numeral 22 denotes a distributor for distributing the reference signal. The distributor 22 has a function of outputting a digital reference signal (square wave) from the output D and an analog reference signal (sine wave) from the output A. Reference numeral 23 denotes a VCO whose oscillation frequency changes according to a supplied DC voltage, ie, a tuning voltage, and reference numeral 24 denotes a prescaler which divides the frequency of an output oscillation signal from the VCO 23 as a feedback signal. 25 distributes the feedback signal divided by the prescaler 24, and outputs the first digital feedback signal from the output D1;
The output D2 is a distributor for transmitting a second digital feedback signal.

Reference numeral 26 denotes a digital phase comparator which detects a phase difference between a digital reference signal from the distributor 22 and a first digital feedback signal from the distributor 25 and outputs a digital phase error signal. Reference numeral 27 denotes a charge pump for removing a carrier component of the phase error signal and outputting a DC voltage. Digital phase comparator 26 and charge pump 27
Constitutes a digital phase error detecting means. Reference numeral 28 denotes a DC-isolated mixer, the RF port of which is supplied with an analog reference signal from the distributor 22.
A second digital feedback signal from the distributor 25 is supplied to the LO port. Further, a DC signal from the charge pump 27, that is, a digital phase error signal is supplied to a ground terminal which is normally set to GND. Reference numeral 29 denotes a low-pass filter for removing a high-frequency component and a noise component of the output signal from the mixer 28. The output signal is supplied to the VCO 23 and used as a tuning voltage.

Next, the operation of the configuration shown in FIG. 1 will be described. FIG. 2 is a signal waveform diagram showing a phase relationship between the analog reference signal Vs supplied to the RF port and the LO port of the mixer 28 and the second digital feedback signal Vf.

FIG. 2A shows the analog reference signal Vs and the second reference signal.
3 shows that the phases of the digital feedback signal Vf of FIG. In this case, the timing of the positive maximum value of the analog reference signal Vs coincides with the rising timing of the second digital feedback signal Vf, and the timing of the negative maximum value of the analog reference signal Vs is the second maximum value. At the falling timing of the digital feedback signal Vf. Therefore, the analog reference signal Vs during the period when the pulse of the second digital feedback signal Vf is at the high level has a positive portion P equal to a negative portion N as indicated by hatching in FIG. Becomes zero.

FIG. 2B shows a state in which the phase is shifted by θ. In this case, the pulse of the second digital feedback signal Vf is the analog reference signal V during the high level period.
As shown by hatching in the figure, s is larger in the positive part P than in the negative part N, and thus the integral value in this period takes a positive value. That is, the integral value (the value including the sign)
Will vary according to the amount of phase shift. Therefore, by integrating the output signal from the IF port of the mixer 28 with the low-pass filter 29, the tuning voltage, which is an analog phase error signal corresponding to the phase error, becomes equal to VC.
It will be supplied to O23.

FIG. 3A shows how to use the conventional mixer shown in FIG. 6, in which the GND terminal is grounded. FIG. 3B shows a signal supplied to the mixer 28 applied to the present invention. The DC phase error signal Vc output from the charge pump 27 is supplied to the GND terminal. Therefore, a composite phase error signal in which the digital phase error signal is superimposed on the analog phase error signal is supplied to the VCO 23.

Thus, by forming a double feedback loop of an analog system and a digital system in the PLL circuit, an analog phase error signal and a digital phase error signal are synthesized and used as a tuning voltage for a VCO. I do. As a result, a good C / N ratio can be obtained by the analog phase error signal, and a wide band locking operation can be performed by the digital phase error signal.

The point of the present embodiment is that the analog phase comparator has an RF port, a LO port, and a mixer 28 having an IF port that is DC-isolated.
In addition, since it is not necessary to amplify the detection voltage, the active element is unnecessary, the disturbance noise is suppressed only to the switching noise of the mixer 28, and further, the detection sensitivity of the mixer 28 is maximized. Mixer 28
When the PLL operation is completed, the lock phase of the digital phase comparator 26 is made variable so that the relationship shown in FIG.

FIG. 4 is a block diagram showing a second embodiment of the present invention. In the configuration of the second embodiment, the same components as those of the first embodiment are denoted by the same reference numerals as those of FIG. 1, and the description thereof is omitted.

In FIG. 4A, reference numeral 30 denotes a reference signal from the reference signal generator 21 and two analog reference signals and 1
This is a distributor that distributes the digital reference signals. Reference numeral 31 denotes a distributor for distributing the signal divided by the prescaler 24 into three digital reference signals, a first digital signal, a second digital signal, and a third digital signal. Reference numeral 32 denotes a double-balanced mixer having a two-stage configuration in which an isolator is provided in the form of DC. Reference numeral 32a denotes a first mixer. By multiplying by a digital feedback signal, a first analog phase error signal is obtained, and a digital phase error signal obtained from the charge pump 27 is added to the first analog phase error signal to output a first combined phase error signal. Also,
32b is a second mixer, which multiplies the second analog reference signal output from each of the distributors 30 and 31 by the third digital feedback signal to obtain a second analog phase error signal. And a second combined phase error signal is output.

FIG. 4B shows a circuit configuration of the mixer 32. A digital phase error signal VC is supplied to the conventional GND terminal 32c.

The feature of the second embodiment is that the mixer has a two-stage structure. In order to lower the switching noise of the mixer 32 to the utmost and further suppress the C / N,
It is necessary to reduce the level of the RF and LO signals applied to the mixer, and as a result, the detection sensitivity is reduced. In order to compensate for this decrease, the mixer has a two-stage configuration.

[0024]

As is apparent from the above embodiments, the present invention provides a digital phase comparison type PLL and an analog phase comparison type P
This compensates for the drawbacks of the LL, and has an effect that a good C / N ratio can be obtained and a wide-band lock operation can be performed. Further, there is an effect that noise in the vicinity of the oscillation spectrum at the time of free run in which the VCO is generated can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a PLL circuit of the present invention.

2 (a) is a signal waveform diagram showing the relationship when the phases of the signals of the RF port and the LO port in FIG. 1 match, and FIG. 2 (b) is out of phase with the signals of the RF port and the LO port in FIG. Signal waveform diagram showing the relationship

FIG. 3A is a diagram showing a configuration when a mixer is used in a conventional method. FIG. 3A is a diagram showing a configuration when a mixer is used in a method of the present invention.

4A is a block diagram showing a configuration of a PLL circuit according to a second embodiment of the present invention; FIG. 4B is a diagram showing a circuit configuration of the mixer of FIG. 4A;

FIG. 5 is a block diagram showing a configuration of a conventional digital PLL circuit.

FIG. 6 is a block diagram showing a configuration of a conventional analog PLL circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 21 reference signal generator 22 second distributor 23 VCO 24 prescaler 25 first distributor 26 digital phase comparator 27 charge pump 28 mixer 29 low-pass filter 30 distributor 31 distributor 32 double balance mixer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03L 7/22

Claims (3)

(57) [Claims] 1. A VCO whose output frequency changes in accordance with an input DC voltage, a prescaler that divides a feedback signal obtained from the VCO, and a first and a second that distribute the divided feedback signal. A first divider for transmitting a digital feedback signal, a reference signal generator for outputting a reference signal of a reference frequency, and a second divider for distributing the reference signal and transmitting a digital reference signal and an analog reference signal And a digital phase error detecting means for comparing the digital reference signal with the first digital feedback signal to transmit a digital phase error signal; and comparing the analog reference signal with the second digital feedback signal. Synthesizing means for adding the digital phase error signal to the obtained analog phase error signal to send out a composite phase error signal; PL having a double-loop structure having a low-pass filter for sending a DC voltage input to a CO
L circuit. 2. A first divider for distributing the divided feedback signal and transmitting first, second, and third digital feedback signals, and distributing the reference signal to a digital reference signal and a digital reference signal. A second transmitting the first and second analog reference signals;
And a first combined phase error signal obtained by adding the digital phase error signal to a first analog phase error signal obtained by comparing the first analog reference signal and the second digital feedback signal. And a second analog phase error signal obtained by comparing the second analog reference signal with a third digital feedback signal.
2. A PLL circuit having a double loop structure according to claim 1, further comprising second synthesizing means for adding said analog phase error signal and transmitting a second synthesized phase error signal. 3. The PLL circuit having a double loop structure according to claim 1, wherein said digital phase error detecting means is supplied with said digital phase error signal to a ground terminal.