JP2814876B2 - PLL circuit with triple loop structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION In a synthesizer device which requires a wide band and high sensitivity VCO C / N ratio in a high frequency band, its reference frequency cannot be selected high due to restrictions on channel space and the like. The present invention relates to a PLL circuit having a triple loop structure that enables a good frequency spectrum to be obtained even below.

[0002]

2. Description of the Related Art Conventionally, this kind of PLL circuit uses a digital phase comparator, amplifies and filters its phase detection voltage by a charge pump circuit, and uses it as a VCO tuning voltage. . FIG.
FIG. 1 is a block diagram showing a configuration of a conventional digital PLL circuit. In FIG. 2, reference numeral 1 denotes a digital phase comparator which compares the phases of two input digital signals and outputs a phase difference signal. Reference numeral 2 denotes a smoothing unit for the phase difference signal by an active low-pass filter to obtain a pulse waveform. Is a charge pump for converting a voltage into a voltage waveform. The output of the charge pump 2 is supplied to a VCO as a tuning voltage. Reference numeral 3 denotes a VCO whose output frequency changes in response to a tuning voltage which is a DC voltage. Reference numeral 4 denotes a prescaler that divides an output oscillation signal obtained from the VCO 3 as a feedback signal, and reference numeral 5 denotes a reference signal generator that generates a reference signal.

In the configuration shown in FIG. 2, a digital phase comparator 1 detects a phase error between a reference signal and a divided feedback signal, and inputs a DC tuning voltage corresponding to the phase error to a VCO. By obtaining an output signal of a predetermined frequency, a digital PLL circuit is formed.

FIG. 3 is a block diagram showing a configuration of a conventional analog PLL circuit. In FIG. 3, reference numeral 11 denotes a mixer (multiplier) that multiplies two analog signals having different phases and outputs a phase error signal of the two signals. Reference numeral 12 denotes a passive low-pass filter for removing high-frequency components. Reference numeral 13 denotes a VCO that oscillates according to the input tuning voltage. 14 receives the tuning voltage and
A prescaler that divides the feedback signal generated by O,
Reference numeral 15 denotes a reference signal generator that generates a reference signal.

In the configuration shown in FIG. 3, the mixer 11
An analog reference signal from the reference signal generator 15 is multiplied by an analog feedback signal divided by the prescaler 14 to obtain a phase error signal corresponding to the phase difference and an input signal 2.
And a phase sum signal having a double frequency. These mixers 1
The output of 1 is supplied to the low-pass filter 12, where the carrier component of the phase error signal and the phase sum signal are removed, and a DC tuning voltage corresponding to the phase error is output. The tuning voltage is supplied to the VCO 13 to form an analog PLL circuit.

[0006]

However, in the above-mentioned conventional PLL device, both the digital phase comparison type and the analog phase comparison type have advantages and disadvantages from the viewpoint of controlling the synthesizer of the wide-band high-sensitivity VCO, and have a good C / N ratio.
There was a problem that both the ratio and the broadband lock could not be satisfied. In addition, since the maximum value of the comparison frequency is determined by the restriction of the desired lock frequency from the channel space, there is also a problem that a sufficient bottleneck is obtained from the viewpoint of C / N suppression and sufficient performance cannot be obtained. Was.

The present invention solves such a conventional problem, and has both advantages of analog phase control capable of improving the C / N ratio and digital phase control capable of performing wide-band lock. It is another object of the present invention to provide an ideal PLL circuit since the comparison frequency can be increased in a pseudo manner.

[0008]

In order to achieve the above object, a PLL circuit having a triple loop structure according to the present invention comprises a VCO whose output frequency changes in accordance with an input DC control voltage.
Higher frequency dividing means for dividing a feedback signal obtained from the VCO to generate a high-frequency first digital feedback signal; and dividing the first digital feedback signal to generate a low-frequency second digital feedback signal. Lower frequency dividing means for generating a feedback signal;
A reference signal generator for generating an analog reference signal and a digital reference signal; a multiplying means for multiplying the analog reference signal to generate a high-frequency analog reference signal;
First phase error detection means for comparing the phases of the digital feedback signal and the digital reference signal to generate a first phase error signal; and detecting the phase of the second digital feedback signal and the analog reference signal. A second phase error detecting means for adding the first phase error signal to a phase error signal obtained by comparison and extracting a low-frequency component to generate a first combined phase error signal; Adding a second combined phase error signal to a phase error signal obtained by comparing the phase of a digital feedback signal with the phase of the high-frequency analog reference signal, extracting a low-frequency component, and setting the third frequency as the DC control voltage; And phase error detecting means.

[0009]

The present invention has the following functions by the above-mentioned structure. That is, in the first stage of the PLL control, since the output levels of the phase error signals obtained from the second and third phase error detecting means are extremely small, the VCO is generated by the phase error signal obtained from the first phase error detecting means.
It takes on the retraction operation. When the lock voltage is determined by this pull-in operation, the output frequency of the VCO is first guided to a band close to the desired frequency. Thereafter, the output sensitivity and accuracy of the phase error signal obtained from the second phase error detection means become higher than the sensitivity and accuracy of the phase error signal from the first phase error detection means. PLL control is performed by the first combined phase error signal from the means.

After that, the locked state is maintained by the first combined phase error signal, and when it is desired to further increase the phase error detection sensitivity, the reference level at which the detection sensitivity and the detection accuracy of the detected phase error are further increased. PLL control is performed by a third phase error signal having a high frequency.

Therefore, it is possible to perform PLL control utilizing the advantages of digital phase detection in the VCO pull-in operation and taking advantage of the high-precision analog phase after the pull-in is completed. Further, the third phase error detection means for detecting a phase error at a frequency higher than the frequency of the reference signal can perform extremely accurate phase control, and has an effect of improving the C / N ratio of the VCO.

[0012]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 1, reference numeral 21 denotes a reference signal generator for generating a reference signal, and reference numeral 22 denotes a distributor for distributing the reference signal. The distributor 22 has a function of outputting a digital reference signal (square wave) from the output D and an analog reference signal (sine wave) from the output A. Reference numeral 23 denotes a VCO whose oscillation frequency changes in accordance with a supplied DC control voltage, ie, a tuning voltage, and 24 divides an output oscillation signal from the VCO 23 as a feedback signal and outputs a frequency higher than the frequency of the reference signal. , An upper programmable counter as an upper frequency dividing means for generating a first digital feedback signal. Reference numeral 25 denotes a lower-order frequency dividing unit for further dividing the first digital feedback signal divided by the programmable counter 24 to generate a second digital feedback signal having a lower frequency than the first digital feedback signal. Is a programmable counter. Reference numeral 26 denotes a distributor for distributing and outputting the second digital feedback signal output from the frequency divider by the lower programmable counter 25.

Reference numeral 27 denotes a digital phase comparator which detects a phase difference between a digital reference signal from the distributor 22 and a second digital feedback signal from the distributor 26 and outputs a digital phase error signal. A charge pump 28 amplifies and smoothes this phase error signal, removes its carrier component, and outputs a DC voltage. Digital phase comparator 27 and charge pump 28 constitute first phase error detecting means.

Reference numeral 29 denotes a lower-order mixer which is DC-isolated. Its RF port is supplied with an analog reference signal from the distributor 22, and its LO port is supplied with a second digital feedback signal from the distributor 26. Supplied. Further, a DC signal from the charge pump 28, that is, a digital phase error signal is supplied to a terminal 29a which is normally set to GND. Therefore, the output port I of the lower mixer 29 is
From the F port, the digital phase error signal is superimposed on the phase error signal between the analog reference signal and the second digital feedback signal, and output as a first combined phase error signal. Reference numeral 30 denotes a low-pass filter that removes a high-frequency component and a noise component of the first phase error signal from the lower mixer 29. The lower mixer 29 and the low-pass filter 30 constitute a second phase error detecting means.

Numeral 31 denotes a frequency multiplier for converting the analog reference signal obtained from the distributor 22 into a high-frequency analog reference signal containing the same frequency component as the output frequency of the higher-order programmable counter 24. Reference numeral 32 denotes a band-pass filter that passes the same frequency component as the output frequency of the higher-order programmable counter 24. This bandpass filter 32 limits the spectrum to a continuous spectrum corresponding to the desired lock frequency. An amplifier 33 amplifies the high-frequency analog reference signal from the band-pass filter 32.

Numeral 34 denotes a DC-isolated upper mixer similar to the lower mixer 29. The RF port is supplied with a high-frequency analog reference signal amplified to a predetermined level by an amplifier 33, and the LO port is supplied to an LO port. A first digital feedback signal, ie, a high-frequency digital feedback signal, is supplied from the upper programmable counter 24. Also,
A low-pass filter 3 is connected to a terminal 34a which is normally set to GND.
A first combined phase error signal from 0 is provided.

Therefore, from the IF port, which is the output port of the mixer 34, the first combined phase error signal is superimposed on the phase error signal between the harmonic analog reference signal and the second digital feedback signal, and Is output as a combined phase error signal. Reference numeral 35 denotes a low-pass filter for removing a high-frequency component and a noise component of the second combined phase error signal. The second combined phase error signal output from the low-pass filter 35 is a VCO2
3 is fed back. The upper mixer 34 and the low-pass filter 35 constitute a third phase error detecting means.

As described above, according to the present embodiment, the digital phase comparison control loop which is the first loop by the first phase error detecting means, and the lower order which is the second loop by the second phase error detecting means. A triple loop is formed by the phase comparison mixer control loop and the higher-order phase comparison mixer control loop, which is the third loop by the third phase error detection means.

Next, the operation of the above embodiment will be described. PL
In the first stage of the L control, since the output level of the phase error signal obtained from the mixer 29 and the mixer 34 is extremely small, the VCO pull-in operation is started by the phase error signal obtained from the charge pump 28. When the lock voltage is determined to some extent by this pull-in operation, the output frequency of the VCO 23 is first guided to a band close to the desired frequency. After that, since the output level of the phase error signal obtained from the mixer 29 becomes higher than the level of the phase error signal from the charge pump 28, PLL control is performed using the first combined phase error signal from the low-pass filter 30.

After that, the locked state is maintained by the first combined phase error signal, and when it is desired to further increase the phase error detection sensitivity, the reference level at which the detection sensitivity and the detection accuracy of the detected phase error become higher. High frequency second
PLL control is performed by the phase error signal of.

In this case, in order to avoid the hunting operation of each loop, a difference is provided between the detection sensitivities, or the cutoff frequency of the filters 28, 30 and 35 connected to the output port of each loop is different. It is necessary to provide.

For example, the amplification degree of the charge pump 28 is set to the maximum, the response is set to be extremely slow, the low-pass filter 30 slightly increases the response, the detection sensitivity is set to the maximum, and the low-pass filter 35 sets the cutoff frequency to the side band. It is preferable that the control voltage is increased to the maximum value and the control voltage width is decreased instead.

Next, a specific example will be described from the viewpoint of the frequency spectrum. It is assumed that the oscillation frequency band of the VCO 23 is 2 GHz from 4.4 GHz to 6.4 GHz.
Further, the frequency division ratio setting of the upper programmable counter 24 is set to 1/8, and the frequency division ratio setting of the lower programmable counter is set to 1/167 to 1/117.
Assuming that the reference frequency is 4.795 MHz, the following operation is performed.

A digital phase comparison control loop as a first loop and a lower phase comparison mixer control loop as a second loop operate at a comparison frequency of 4.795 MHz, and the division ratio of the lower programmable counter is 1/117. in the case of,
Since the frequency division ratio of the upper programmable counter is 1/8, the lock frequency of the VCO 23 is determined by the following equation.

4.795 MHz × 117 × 8 = 4.48812 GHz In this case, the comparison frequency of the upper mixer 34 is 4.48812 / 8 = 561.015 MHz as shown in the following equation. In this case, 4.7 generated by the multiplier 31 is used.
In the continuous spectrum at intervals of 95 MHz, 117 times higher frequency will be used.

In the second combined phase error signal output from the IF port of the upper mixer 34, a low-pass filter constant is applied to a filter constant that allows only the DC voltage at the time of lock completion to pass and does not pass a high frequency that is an integral multiple of 4.795 MHz. Filter 3
If 5 is set, the spectrum other than the desired high frequency is ignored.

[0027]

As is apparent from the above-described embodiment, the present invention makes up for the disadvantages of the digital phase comparison type PLL and the analog phase comparison type PLL by configuring a triple detection loop, and makes it possible to set the comparison frequency to a desired value. The effect of increasing the detection sensitivity can be obtained by increasing the lock frequency channel space without coarsening. Further, an effect of reducing noise near the oscillation spectrum at the time of free-run in which the VCO occurs can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a PLL circuit according to the present invention.

FIG. 2 is a configuration block diagram of a conventional digital PLL circuit.

FIG. 3 is a configuration block diagram of a conventional analog PLL circuit.

[Explanation of symbols]

 21 Reference Signal Generator 22 Divider 23 VCO 24 Upper Programmable Counter 25 Lower Programmable Counter 26 Distributor 27 Digital Phase Comparator 28 Charge Pump 29 Lower Mixer 30 Low-Pass Filter 31 Multiplier 32 Band-Pass Filter 33 Amplifier 34 Upper Mixer 35 Low-pass filter

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-6-188732 (JP, A) JP-A-6-303131 (JP, A) JP-A-3-101520 (JP, A) JP-A-61- 184001 (JP, A) JP-A-1-112572 (JP, A) JP-A-1-125024 (JP, A) JP-A-3-186017 (JP, A) JP-A-2-149018 (JP, A) JP-A-1-238223 (JP, A) JP-A-2-112030 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) H03L 7/22 H03L 7/087

Claims (1)

(57) [Claims] 1. A VCO whose output frequency changes in accordance with an input DC control voltage, and a high-order frequency dividing means for dividing a feedback signal obtained from the VCO to generate a high-frequency first digital feedback signal. Lower frequency dividing means for dividing the first digital feedback signal to generate a low-frequency second digital feedback signal; a reference signal generator for generating an analog reference signal and a digital reference signal; Multiplying means for multiplying a signal to generate a harmonic analog reference signal, and a first phase error for generating a first phase error signal by comparing the phases of the second digital feedback signal and the digital reference signal Detecting means for adding the first phase error signal to a phase error signal obtained by comparing the phases of the second digital feedback signal and the analog reference signal, and A second phase error detecting means for extracting and generating a first combined phase error signal; and a second phase error signal obtained by comparing the phase of the first digital feedback signal with the phase of the high-frequency analog reference signal. 3. A PLL circuit having a triple loop structure, comprising: a third phase error detecting means for adding the two combined phase error signals and extracting a low-frequency component to obtain the DC control voltage.